去除大部分类型错误
This commit is contained in:
Liphen
parent
a8fe6f7a9c
commit
a1f7cd92d0
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@ -1,144 +1,143 @@
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// package cpu
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package cpu
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// import chisel3._
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// import chisel3.util._
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// import chisel3.internal.DontCareBinding
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import chisel3._
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import chisel3.util._
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import chisel3.internal.DontCareBinding
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// import defines._
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// import defines.Const._
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// import pipeline.fetch._
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// import pipeline.decoder._
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// import pipeline.execute._
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// import pipeline.memory._
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// import pipeline.writeback._
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// import ctrl._
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// import mmu._
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// import chisel3.util.experimental.decode.decoder
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// import cpu.pipeline.fetch.InstFifo
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import defines._
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import defines.Const._
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import pipeline.fetch._
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import pipeline.decoder._
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import pipeline.execute._
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import pipeline.memory._
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import pipeline.writeback._
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import ctrl._
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import mmu._
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import chisel3.util.experimental.decode.decoder
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import cpu.pipeline.fetch.InstFifo
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// class Core(implicit val config: CpuConfig) extends Module {
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// val io = IO(new Bundle {
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// val ext_int = Input(UInt(EXT_INT_WID.W))
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// val inst = new Cache_ICache()
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// val data = new Cache_DCache()
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// val debug = new DEBUG()
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// })
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class Core(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val ext_int = Input(new ExtInterrupt())
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val inst = new Cache_ICache()
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val data = new Cache_DCache()
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val debug = new DEBUG()
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})
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// val ctrl = Module(new Ctrl()).io
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// val fetchUnit = Module(new FetchUnit()).io
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// val bpu = Module(new BranchPredictorUnit()).io
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// val instFifo = Module(new InstFifo()).io
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// val decoderUnit = Module(new DecoderUnit()).io
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// val regfile = Module(new ARegFile()).io
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// val executeStage = Module(new ExecuteStage()).io
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// val executeUnit = Module(new ExecuteUnit()).io
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// val csr = Module(new Csr()).io
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// val memoryStage = Module(new MemoryStage()).io
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// val memoryUnit = Module(new MemoryUnit()).io
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// val writeBackStage = Module(new WriteBackStage()).io
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// val writeBackUnit = Module(new WriteBackUnit()).io
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val ctrl = Module(new Ctrl()).io
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val fetchUnit = Module(new FetchUnit()).io
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val bpu = Module(new BranchPredictorUnit()).io
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val instFifo = Module(new InstFifo()).io
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val decoderUnit = Module(new DecoderUnit()).io
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val regfile = Module(new ARegFile()).io
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val executeStage = Module(new ExecuteStage()).io
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val executeUnit = Module(new ExecuteUnit()).io
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val csr = Module(new Csr()).io
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val memoryStage = Module(new MemoryStage()).io
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val memoryUnit = Module(new MemoryUnit()).io
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val writeBackStage = Module(new WriteBackStage()).io
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val writeBackUnit = Module(new WriteBackUnit()).io
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// ctrl.instFifo.has2insts := !(instFifo.empty || instFifo.almost_empty)
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// ctrl.decoderUnit <> decoderUnit.ctrl
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// ctrl.executeUnit <> executeUnit.ctrl
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// ctrl.memoryUnit <> memoryUnit.ctrl
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// ctrl.writeBackUnit <> writeBackUnit.ctrl
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// ctrl.cacheCtrl.iCache_stall := io.inst.stall
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// ctrl.cacheCtrl.dCache_stall := io.data.stall
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ctrl.instFifo.has2insts := !(instFifo.empty || instFifo.almost_empty)
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ctrl.decoderUnit <> decoderUnit.ctrl
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ctrl.executeUnit <> executeUnit.ctrl
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ctrl.memoryUnit <> memoryUnit.ctrl
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ctrl.writeBackUnit <> writeBackUnit.ctrl
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ctrl.cacheCtrl.iCache_stall := io.inst.stall
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ctrl.cacheCtrl.dCache_stall := io.data.stall
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// fetchUnit.memory <> memoryUnit.fetchUnit
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// fetchUnit.execute <> executeUnit.fetchUnit
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// fetchUnit.decoder <> decoderUnit.fetchUnit
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// fetchUnit.instFifo.full := instFifo.full
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// fetchUnit.iCache.inst_valid := io.inst.valid
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// io.inst.addr(0) := fetchUnit.iCache.pc
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// io.inst.addr(1) := fetchUnit.iCache.pc_next
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// for (i <- 2 until config.instFetchNum) {
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// io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U
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// }
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fetchUnit.memory <> memoryUnit.fetchUnit
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fetchUnit.execute <> executeUnit.fetchUnit
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fetchUnit.decoder <> decoderUnit.fetchUnit
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fetchUnit.instFifo.full := instFifo.full
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fetchUnit.iCache.inst_valid := io.inst.valid
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io.inst.addr(0) := fetchUnit.iCache.pc
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io.inst.addr(1) := fetchUnit.iCache.pc_next
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for (i <- 2 until config.instFetchNum) {
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io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U
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}
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// bpu.decoder.ena := ctrl.decoderUnit.allow_to_go
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// bpu.decoder.op := decoderUnit.bpu.decoded_inst0.op
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// bpu.decoder.inst := decoderUnit.bpu.decoded_inst0.inst
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// bpu.decoder.rs1 := decoderUnit.bpu.decoded_inst0.reg1_raddr
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// bpu.decoder.rs2 := decoderUnit.bpu.decoded_inst0.reg2_raddr
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// bpu.decoder.pc := decoderUnit.bpu.pc
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// bpu.decoder.pc_plus4 := decoderUnit.bpu.pc + 4.U
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// bpu.decoder.pht_index := decoderUnit.bpu.pht_index
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// decoderUnit.bpu.update_pht_index := bpu.decoder.update_pht_index
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// bpu.execute <> executeUnit.bpu
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// decoderUnit.bpu.branch_inst := bpu.decoder.branch_inst
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// decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch
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// decoderUnit.bpu.branch_target := bpu.decoder.branch_target
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bpu.decoder.ena := ctrl.decoderUnit.allow_to_go
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bpu.decoder.op := decoderUnit.bpu.decoded_inst0.op
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bpu.decoder.inst := decoderUnit.bpu.decoded_inst0.inst
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bpu.decoder.rs1 := decoderUnit.bpu.decoded_inst0.reg1_raddr
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bpu.decoder.rs2 := decoderUnit.bpu.decoded_inst0.reg2_raddr
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bpu.decoder.pc := decoderUnit.bpu.pc
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bpu.decoder.pc_plus4 := decoderUnit.bpu.pc + 4.U
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bpu.decoder.pht_index := decoderUnit.bpu.pht_index
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decoderUnit.bpu.update_pht_index := bpu.decoder.update_pht_index
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bpu.execute <> executeUnit.bpu
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decoderUnit.bpu.branch_inst := bpu.decoder.branch_inst
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decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch
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decoderUnit.bpu.branch_target := bpu.decoder.branch_target
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// instFifo.do_flush := ctrl.decoderUnit.do_flush
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// instFifo.icache_stall := io.inst.stall
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// instFifo.ren <> decoderUnit.instFifo.allow_to_go
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// decoderUnit.instFifo.inst <> instFifo.read
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instFifo.do_flush := ctrl.decoderUnit.do_flush
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instFifo.icache_stall := io.inst.stall
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instFifo.ren <> decoderUnit.instFifo.allow_to_go
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decoderUnit.instFifo.inst <> instFifo.read
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// for (i <- 0 until config.instFetchNum) {
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// instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i)
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// bpu.instBuffer.pc(i) := instFifo.write(i).pc
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// instFifo.wen(i) := io.inst.valid(i)
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// instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U
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// instFifo.write(i).inst := io.inst.rdata
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// }
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for (i <- 0 until config.instFetchNum) {
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instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i)
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bpu.instBuffer.pc(i) := instFifo.write(i).pc
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instFifo.wen(i) := io.inst.valid(i)
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instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U
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instFifo.write(i).inst := io.inst.rdata(i)
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}
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// decoderUnit.instFifo.info.empty := instFifo.empty
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// decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty
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// decoderUnit.regfile <> regfile.read
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// for (i <- 0 until (config.fuNum)) {
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// decoderUnit.forward(i).exe := executeUnit.decoderUnit.forward(i).exe
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// decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg
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// decoderUnit.forward(i).mem := memoryUnit.decoderUnit(i)
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// }
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// decoderUnit.csr <> csr.decoderUnit
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// decoderUnit.executeStage <> executeStage.decoderUnit
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decoderUnit.instFifo.info.empty := instFifo.empty
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decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty
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decoderUnit.regfile <> regfile.read
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for (i <- 0 until (config.fuNum)) {
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decoderUnit.forward(i).exe := executeUnit.decoderUnit.forward(i).exe
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decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg
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decoderUnit.forward(i).mem := memoryUnit.decoderUnit(i)
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}
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decoderUnit.csr <> csr.decoderUnit
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decoderUnit.executeStage <> executeStage.decoderUnit
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// executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush_req ||
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// !decoderUnit.executeStage.inst0.ex.bd && ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go ||
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// !ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go
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// executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush_req ||
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// (ctrl.executeUnit.do_flush && decoderUnit.executeStage.inst1.allow_to_go) ||
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// (ctrl.executeUnit.allow_to_go && !decoderUnit.executeStage.inst1.allow_to_go)
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// executeStage.ctrl.inst0_allow_to_go := ctrl.executeUnit.allow_to_go
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executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush_req ||
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ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go ||
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!ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go
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executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush_req ||
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(ctrl.executeUnit.do_flush && decoderUnit.executeStage.inst1.allow_to_go) ||
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(ctrl.executeUnit.allow_to_go && !decoderUnit.executeStage.inst1.allow_to_go)
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executeStage.ctrl.inst0_allow_to_go := ctrl.executeUnit.allow_to_go
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// executeUnit.decoderUnit.inst0_bd := decoderUnit.executeStage.inst0.ex.bd
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// executeUnit.executeStage <> executeStage.executeUnit
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// executeUnit.csr <> csr.executeUnit
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// executeUnit.memoryStage <> memoryStage.executeUnit
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executeUnit.executeStage <> executeStage.executeUnit
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executeUnit.csr <> csr.executeUnit
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executeUnit.memoryStage <> memoryStage.executeUnit
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// memoryStage.ctrl.allow_to_go := ctrl.memoryUnit.allow_to_go
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// memoryStage.ctrl.clear := ctrl.memoryUnit.do_flush
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memoryStage.ctrl.allow_to_go := ctrl.memoryUnit.allow_to_go
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memoryStage.ctrl.clear := ctrl.memoryUnit.do_flush
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// memoryUnit.memoryStage <> memoryStage.memoryUnit
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// memoryUnit.csr <> csr.memoryUnit
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// memoryUnit.writeBackStage <> writeBackStage.memoryUnit
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memoryUnit.memoryStage <> memoryStage.memoryUnit
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memoryUnit.csr <> csr.memoryUnit
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memoryUnit.writeBackStage <> writeBackStage.memoryUnit
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// csr.ctrl.exe_stall := !ctrl.executeUnit.allow_to_go
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// csr.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go
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// csr.ext_int := io.ext_int
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csr.ctrl.exe_stall := !ctrl.executeUnit.allow_to_go
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csr.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go
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csr.ext_int := io.ext_int
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// memoryUnit.dataMemory.in.rdata := io.data.rdata
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// io.data.en := memoryUnit.dataMemory.out.en
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// io.data.size := memoryUnit.dataMemory.out.rlen
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// io.data.write := memoryUnit.dataMemory.out.wen
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// io.data.wdata := memoryUnit.dataMemory.out.wdata
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// io.data.addr := memoryUnit.dataMemory.out.addr
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memoryUnit.dataMemory.in.rdata := io.data.rdata
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io.data.en := memoryUnit.dataMemory.out.en
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io.data.size := memoryUnit.dataMemory.out.rlen
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io.data.write := memoryUnit.dataMemory.out.wen
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io.data.wdata := memoryUnit.dataMemory.out.wdata
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io.data.addr := memoryUnit.dataMemory.out.addr
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// writeBackStage.memoryUnit <> memoryUnit.writeBackStage
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// writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go
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// writeBackStage.ctrl.clear := ctrl.writeBackUnit.do_flush
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writeBackStage.memoryUnit <> memoryUnit.writeBackStage
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writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go
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writeBackStage.ctrl.clear := ctrl.writeBackUnit.do_flush
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// writeBackUnit.writeBackStage <> writeBackStage.writeBackUnit
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// writeBackUnit.ctrl <> ctrl.writeBackUnit
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// regfile.write <> writeBackUnit.regfile
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writeBackUnit.writeBackStage <> writeBackStage.writeBackUnit
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writeBackUnit.ctrl <> ctrl.writeBackUnit
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regfile.write <> writeBackUnit.regfile
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// io.debug <> writeBackUnit.debug
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io.debug <> writeBackUnit.debug
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// // io.inst.fence_i := executeUnit.executeStage.inst0.inst_info.ifence
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// // io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.dfence
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// io.inst.en := !instFifo.full
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// io.inst.ready := !ctrl.fetchUnit.allow_to_go
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// io.data.ready := !ctrl.memoryUnit.allow_to_go
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// }
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// io.inst.fence_i := executeUnit.executeStage.inst0.inst_info.ifence
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// io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.dfence
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io.inst.en := !instFifo.full
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io.inst.ready := !ctrl.fetchUnit.allow_to_go
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io.data.ready := !ctrl.memoryUnit.allow_to_go
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}
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@ -1,14 +1,14 @@
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// import cpu._
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// import circt.stage._
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import cpu._
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import circt.stage._
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// object Elaborate extends App {
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// implicit val config = new CpuConfig()
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// def top = new PuaCpu()
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// val useMFC = false // use MLIR-based firrtl compiler
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// val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
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// if (useMFC) {
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// (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
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// } else {
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// (new chisel3.stage.ChiselStage).execute(args, generator)
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// }
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// }
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object Elaborate extends App {
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implicit val config = new CpuConfig()
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def top = new PuaCpu()
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val useMFC = false // use MLIR-based firrtl compiler
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val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
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if (useMFC) {
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(new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
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} else {
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(new chisel3.stage.ChiselStage).execute(args, generator)
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}
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}
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@ -1,23 +1,23 @@
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// import chisel3._
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// import chisel3.util._
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// import cache._
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// import cpu._
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// import cpu.defines._
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import chisel3._
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import chisel3.util._
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import cache._
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import cpu._
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import cpu.defines._
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// class PuaCpu extends Module {
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// implicit val config = new CpuConfig()
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// val io = IO(new Bundle {
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// val ext_int = Input(UInt(EXT_INT_WID.W))
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// val axi = new AXI()
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// val debug = new DEBUG()
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// })
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// val core = Module(new Core())
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// val cache = Module(new Cache())
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class PuaCpu extends Module {
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implicit val config = new CpuConfig()
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val io = IO(new Bundle {
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val ext_int = Input(new ExtInterrupt())
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val axi = new AXI()
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val debug = new DEBUG()
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})
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val core = Module(new Core())
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val cache = Module(new Cache())
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// core.io.inst <> cache.io.inst
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// core.io.data <> cache.io.data
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core.io.inst <> cache.io.inst
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core.io.data <> cache.io.data
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// io.ext_int <> core.io.ext_int
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// io.debug <> core.io.debug
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// io.axi <> cache.io.axi
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// }
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io.ext_int <> core.io.ext_int
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io.debug <> core.io.debug
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io.axi <> cache.io.axi
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}
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@ -12,6 +12,12 @@ class ExceptionInfo extends Bundle {
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val tval = UInt(XLEN.W)
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}
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class ExtInterrupt extends Bundle {
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val ei = Bool()
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val ti = Bool()
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val si = Bool()
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}
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class SrcInfo extends Bundle {
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val src1_data = UInt(XLEN.W)
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val src2_data = UInt(XLEN.W)
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@ -53,29 +53,31 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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val ctrl = new DecoderUnitCtrl()
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})
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if (config.decoderNum == 2) {
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val issue = Module(new Issue()).io
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issue.allow_to_go := io.ctrl.allow_to_go
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issue.instFifo := io.instFifo.info
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io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
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for (i <- 0 until (config.decoderNum)) {
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decoder(i).io.in.inst := inst(i)
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issue.decodeInst(i) := inst_info(i)
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issue.execute(i).mem_wreg := io.forward(i).mem_wreg
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issue.execute(i).reg_waddr := io.forward(i).exe.waddr
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}
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io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go
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}
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val decoder = Seq.fill(config.decoderNum)(Module(new Decoder()))
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val jumpCtrl = Module(new JumpCtrl()).io
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val forwardCtrl = Module(new ForwardCtrl()).io
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val issue = Module(new Issue()).io
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io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr
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io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
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if (config.decoderNum == 2) {
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io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr
|
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io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr
|
||||
val pc = io.instFifo.inst.map(_.pc)
|
||||
val inst = io.instFifo.inst.map(_.inst)
|
||||
val inst_info = decoder.map(_.io.out.inst_info)
|
||||
val priv_mode = io.csr.priv_mode
|
||||
|
||||
issue.allow_to_go := io.ctrl.allow_to_go
|
||||
issue.instFifo := io.instFifo.info
|
||||
io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
|
||||
for (i <- 0 until (config.decoderNum)) {
|
||||
decoder(i).io.in.inst := inst(i)
|
||||
issue.decodeInst(i) := inst_info(i)
|
||||
issue.execute(i).mem_wreg := io.forward(i).mem_wreg
|
||||
issue.execute(i).reg_waddr := io.forward(i).exe.waddr
|
||||
}
|
||||
io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go
|
||||
|
||||
io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr
|
||||
io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
|
||||
io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr
|
||||
io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr
|
||||
forwardCtrl.in.forward := io.forward
|
||||
forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题
|
||||
jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go
|
||||
|
|
@ -101,15 +103,6 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
|
|||
io.ctrl.inst0.src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
|
||||
io.ctrl.branch := inst0_branch
|
||||
|
||||
val pc = io.instFifo.inst.map(_.pc)
|
||||
val inst = io.instFifo.inst.map(_.inst)
|
||||
val inst_info = decoder.map(_.io.out.inst_info)
|
||||
val priv_mode = io.csr.priv_mode
|
||||
|
||||
for (i <- 0 until (config.decoderNum)) {
|
||||
decoder(i).io.in.inst := inst(i)
|
||||
}
|
||||
|
||||
val int = WireInit(0.U(INT_WID.W))
|
||||
BoringUtils.addSink(int, "intDecoderUnit")
|
||||
io.executeStage.inst0.ex.interrupt.zip(int.asBools).map { case (x, y) => x := y }
|
||||
|
|
@ -139,7 +132,6 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
|
|||
inst_info(0).op === CSROpType.jmp && priv_mode === ModeS
|
||||
io.executeStage.inst0.ex.exception(ecallU) := inst_info(0).inst(31, 20) === privEcall &&
|
||||
inst_info(0).op === CSROpType.jmp && priv_mode === ModeU
|
||||
|
||||
io.executeStage.inst0.ex.tval := Mux(
|
||||
io.executeStage.inst0.ex.exception(instrAccessFault) || io.executeStage.inst0.ex.exception(instrAddrMisaligned),
|
||||
io.instFifo.inst(0).pc,
|
||||
|
|
@ -151,39 +143,37 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
|
|||
io.executeStage.inst0.jb_info.pred_branch := io.bpu.pred_branch
|
||||
io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target
|
||||
io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
|
||||
if (config.decoderNum == 2) {
|
||||
io.executeStage.inst1.valid := !io.instFifo.info.almost_empty
|
||||
io.executeStage.inst1.pc := pc(1)
|
||||
io.executeStage.inst1.inst_info := inst_info(1)
|
||||
io.executeStage.inst1.src_info.src1_data := Mux(
|
||||
inst_info(1).reg1_ren,
|
||||
forwardCtrl.out.inst(1).src1.rdata,
|
||||
SignedExtend(pc(1), INST_ADDR_WID)
|
||||
)
|
||||
io.executeStage.inst1.src_info.src2_data := Mux(
|
||||
inst_info(1).reg2_ren,
|
||||
forwardCtrl.out.inst(1).src2.rdata,
|
||||
decoder(1).io.out.inst_info.imm
|
||||
)
|
||||
io.executeStage.inst1.ex.exception.map(_ := false.B)
|
||||
io.executeStage.inst1.ex.exception(illegalInstr) := !inst_info(1).inst_valid
|
||||
io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err
|
||||
io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
|
||||
io.executeStage.inst1.ex.exception(breakPoint) := inst_info(1).inst(31, 20) === privEbreak &&
|
||||
|
||||
io.executeStage.inst1.valid := !io.instFifo.info.almost_empty
|
||||
io.executeStage.inst1.pc := pc(1)
|
||||
io.executeStage.inst1.inst_info := inst_info(1)
|
||||
io.executeStage.inst1.src_info.src1_data := Mux(
|
||||
inst_info(1).reg1_ren,
|
||||
forwardCtrl.out.inst(1).src1.rdata,
|
||||
SignedExtend(pc(1), INST_ADDR_WID)
|
||||
)
|
||||
io.executeStage.inst1.src_info.src2_data := Mux(
|
||||
inst_info(1).reg2_ren,
|
||||
forwardCtrl.out.inst(1).src2.rdata,
|
||||
decoder(1).io.out.inst_info.imm
|
||||
)
|
||||
io.executeStage.inst1.ex.exception.map(_ := false.B)
|
||||
io.executeStage.inst1.ex.exception(illegalInstr) := !inst_info(1).inst_valid
|
||||
io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err
|
||||
io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
|
||||
io.executeStage.inst1.ex.exception(breakPoint) := inst_info(1).inst(31, 20) === privEbreak &&
|
||||
inst_info(1).op === CSROpType.jmp
|
||||
io.executeStage.inst1.ex.exception(ecallM) := inst_info(1).inst(31, 20) === privEcall &&
|
||||
io.executeStage.inst1.ex.exception(ecallM) := inst_info(1).inst(31, 20) === privEcall &&
|
||||
inst_info(1).op === CSROpType.jmp && priv_mode === ModeM
|
||||
io.executeStage.inst1.ex.exception(ecallS) := inst_info(1).inst(31, 20) === privEcall &&
|
||||
io.executeStage.inst1.ex.exception(ecallS) := inst_info(1).inst(31, 20) === privEcall &&
|
||||
inst_info(1).op === CSROpType.jmp && priv_mode === ModeS
|
||||
io.executeStage.inst1.ex.exception(ecallU) := inst_info(1).inst(31, 20) === privEcall &&
|
||||
io.executeStage.inst1.ex.exception(ecallU) := inst_info(1).inst(31, 20) === privEcall &&
|
||||
inst_info(1).op === CSROpType.jmp && priv_mode === ModeU
|
||||
|
||||
io.executeStage.inst1.ex.tval := Mux(
|
||||
io.executeStage.inst1.ex.exception(instrAccessFault) || io.executeStage.inst1.ex.exception(instrAddrMisaligned),
|
||||
io.instFifo.inst(1).pc,
|
||||
0.U
|
||||
)
|
||||
} else {
|
||||
io.executeStage.inst1 := DontCare
|
||||
}
|
||||
io.executeStage.inst1.ex.tval := Mux(
|
||||
io.executeStage.inst1.ex.exception(instrAccessFault) || io.executeStage.inst1.ex.exception(instrAddrMisaligned),
|
||||
io.instFifo.inst(1).pc,
|
||||
0.U
|
||||
)
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ class CsrDecoderUnit extends Bundle {
|
|||
|
||||
class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
|
||||
val io = IO(new Bundle {
|
||||
val ext_int = Input(UInt(EXT_INT_WID.W))
|
||||
val ext_int = Input(new ExtInterrupt())
|
||||
val ctrl = Input(new Bundle {
|
||||
val exe_stall = Bool()
|
||||
val mem_stall = Bool()
|
||||
|
|
@ -68,12 +68,12 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
|
|||
val mstatus_init = Wire(new Mstatus())
|
||||
mstatus_init := 0.U.asTypeOf(new Mstatus())
|
||||
mstatus_init.uxl := 2.U
|
||||
val mstatus = RegInit(mstatus_init.asUInt) // 状态寄存器
|
||||
val mstatus = RegInit(UInt(XLEN.W), mstatus_init.asUInt) // 状态寄存器
|
||||
val misa_init = Wire(new Misa())
|
||||
misa_init := 0.U.asTypeOf(new Misa())
|
||||
misa_init.mxl := 2.U
|
||||
misa_init.extensions := "h101100".U
|
||||
val misa = RegInit(misa_init.asUInt) // ISA寄存器
|
||||
val misa = RegInit(UInt(XLEN.W), misa_init.asUInt) // ISA寄存器
|
||||
val mie = RegInit(0.U(XLEN.W)) // 中断使能寄存器
|
||||
val mtvec = RegInit(0.U(XLEN.W)) // 中断向量基址寄存器
|
||||
val mcounteren = RegInit(0.U(XLEN.W)) // 计数器使能寄存器
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
|
|||
io.memoryStage.inst0.inst_info := io.executeStage.inst0.inst_info
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata(0)
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
|
||||
io.memoryStage.inst0.ex := MuxLookup(io.executeStage.inst0.inst_info.fusel, fu.inst(0).ex.out)(
|
||||
|
|
@ -125,7 +125,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
|
|||
io.memoryStage.inst1.inst_info := io.executeStage.inst1.inst_info
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata(1)
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
|
||||
io.memoryStage.inst1.ex := MuxLookup(io.executeStage.inst1.inst_info.fusel, fu.inst(1).ex.out)(
|
||||
|
|
@ -137,11 +137,11 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
|
|||
|
||||
io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.inst_info.reg_wen
|
||||
io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.inst_info.reg_waddr
|
||||
io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata
|
||||
io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.inst_info.fusel)
|
||||
io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.inst_info.mem_wreg
|
||||
|
||||
io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.inst_info.reg_wen
|
||||
io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.inst_info.reg_waddr
|
||||
io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata
|
||||
io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.inst_info.fusel)
|
||||
io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.inst_info.mem_wreg
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,30 +47,24 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
|
|||
|
||||
io.decoderUnit(0).wen := io.writeBackStage.inst0.inst_info.reg_wen
|
||||
io.decoderUnit(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
|
||||
io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata
|
||||
io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.inst_info.fusel)
|
||||
io.decoderUnit(1).wen := io.writeBackStage.inst1.inst_info.reg_wen
|
||||
io.decoderUnit(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
|
||||
io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata
|
||||
io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.inst_info.fusel)
|
||||
|
||||
io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc
|
||||
io.writeBackStage.inst0.inst_info := io.memoryStage.inst0.inst_info
|
||||
io.writeBackStage.inst0.rd_info.wdata := Mux(
|
||||
io.writeBackStage.inst0.inst_info.mem_wreg,
|
||||
dataMemoryAccess.memoryUnit.out.rdata,
|
||||
io.memoryStage.inst0.rd_info.wdata
|
||||
)
|
||||
io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex
|
||||
io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception
|
||||
io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc
|
||||
io.writeBackStage.inst0.inst_info := io.memoryStage.inst0.inst_info
|
||||
io.writeBackStage.inst0.rd_info.wdata := io.memoryStage.inst0.rd_info.wdata
|
||||
io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
|
||||
io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex
|
||||
io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception
|
||||
|
||||
io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
|
||||
io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info
|
||||
io.writeBackStage.inst1.rd_info.wdata := Mux(
|
||||
io.writeBackStage.inst1.inst_info.mem_wreg,
|
||||
dataMemoryAccess.memoryUnit.out.rdata,
|
||||
io.memoryStage.inst1.rd_info.wdata
|
||||
)
|
||||
io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex
|
||||
io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception
|
||||
io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
|
||||
io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info
|
||||
io.writeBackStage.inst1.rd_info.wdata := io.memoryStage.inst1.rd_info.wdata
|
||||
io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
|
||||
io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex
|
||||
io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception
|
||||
|
||||
io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc
|
||||
io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex
|
||||
|
|
|
|||
|
|
@ -1,19 +1,11 @@
|
|||
import cpu._
|
||||
import circt.stage._
|
||||
import cache.Cache
|
||||
import cpu.pipeline.decoder.Decoder
|
||||
import cpu.pipeline.decoder.DecoderUnit
|
||||
import cache.ICache
|
||||
import cpu.pipeline.fetch.BranchPredictorUnit
|
||||
import cpu.pipeline.execute.Alu
|
||||
import cpu.pipeline.execute.BranchCtrl
|
||||
import cpu.pipeline.execute.Fu
|
||||
import cpu.pipeline.execute.ExeAccessMemCtrl
|
||||
import cpu.pipeline.memory.DataMemoryAccess
|
||||
|
||||
import cpu.pipeline.execute.Csr
|
||||
|
||||
object TestMain extends App {
|
||||
implicit val config = new CpuConfig()
|
||||
def top = new DataMemoryAccess()
|
||||
def top = new Csr()
|
||||
val useMFC = false // use MLIR-based firrtl compiler
|
||||
val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
|
||||
if (useMFC) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue