From a1f7cd92d0f70a88cee5e1fccfb7dec7a1981e76 Mon Sep 17 00:00:00 2001 From: Liphen Date: Thu, 23 Nov 2023 14:08:40 +0800 Subject: [PATCH] =?UTF-8?q?=E5=8E=BB=E9=99=A4=E5=A4=A7=E9=83=A8=E5=88=86?= =?UTF-8?q?=E7=B1=BB=E5=9E=8B=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/Core.scala | 247 +++++++++--------- chisel/playground/src/Elaborate.scala | 26 +- chisel/playground/src/PuaCpu.scala | 40 +-- chisel/playground/src/defines/Bundles.scala | 6 + .../src/pipeline/decoder/DecoderUnit.scala | 106 ++++---- .../playground/src/pipeline/execute/Csr.scala | 6 +- .../src/pipeline/execute/ExecuteUnit.scala | 8 +- .../src/pipeline/memory/MemoryUnit.scala | 34 +-- chisel/playground/test/src/TestMain.scala | 14 +- 9 files changed, 234 insertions(+), 253 deletions(-) diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index d933cdf..1fd178e 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -1,144 +1,143 @@ -// package cpu +package cpu -// import chisel3._ -// import chisel3.util._ -// import chisel3.internal.DontCareBinding +import chisel3._ +import chisel3.util._ +import chisel3.internal.DontCareBinding -// import defines._ -// import defines.Const._ -// import pipeline.fetch._ -// import pipeline.decoder._ -// import pipeline.execute._ -// import pipeline.memory._ -// import pipeline.writeback._ -// import ctrl._ -// import mmu._ -// import chisel3.util.experimental.decode.decoder -// import cpu.pipeline.fetch.InstFifo +import defines._ +import defines.Const._ +import pipeline.fetch._ +import pipeline.decoder._ +import pipeline.execute._ +import pipeline.memory._ +import pipeline.writeback._ +import ctrl._ +import mmu._ +import chisel3.util.experimental.decode.decoder +import cpu.pipeline.fetch.InstFifo -// class Core(implicit val config: CpuConfig) extends Module { -// val io = IO(new Bundle { -// val ext_int = Input(UInt(EXT_INT_WID.W)) -// val inst = new Cache_ICache() -// val data = new Cache_DCache() -// val debug = new DEBUG() -// }) +class Core(implicit val config: CpuConfig) extends Module { + val io = IO(new Bundle { + val ext_int = Input(new ExtInterrupt()) + val inst = new Cache_ICache() + val data = new Cache_DCache() + val debug = new DEBUG() + }) -// val ctrl = Module(new Ctrl()).io -// val fetchUnit = Module(new FetchUnit()).io -// val bpu = Module(new BranchPredictorUnit()).io -// val instFifo = Module(new InstFifo()).io -// val decoderUnit = Module(new DecoderUnit()).io -// val regfile = Module(new ARegFile()).io -// val executeStage = Module(new ExecuteStage()).io -// val executeUnit = Module(new ExecuteUnit()).io -// val csr = Module(new Csr()).io -// val memoryStage = Module(new MemoryStage()).io -// val memoryUnit = Module(new MemoryUnit()).io -// val writeBackStage = Module(new WriteBackStage()).io -// val writeBackUnit = Module(new WriteBackUnit()).io + val ctrl = Module(new Ctrl()).io + val fetchUnit = Module(new FetchUnit()).io + val bpu = Module(new BranchPredictorUnit()).io + val instFifo = Module(new InstFifo()).io + val decoderUnit = Module(new DecoderUnit()).io + val regfile = Module(new ARegFile()).io + val executeStage = Module(new ExecuteStage()).io + val executeUnit = Module(new ExecuteUnit()).io + val csr = Module(new Csr()).io + val memoryStage = Module(new MemoryStage()).io + val memoryUnit = Module(new MemoryUnit()).io + val writeBackStage = Module(new WriteBackStage()).io + val writeBackUnit = Module(new WriteBackUnit()).io -// ctrl.instFifo.has2insts := !(instFifo.empty || instFifo.almost_empty) -// ctrl.decoderUnit <> decoderUnit.ctrl -// ctrl.executeUnit <> executeUnit.ctrl -// ctrl.memoryUnit <> memoryUnit.ctrl -// ctrl.writeBackUnit <> writeBackUnit.ctrl -// ctrl.cacheCtrl.iCache_stall := io.inst.stall -// ctrl.cacheCtrl.dCache_stall := io.data.stall + ctrl.instFifo.has2insts := !(instFifo.empty || instFifo.almost_empty) + ctrl.decoderUnit <> decoderUnit.ctrl + ctrl.executeUnit <> executeUnit.ctrl + ctrl.memoryUnit <> memoryUnit.ctrl + ctrl.writeBackUnit <> writeBackUnit.ctrl + ctrl.cacheCtrl.iCache_stall := io.inst.stall + ctrl.cacheCtrl.dCache_stall := io.data.stall -// fetchUnit.memory <> memoryUnit.fetchUnit -// fetchUnit.execute <> executeUnit.fetchUnit -// fetchUnit.decoder <> decoderUnit.fetchUnit -// fetchUnit.instFifo.full := instFifo.full -// fetchUnit.iCache.inst_valid := io.inst.valid -// io.inst.addr(0) := fetchUnit.iCache.pc -// io.inst.addr(1) := fetchUnit.iCache.pc_next -// for (i <- 2 until config.instFetchNum) { -// io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U -// } + fetchUnit.memory <> memoryUnit.fetchUnit + fetchUnit.execute <> executeUnit.fetchUnit + fetchUnit.decoder <> decoderUnit.fetchUnit + fetchUnit.instFifo.full := instFifo.full + fetchUnit.iCache.inst_valid := io.inst.valid + io.inst.addr(0) := fetchUnit.iCache.pc + io.inst.addr(1) := fetchUnit.iCache.pc_next + for (i <- 2 until config.instFetchNum) { + io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U + } -// bpu.decoder.ena := ctrl.decoderUnit.allow_to_go -// bpu.decoder.op := decoderUnit.bpu.decoded_inst0.op -// bpu.decoder.inst := decoderUnit.bpu.decoded_inst0.inst -// bpu.decoder.rs1 := decoderUnit.bpu.decoded_inst0.reg1_raddr -// bpu.decoder.rs2 := decoderUnit.bpu.decoded_inst0.reg2_raddr -// bpu.decoder.pc := decoderUnit.bpu.pc -// bpu.decoder.pc_plus4 := decoderUnit.bpu.pc + 4.U -// bpu.decoder.pht_index := decoderUnit.bpu.pht_index -// decoderUnit.bpu.update_pht_index := bpu.decoder.update_pht_index -// bpu.execute <> executeUnit.bpu -// decoderUnit.bpu.branch_inst := bpu.decoder.branch_inst -// decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch -// decoderUnit.bpu.branch_target := bpu.decoder.branch_target + bpu.decoder.ena := ctrl.decoderUnit.allow_to_go + bpu.decoder.op := decoderUnit.bpu.decoded_inst0.op + bpu.decoder.inst := decoderUnit.bpu.decoded_inst0.inst + bpu.decoder.rs1 := decoderUnit.bpu.decoded_inst0.reg1_raddr + bpu.decoder.rs2 := decoderUnit.bpu.decoded_inst0.reg2_raddr + bpu.decoder.pc := decoderUnit.bpu.pc + bpu.decoder.pc_plus4 := decoderUnit.bpu.pc + 4.U + bpu.decoder.pht_index := decoderUnit.bpu.pht_index + decoderUnit.bpu.update_pht_index := bpu.decoder.update_pht_index + bpu.execute <> executeUnit.bpu + decoderUnit.bpu.branch_inst := bpu.decoder.branch_inst + decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch + decoderUnit.bpu.branch_target := bpu.decoder.branch_target -// instFifo.do_flush := ctrl.decoderUnit.do_flush -// instFifo.icache_stall := io.inst.stall -// instFifo.ren <> decoderUnit.instFifo.allow_to_go -// decoderUnit.instFifo.inst <> instFifo.read + instFifo.do_flush := ctrl.decoderUnit.do_flush + instFifo.icache_stall := io.inst.stall + instFifo.ren <> decoderUnit.instFifo.allow_to_go + decoderUnit.instFifo.inst <> instFifo.read -// for (i <- 0 until config.instFetchNum) { -// instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i) -// bpu.instBuffer.pc(i) := instFifo.write(i).pc -// instFifo.wen(i) := io.inst.valid(i) -// instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U -// instFifo.write(i).inst := io.inst.rdata -// } + for (i <- 0 until config.instFetchNum) { + instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i) + bpu.instBuffer.pc(i) := instFifo.write(i).pc + instFifo.wen(i) := io.inst.valid(i) + instFifo.write(i).pc := io.inst.addr(0) + (i * 4).U + instFifo.write(i).inst := io.inst.rdata(i) + } -// decoderUnit.instFifo.info.empty := instFifo.empty -// decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty -// decoderUnit.regfile <> regfile.read -// for (i <- 0 until (config.fuNum)) { -// decoderUnit.forward(i).exe := executeUnit.decoderUnit.forward(i).exe -// decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg -// decoderUnit.forward(i).mem := memoryUnit.decoderUnit(i) -// } -// decoderUnit.csr <> csr.decoderUnit -// decoderUnit.executeStage <> executeStage.decoderUnit + decoderUnit.instFifo.info.empty := instFifo.empty + decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty + decoderUnit.regfile <> regfile.read + for (i <- 0 until (config.fuNum)) { + decoderUnit.forward(i).exe := executeUnit.decoderUnit.forward(i).exe + decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg + decoderUnit.forward(i).mem := memoryUnit.decoderUnit(i) + } + decoderUnit.csr <> csr.decoderUnit + decoderUnit.executeStage <> executeStage.decoderUnit -// executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush_req || -// !decoderUnit.executeStage.inst0.ex.bd && ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go || -// !ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go -// executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush_req || -// (ctrl.executeUnit.do_flush && decoderUnit.executeStage.inst1.allow_to_go) || -// (ctrl.executeUnit.allow_to_go && !decoderUnit.executeStage.inst1.allow_to_go) -// executeStage.ctrl.inst0_allow_to_go := ctrl.executeUnit.allow_to_go + executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush_req || + ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go || + !ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go + executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush_req || + (ctrl.executeUnit.do_flush && decoderUnit.executeStage.inst1.allow_to_go) || + (ctrl.executeUnit.allow_to_go && !decoderUnit.executeStage.inst1.allow_to_go) + executeStage.ctrl.inst0_allow_to_go := ctrl.executeUnit.allow_to_go -// executeUnit.decoderUnit.inst0_bd := decoderUnit.executeStage.inst0.ex.bd -// executeUnit.executeStage <> executeStage.executeUnit -// executeUnit.csr <> csr.executeUnit -// executeUnit.memoryStage <> memoryStage.executeUnit + executeUnit.executeStage <> executeStage.executeUnit + executeUnit.csr <> csr.executeUnit + executeUnit.memoryStage <> memoryStage.executeUnit -// memoryStage.ctrl.allow_to_go := ctrl.memoryUnit.allow_to_go -// memoryStage.ctrl.clear := ctrl.memoryUnit.do_flush + memoryStage.ctrl.allow_to_go := ctrl.memoryUnit.allow_to_go + memoryStage.ctrl.clear := ctrl.memoryUnit.do_flush -// memoryUnit.memoryStage <> memoryStage.memoryUnit -// memoryUnit.csr <> csr.memoryUnit -// memoryUnit.writeBackStage <> writeBackStage.memoryUnit + memoryUnit.memoryStage <> memoryStage.memoryUnit + memoryUnit.csr <> csr.memoryUnit + memoryUnit.writeBackStage <> writeBackStage.memoryUnit -// csr.ctrl.exe_stall := !ctrl.executeUnit.allow_to_go -// csr.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go -// csr.ext_int := io.ext_int + csr.ctrl.exe_stall := !ctrl.executeUnit.allow_to_go + csr.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go + csr.ext_int := io.ext_int -// memoryUnit.dataMemory.in.rdata := io.data.rdata -// io.data.en := memoryUnit.dataMemory.out.en -// io.data.size := memoryUnit.dataMemory.out.rlen -// io.data.write := memoryUnit.dataMemory.out.wen -// io.data.wdata := memoryUnit.dataMemory.out.wdata -// io.data.addr := memoryUnit.dataMemory.out.addr + memoryUnit.dataMemory.in.rdata := io.data.rdata + io.data.en := memoryUnit.dataMemory.out.en + io.data.size := memoryUnit.dataMemory.out.rlen + io.data.write := memoryUnit.dataMemory.out.wen + io.data.wdata := memoryUnit.dataMemory.out.wdata + io.data.addr := memoryUnit.dataMemory.out.addr -// writeBackStage.memoryUnit <> memoryUnit.writeBackStage -// writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go -// writeBackStage.ctrl.clear := ctrl.writeBackUnit.do_flush + writeBackStage.memoryUnit <> memoryUnit.writeBackStage + writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go + writeBackStage.ctrl.clear := ctrl.writeBackUnit.do_flush -// writeBackUnit.writeBackStage <> writeBackStage.writeBackUnit -// writeBackUnit.ctrl <> ctrl.writeBackUnit -// regfile.write <> writeBackUnit.regfile + writeBackUnit.writeBackStage <> writeBackStage.writeBackUnit + writeBackUnit.ctrl <> ctrl.writeBackUnit + regfile.write <> writeBackUnit.regfile -// io.debug <> writeBackUnit.debug + io.debug <> writeBackUnit.debug -// // io.inst.fence_i := executeUnit.executeStage.inst0.inst_info.ifence -// // io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.dfence -// io.inst.en := !instFifo.full -// io.inst.ready := !ctrl.fetchUnit.allow_to_go -// io.data.ready := !ctrl.memoryUnit.allow_to_go -// } + // io.inst.fence_i := executeUnit.executeStage.inst0.inst_info.ifence + // io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.dfence + io.inst.en := !instFifo.full + io.inst.ready := !ctrl.fetchUnit.allow_to_go + io.data.ready := !ctrl.memoryUnit.allow_to_go +} diff --git a/chisel/playground/src/Elaborate.scala b/chisel/playground/src/Elaborate.scala index 24b5572..f37c1fc 100644 --- a/chisel/playground/src/Elaborate.scala +++ b/chisel/playground/src/Elaborate.scala @@ -1,14 +1,14 @@ -// import cpu._ -// import circt.stage._ +import cpu._ +import circt.stage._ -// object Elaborate extends App { -// implicit val config = new CpuConfig() -// def top = new PuaCpu() -// val useMFC = false // use MLIR-based firrtl compiler -// val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) -// if (useMFC) { -// (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog)) -// } else { -// (new chisel3.stage.ChiselStage).execute(args, generator) -// } -// } +object Elaborate extends App { + implicit val config = new CpuConfig() + def top = new PuaCpu() + val useMFC = false // use MLIR-based firrtl compiler + val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) + if (useMFC) { + (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog)) + } else { + (new chisel3.stage.ChiselStage).execute(args, generator) + } +} diff --git a/chisel/playground/src/PuaCpu.scala b/chisel/playground/src/PuaCpu.scala index 1d991a4..7362d0e 100644 --- a/chisel/playground/src/PuaCpu.scala +++ b/chisel/playground/src/PuaCpu.scala @@ -1,23 +1,23 @@ -// import chisel3._ -// import chisel3.util._ -// import cache._ -// import cpu._ -// import cpu.defines._ +import chisel3._ +import chisel3.util._ +import cache._ +import cpu._ +import cpu.defines._ -// class PuaCpu extends Module { -// implicit val config = new CpuConfig() -// val io = IO(new Bundle { -// val ext_int = Input(UInt(EXT_INT_WID.W)) -// val axi = new AXI() -// val debug = new DEBUG() -// }) -// val core = Module(new Core()) -// val cache = Module(new Cache()) +class PuaCpu extends Module { + implicit val config = new CpuConfig() + val io = IO(new Bundle { + val ext_int = Input(new ExtInterrupt()) + val axi = new AXI() + val debug = new DEBUG() + }) + val core = Module(new Core()) + val cache = Module(new Cache()) -// core.io.inst <> cache.io.inst -// core.io.data <> cache.io.data + core.io.inst <> cache.io.inst + core.io.data <> cache.io.data -// io.ext_int <> core.io.ext_int -// io.debug <> core.io.debug -// io.axi <> cache.io.axi -// } + io.ext_int <> core.io.ext_int + io.debug <> core.io.debug + io.axi <> cache.io.axi +} diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index f9f7e4c..51712dc 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -12,6 +12,12 @@ class ExceptionInfo extends Bundle { val tval = UInt(XLEN.W) } +class ExtInterrupt extends Bundle { + val ei = Bool() + val ti = Bool() + val si = Bool() +} + class SrcInfo extends Bundle { val src1_data = UInt(XLEN.W) val src2_data = UInt(XLEN.W) diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala index c4f6d23..2f915eb 100644 --- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala +++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala @@ -53,29 +53,31 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti val ctrl = new DecoderUnitCtrl() }) - if (config.decoderNum == 2) { - val issue = Module(new Issue()).io - issue.allow_to_go := io.ctrl.allow_to_go - issue.instFifo := io.instFifo.info - io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go - for (i <- 0 until (config.decoderNum)) { - decoder(i).io.in.inst := inst(i) - issue.decodeInst(i) := inst_info(i) - issue.execute(i).mem_wreg := io.forward(i).mem_wreg - issue.execute(i).reg_waddr := io.forward(i).exe.waddr - } - io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go - } val decoder = Seq.fill(config.decoderNum)(Module(new Decoder())) val jumpCtrl = Module(new JumpCtrl()).io val forwardCtrl = Module(new ForwardCtrl()).io + val issue = Module(new Issue()).io - io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr - io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr - if (config.decoderNum == 2) { - io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr - io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr + val pc = io.instFifo.inst.map(_.pc) + val inst = io.instFifo.inst.map(_.inst) + val inst_info = decoder.map(_.io.out.inst_info) + val priv_mode = io.csr.priv_mode + + issue.allow_to_go := io.ctrl.allow_to_go + issue.instFifo := io.instFifo.info + io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go + for (i <- 0 until (config.decoderNum)) { + decoder(i).io.in.inst := inst(i) + issue.decodeInst(i) := inst_info(i) + issue.execute(i).mem_wreg := io.forward(i).mem_wreg + issue.execute(i).reg_waddr := io.forward(i).exe.waddr } + io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go + + io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr + io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr + io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr + io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr forwardCtrl.in.forward := io.forward forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题 jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go @@ -101,15 +103,6 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti io.ctrl.inst0.src2.raddr := decoder(0).io.out.inst_info.reg2_raddr io.ctrl.branch := inst0_branch - val pc = io.instFifo.inst.map(_.pc) - val inst = io.instFifo.inst.map(_.inst) - val inst_info = decoder.map(_.io.out.inst_info) - val priv_mode = io.csr.priv_mode - - for (i <- 0 until (config.decoderNum)) { - decoder(i).io.in.inst := inst(i) - } - val int = WireInit(0.U(INT_WID.W)) BoringUtils.addSink(int, "intDecoderUnit") io.executeStage.inst0.ex.interrupt.zip(int.asBools).map { case (x, y) => x := y } @@ -139,7 +132,6 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti inst_info(0).op === CSROpType.jmp && priv_mode === ModeS io.executeStage.inst0.ex.exception(ecallU) := inst_info(0).inst(31, 20) === privEcall && inst_info(0).op === CSROpType.jmp && priv_mode === ModeU - io.executeStage.inst0.ex.tval := Mux( io.executeStage.inst0.ex.exception(instrAccessFault) || io.executeStage.inst0.ex.exception(instrAddrMisaligned), io.instFifo.inst(0).pc, @@ -151,39 +143,37 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti io.executeStage.inst0.jb_info.pred_branch := io.bpu.pred_branch io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index - if (config.decoderNum == 2) { - io.executeStage.inst1.valid := !io.instFifo.info.almost_empty - io.executeStage.inst1.pc := pc(1) - io.executeStage.inst1.inst_info := inst_info(1) - io.executeStage.inst1.src_info.src1_data := Mux( - inst_info(1).reg1_ren, - forwardCtrl.out.inst(1).src1.rdata, - SignedExtend(pc(1), INST_ADDR_WID) - ) - io.executeStage.inst1.src_info.src2_data := Mux( - inst_info(1).reg2_ren, - forwardCtrl.out.inst(1).src2.rdata, - decoder(1).io.out.inst_info.imm - ) - io.executeStage.inst1.ex.exception.map(_ := false.B) - io.executeStage.inst1.ex.exception(illegalInstr) := !inst_info(1).inst_valid - io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err - io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err - io.executeStage.inst1.ex.exception(breakPoint) := inst_info(1).inst(31, 20) === privEbreak && + + io.executeStage.inst1.valid := !io.instFifo.info.almost_empty + io.executeStage.inst1.pc := pc(1) + io.executeStage.inst1.inst_info := inst_info(1) + io.executeStage.inst1.src_info.src1_data := Mux( + inst_info(1).reg1_ren, + forwardCtrl.out.inst(1).src1.rdata, + SignedExtend(pc(1), INST_ADDR_WID) + ) + io.executeStage.inst1.src_info.src2_data := Mux( + inst_info(1).reg2_ren, + forwardCtrl.out.inst(1).src2.rdata, + decoder(1).io.out.inst_info.imm + ) + io.executeStage.inst1.ex.exception.map(_ := false.B) + io.executeStage.inst1.ex.exception(illegalInstr) := !inst_info(1).inst_valid + io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err + io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err + io.executeStage.inst1.ex.exception(breakPoint) := inst_info(1).inst(31, 20) === privEbreak && inst_info(1).op === CSROpType.jmp - io.executeStage.inst1.ex.exception(ecallM) := inst_info(1).inst(31, 20) === privEcall && + io.executeStage.inst1.ex.exception(ecallM) := inst_info(1).inst(31, 20) === privEcall && inst_info(1).op === CSROpType.jmp && priv_mode === ModeM - io.executeStage.inst1.ex.exception(ecallS) := inst_info(1).inst(31, 20) === privEcall && + io.executeStage.inst1.ex.exception(ecallS) := inst_info(1).inst(31, 20) === privEcall && inst_info(1).op === CSROpType.jmp && priv_mode === ModeS - io.executeStage.inst1.ex.exception(ecallU) := inst_info(1).inst(31, 20) === privEcall && + io.executeStage.inst1.ex.exception(ecallU) := inst_info(1).inst(31, 20) === privEcall && inst_info(1).op === CSROpType.jmp && priv_mode === ModeU - io.executeStage.inst1.ex.tval := Mux( - io.executeStage.inst1.ex.exception(instrAccessFault) || io.executeStage.inst1.ex.exception(instrAddrMisaligned), - io.instFifo.inst(1).pc, - 0.U - ) - } else { - io.executeStage.inst1 := DontCare - } + io.executeStage.inst1.ex.tval := Mux( + io.executeStage.inst1.ex.exception(instrAccessFault) || io.executeStage.inst1.ex.exception(instrAddrMisaligned), + io.instFifo.inst(1).pc, + 0.U + ) + } diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala index d24f98a..acaf827 100644 --- a/chisel/playground/src/pipeline/execute/Csr.scala +++ b/chisel/playground/src/pipeline/execute/Csr.scala @@ -45,7 +45,7 @@ class CsrDecoderUnit extends Bundle { class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { val io = IO(new Bundle { - val ext_int = Input(UInt(EXT_INT_WID.W)) + val ext_int = Input(new ExtInterrupt()) val ctrl = Input(new Bundle { val exe_stall = Bool() val mem_stall = Bool() @@ -68,12 +68,12 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { val mstatus_init = Wire(new Mstatus()) mstatus_init := 0.U.asTypeOf(new Mstatus()) mstatus_init.uxl := 2.U - val mstatus = RegInit(mstatus_init.asUInt) // 状态寄存器 + val mstatus = RegInit(UInt(XLEN.W), mstatus_init.asUInt) // 状态寄存器 val misa_init = Wire(new Misa()) misa_init := 0.U.asTypeOf(new Misa()) misa_init.mxl := 2.U misa_init.extensions := "h101100".U - val misa = RegInit(misa_init.asUInt) // ISA寄存器 + val misa = RegInit(UInt(XLEN.W), misa_init.asUInt) // ISA寄存器 val mie = RegInit(0.U(XLEN.W)) // 中断使能寄存器 val mtvec = RegInit(0.U(XLEN.W)) // 中断向量基址寄存器 val mcounteren = RegInit(0.U(XLEN.W)) // 计数器使能寄存器 diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index 921ef5c..5152317 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -111,7 +111,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { io.memoryStage.inst0.inst_info := io.executeStage.inst0.inst_info io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu - io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata + io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata(0) io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U io.memoryStage.inst0.ex := MuxLookup(io.executeStage.inst0.inst_info.fusel, fu.inst(0).ex.out)( @@ -125,7 +125,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { io.memoryStage.inst1.inst_info := io.executeStage.inst1.inst_info io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu - io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata + io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata(1) io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U io.memoryStage.inst1.ex := MuxLookup(io.executeStage.inst1.inst_info.fusel, fu.inst(1).ex.out)( @@ -137,11 +137,11 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.inst_info.reg_wen io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.inst_info.reg_waddr - io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata + io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.inst_info.fusel) io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.inst_info.mem_wreg io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.inst_info.reg_wen io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.inst_info.reg_waddr - io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata + io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.inst_info.fusel) io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.inst_info.mem_wreg } diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala index c5e963b..81c49be 100644 --- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala +++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala @@ -47,30 +47,24 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module { io.decoderUnit(0).wen := io.writeBackStage.inst0.inst_info.reg_wen io.decoderUnit(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr - io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata + io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.inst_info.fusel) io.decoderUnit(1).wen := io.writeBackStage.inst1.inst_info.reg_wen io.decoderUnit(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr - io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata + io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.inst_info.fusel) - io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc - io.writeBackStage.inst0.inst_info := io.memoryStage.inst0.inst_info - io.writeBackStage.inst0.rd_info.wdata := Mux( - io.writeBackStage.inst0.inst_info.mem_wreg, - dataMemoryAccess.memoryUnit.out.rdata, - io.memoryStage.inst0.rd_info.wdata - ) - io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex - io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception + io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc + io.writeBackStage.inst0.inst_info := io.memoryStage.inst0.inst_info + io.writeBackStage.inst0.rd_info.wdata := io.memoryStage.inst0.rd_info.wdata + io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata + io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex + io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception - io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc - io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info - io.writeBackStage.inst1.rd_info.wdata := Mux( - io.writeBackStage.inst1.inst_info.mem_wreg, - dataMemoryAccess.memoryUnit.out.rdata, - io.memoryStage.inst1.rd_info.wdata - ) - io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex - io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception + io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc + io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info + io.writeBackStage.inst1.rd_info.wdata := io.memoryStage.inst1.rd_info.wdata + io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata + io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex + io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex diff --git a/chisel/playground/test/src/TestMain.scala b/chisel/playground/test/src/TestMain.scala index 0618b01..21d8574 100644 --- a/chisel/playground/test/src/TestMain.scala +++ b/chisel/playground/test/src/TestMain.scala @@ -1,19 +1,11 @@ import cpu._ import circt.stage._ -import cache.Cache -import cpu.pipeline.decoder.Decoder -import cpu.pipeline.decoder.DecoderUnit -import cache.ICache -import cpu.pipeline.fetch.BranchPredictorUnit -import cpu.pipeline.execute.Alu -import cpu.pipeline.execute.BranchCtrl -import cpu.pipeline.execute.Fu -import cpu.pipeline.execute.ExeAccessMemCtrl -import cpu.pipeline.memory.DataMemoryAccess + +import cpu.pipeline.execute.Csr object TestMain extends App { implicit val config = new CpuConfig() - def top = new DataMemoryAccess() + def top = new Csr() val useMFC = false // use MLIR-based firrtl compiler val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) if (useMFC) {