148 lines
6.7 KiB
Scala
148 lines
6.7 KiB
Scala
package cpu.pipeline.execute
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import chisel3._
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import chisel3.util._
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import cpu.CpuConfig
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.pipeline.decoder.RegWrite
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import cpu.pipeline.memory.ExecuteUnitMemoryUnit
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import cpu.pipeline.fetch.ExecuteUnitBranchPredictor
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class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val ctrl = new ExecuteCtrl()
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val executeStage = Input(new DecoderUnitExecuteUnit())
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val csr = Flipped(new CsrExecuteUnit())
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val bpu = new ExecuteUnitBranchPredictor()
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val fetchUnit = Output(new Bundle {
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val branch = Bool()
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val target = UInt(PC_WID.W)
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})
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val decoderUnit = new Bundle {
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val forward = Output(
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Vec(
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config.fuNum,
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new Bundle {
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val exe = new RegWrite()
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val exe_mem_wreg = Bool()
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}
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)
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)
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val inst0_bd = Input(Bool())
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}
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val memoryStage = Output(new ExecuteUnitMemoryUnit())
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})
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val fu = Module(new Fu()).io
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val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
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io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.inst_info.mem_wreg
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io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr
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io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.inst_info.mem_wreg
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io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr
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io.ctrl.branch := io.ctrl.allow_to_go &&
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(io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
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io.csr.in.inst_info(0) := Mux(
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!io.executeStage.inst0.ex.exception.asUInt.orR,
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io.executeStage.inst0.inst_info,
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0.U.asTypeOf(new InstInfo())
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)
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io.csr.in.inst_info(1) := io.executeStage.inst1.inst_info
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// input accessMemCtrl
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accessMemCtrl.inst(0).inst_info := io.executeStage.inst0.inst_info
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accessMemCtrl.inst(0).src_info := io.executeStage.inst0.src_info
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accessMemCtrl.inst(0).ex.in := io.executeStage.inst0.ex
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accessMemCtrl.inst(1).inst_info := io.executeStage.inst1.inst_info
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accessMemCtrl.inst(1).src_info := io.executeStage.inst1.src_info
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accessMemCtrl.inst(1).ex.in := io.executeStage.inst1.ex
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// input fu
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fu.ctrl <> io.ctrl.fu
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fu.inst(0).pc := io.executeStage.inst0.pc
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fu.inst(0).mul_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
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!MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
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fu.inst(0).div_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
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MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
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fu.inst(0).inst_info := io.executeStage.inst0.inst_info
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fu.inst(0).src_info := io.executeStage.inst0.src_info
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fu.inst(0).ex.in :=
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Mux(io.executeStage.inst0.inst_info.fusel === FuType.lsu, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
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fu.inst(1).pc := io.executeStage.inst1.pc
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fu.inst(1).mul_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
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!MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
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fu.inst(1).div_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
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MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
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fu.inst(1).inst_info := io.executeStage.inst1.inst_info
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fu.inst(1).src_info := io.executeStage.inst1.src_info
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fu.inst(1).ex.in := io.executeStage.inst1.ex
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fu.csr_rdata := io.csr.out.rdata
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fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
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io.bpu.pc := io.executeStage.inst0.pc
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io.bpu.update_pht_index := io.executeStage.inst0.jb_info.update_pht_index
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io.bpu.branch := fu.branch.branch
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io.bpu.branch_inst := io.executeStage.inst0.jb_info.branch_inst
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io.fetchUnit.branch := io.ctrl.allow_to_go &&
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(io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
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io.fetchUnit.target := MuxCase(
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io.executeStage.inst0.pc + 4.U, // 默认顺序运行吧
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Seq(
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(fu.branch.pred_fail && fu.branch.branch) -> io.executeStage.inst0.jb_info.branch_target,
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(fu.branch.pred_fail && !fu.branch.branch) -> (io.executeStage.inst0.pc + 4.U),
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(io.executeStage.inst0.jb_info.jump_regiser) -> (io.executeStage.inst0.src_info.src1_data + io.executeStage.inst0.src_info.src2_data)
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)
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)
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io.ctrl.fu_stall := fu.stall_req
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io.memoryStage.inst0.mem.en := accessMemCtrl.mem.out.en
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io.memoryStage.inst0.mem.ren := accessMemCtrl.mem.out.ren
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io.memoryStage.inst0.mem.wen := accessMemCtrl.mem.out.wen
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io.memoryStage.inst0.mem.addr := accessMemCtrl.mem.out.addr
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io.memoryStage.inst0.mem.wdata := accessMemCtrl.mem.out.wdata
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io.memoryStage.inst0.mem.sel := accessMemCtrl.inst.map(_.mem_sel)
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io.memoryStage.inst0.mem.inst_info := accessMemCtrl.mem.out.inst_info
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io.memoryStage.inst0.pc := io.executeStage.inst0.pc
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io.memoryStage.inst0.inst_info := io.executeStage.inst0.inst_info
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io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
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io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
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io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata(0)
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io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
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io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
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io.memoryStage.inst0.ex := MuxLookup(io.executeStage.inst0.inst_info.fusel, fu.inst(0).ex.out)(
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Seq(
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FuType.lsu -> accessMemCtrl.inst(0).ex.out,
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FuType.csr -> io.csr.out.ex(0)
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)
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)
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io.memoryStage.inst1.pc := io.executeStage.inst1.pc
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io.memoryStage.inst1.inst_info := io.executeStage.inst1.inst_info
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io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
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io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
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io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata(1)
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io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
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io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
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io.memoryStage.inst1.ex := MuxLookup(io.executeStage.inst1.inst_info.fusel, fu.inst(1).ex.out)(
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Seq(
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FuType.lsu -> accessMemCtrl.inst(1).ex.out,
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FuType.csr -> io.csr.out.ex(1)
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)
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)
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io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.inst_info.reg_wen
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io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.inst_info.reg_waddr
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io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.inst_info.fusel)
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io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.inst_info.mem_wreg
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io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.inst_info.reg_wen
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io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.inst_info.reg_waddr
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io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.inst_info.fusel)
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io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.inst_info.mem_wreg
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}
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