fix(mem): 修复wstrb错误
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parent
e3366efc56
commit
aac7d1ccb8
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@ -71,7 +71,7 @@ class Core(implicit val config: CpuConfig) extends Module {
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decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch
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decoderUnit.bpu.branch_target := bpu.decoder.branch_target
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instFifo.do_flush := ctrl.decoderUnit.do_flush
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instFifo.do_flush := ctrl.decoderUnit.do_flush
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instFifo.ren <> decoderUnit.instFifo.allow_to_go
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decoderUnit.instFifo.inst <> instFifo.read
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@ -122,9 +122,10 @@ class Core(implicit val config: CpuConfig) extends Module {
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memoryUnit.dataMemory.in.rdata := io.data.rdata
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io.data.en := memoryUnit.dataMemory.out.en
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io.data.size := memoryUnit.dataMemory.out.rlen
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io.data.wen := memoryUnit.dataMemory.out.wen
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io.data.wen := memoryUnit.dataMemory.out.wen
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io.data.wdata := memoryUnit.dataMemory.out.wdata
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io.data.addr := memoryUnit.dataMemory.out.addr
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io.data.wstrb := memoryUnit.dataMemory.out.wstrb
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writeBackStage.memoryUnit <> memoryUnit.writeBackStage
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writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go
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@ -140,7 +141,7 @@ class Core(implicit val config: CpuConfig) extends Module {
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executeUnit.executeStage.inst0.inst_info.op === MOUOpType.fencei
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io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.fusel === FuType.mou &&
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memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei
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io.inst.req := !instFifo.full && !reset.asBool
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io.inst.req := !instFifo.full && !reset.asBool
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io.inst.cpu_ready := ctrl.fetchUnit.allow_to_go
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io.data.cpu_ready := ctrl.memoryUnit.allow_to_go
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}
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@ -18,24 +18,14 @@ class DCache(implicit config: CpuConfig) extends Module {
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val s_idle :: s_uncached :: s_writeback :: s_save :: Nil = Enum(4)
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val status = RegInit(s_idle)
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val wstrb_gen = Wire(UInt(8.W))
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wstrb_gen := MuxLookup(io.cpu.size, "b1111_1111".U)(
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Seq(
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0.U -> ("b1".U << io.cpu.addr(2, 0)),
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1.U -> ("b11".U << Cat(io.cpu.addr(2, 1), 0.U(1.W))),
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2.U -> ("b1111".U << Cat(io.cpu.addr(2), 0.U(2.W))),
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3.U -> ("b1111_1111".U)
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)
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)
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io.cpu.valid := status === s_save
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val addr_err = io.cpu.addr(63, 32).orR
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// default
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val awvalid = RegInit(false.B)
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val awaddr = RegInit(0.U(32.W))
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val awsize = RegInit(0.U(3.W))
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val awaddr = RegInit(0.U(AXI_ADDR_WID.W))
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val awsize = RegInit(0.U(AXI_SIZE_WID.W))
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io.axi.aw.id := 1.U
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io.axi.aw.addr := awaddr
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io.axi.aw.len := 0.U
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@ -47,8 +37,8 @@ class DCache(implicit config: CpuConfig) extends Module {
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io.axi.aw.cache := 0.U
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val wvalid = RegInit(false.B)
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val wdata = RegInit(0.U(XLEN.W))
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val wstrb = RegInit(0.U(4.W))
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val wdata = RegInit(0.U(AXI_DATA_WID.W))
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val wstrb = RegInit(0.U(AXI_STRB_WID.W))
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io.axi.w.id := 1.U
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io.axi.w.data := wdata
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io.axi.w.strb := wstrb
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@ -57,9 +47,9 @@ class DCache(implicit config: CpuConfig) extends Module {
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io.axi.b.ready := 1.U
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val araddr = RegInit(0.U(32.W))
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val arsize = RegInit(0.U(3.W))
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val arlen = RegInit(0.U(8.W))
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val araddr = RegInit(0.U(AXI_ADDR_WID.W))
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val arsize = RegInit(0.U(AXI_SIZE_WID.W))
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val arlen = RegInit(0.U(AXI_LEN_WID.W))
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val arvalid = RegInit(false.B)
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io.axi.ar.id := 1.U
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io.axi.ar.addr := araddr
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@ -87,6 +77,7 @@ class DCache(implicit config: CpuConfig) extends Module {
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Mux(io.cpu.en, (cached_stall || mmio_read_stall || mmio_write_stall), io.cpu.fence_i),
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status =/= s_save
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)
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switch(status) {
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is(s_idle) {
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acc_err := false.B
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@ -100,7 +91,7 @@ class DCache(implicit config: CpuConfig) extends Module {
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awsize := Cat(false.B, io.cpu.size)
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awvalid := true.B
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wdata := io.cpu.wdata
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wstrb := wstrb_gen
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wstrb := io.cpu.wstrb
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wvalid := true.B
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status := s_writeback
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}.otherwise {
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@ -23,7 +23,7 @@ class ICache(implicit config: CpuConfig) extends Module {
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// default
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val arvalid = RegInit(false.B)
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val araddr = RegInit(0.U(32.W))
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val araddr = RegInit(0.U(AXI_ADDR_WID.W))
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io.axi.ar.id := 0.U
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io.axi.ar.addr := araddr
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io.axi.ar.len := 0.U
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@ -36,7 +36,7 @@ class ICache(implicit config: CpuConfig) extends Module {
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val rready = RegInit(false.B)
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val saved = RegInit(VecInit(Seq.fill(config.instFetchNum)(0.U.asTypeOf(new Bundle {
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val inst = UInt(32.W)
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val inst = UInt(AXI_DATA_WID.W)
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val valid = Bool()
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}))))
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io.axi.r.ready := true.B
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@ -130,6 +130,7 @@ class Cache_DCache extends Bundle {
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val wdata = Output(UInt(XLEN.W))
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val cpu_ready = Output(Bool())
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val fence_i = Output(Bool())
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val wstrb = Output(UInt(AXI_STRB_WID.W))
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val rdata = Input(UInt(XLEN.W))
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val valid = Input(Bool())
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@ -141,14 +142,14 @@ class Cache_DCache extends Bundle {
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// master -> slave
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class AR extends Bundle {
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val id = Output(UInt(4.W))
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val addr = Output(UInt(32.W))
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val len = Output(UInt(8.W))
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val size = Output(UInt(3.W))
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val burst = Output(UInt(2.W))
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val lock = Output(UInt(2.W))
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val cache = Output(UInt(4.W))
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val prot = Output(UInt(3.W))
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val id = Output(UInt(AXI_ID_WID.W))
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val addr = Output(UInt(AXI_ADDR_WID.W))
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val len = Output(UInt(AXI_LEN_WID.W))
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val size = Output(UInt(AXI_SIZE_WID.W))
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val burst = Output(UInt(AXI_BURST_WID.W))
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val lock = Output(UInt(AXI_LOCK_WID.W))
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val cache = Output(UInt(AXI_CACHE_WID.W))
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val prot = Output(UInt(AXI_PROT_WID.W))
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val valid = Output(Bool())
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val ready = Input(Bool())
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@ -157,31 +158,31 @@ class AR extends Bundle {
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class R extends Bundle {
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val ready = Output(Bool())
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val id = Input(UInt(4.W))
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val data = Input(UInt(XLEN.W))
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val resp = Input(UInt(2.W))
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val id = Input(UInt(AXI_ID_WID.W))
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val data = Input(UInt(AXI_DATA_WID.W))
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val resp = Input(UInt(AXI_RESP_WID.W))
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val last = Input(Bool())
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val valid = Input(Bool())
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}
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class AW extends Bundle {
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val id = Output(UInt(4.W))
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val addr = Output(UInt(32.W))
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val len = Output(UInt(8.W))
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val size = Output(UInt(3.W))
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val burst = Output(UInt(2.W))
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val lock = Output(UInt(2.W))
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val cache = Output(UInt(4.W))
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val prot = Output(UInt(3.W))
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val id = Output(UInt(AXI_ID_WID.W))
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val addr = Output(UInt(AXI_ADDR_WID.W))
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val len = Output(UInt(AXI_LEN_WID.W))
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val size = Output(UInt(AXI_SIZE_WID.W))
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val burst = Output(UInt(AXI_BURST_WID.W))
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val lock = Output(UInt(AXI_LOCK_WID.W))
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val cache = Output(UInt(AXI_CACHE_WID.W))
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val prot = Output(UInt(AXI_PROT_WID.W))
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val valid = Output(Bool())
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val ready = Input(Bool())
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}
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class W extends Bundle {
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val id = Output(UInt(4.W))
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val data = Output(UInt(XLEN.W))
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val strb = Output(UInt(4.W))
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val id = Output(UInt(AXI_ID_WID.W))
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val data = Output(UInt(AXI_DATA_WID.W))
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val strb = Output(UInt(AXI_STRB_WID.W))
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val last = Output(Bool())
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val valid = Output(Bool())
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@ -191,8 +192,8 @@ class W extends Bundle {
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class B extends Bundle {
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val ready = Output(Bool())
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val id = Input(UInt(4.W))
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val resp = Input(UInt(2.W))
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val id = Input(UInt(AXI_ID_WID.W))
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val resp = Input(UInt(AXI_RESP_WID.W))
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val valid = Input(Bool())
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}
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@ -225,25 +226,8 @@ class AXI extends Bundle {
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}
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class DEBUG extends Bundle {
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val wb_pc = Output(UInt(32.W))
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val wb_pc = Output(UInt(PC_WID.W))
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val wb_rf_wen = Output(Bool())
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val wb_rf_wnum = Output(UInt(5.W))
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val wb_rf_wdata = Output(UInt(32.W))
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}
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class Ctrl_Sram extends Bundle {
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val do_flush = Output(Bool())
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}
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class Ctrl_Stage extends Bundle {
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val do_flush = Output(Bool())
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val after_ex = Output(Bool())
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}
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class Sram_Ctrl extends Bundle {
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val sram_discard = Output(UInt(2.W))
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}
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class Pipeline_Ctrl extends Bundle {
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val ex = Output(Bool())
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val wb_rf_wnum = Output(UInt(REG_ADDR_WID.W))
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val wb_rf_wdata = Output(UInt(DATA_WID.W))
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}
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@ -33,7 +33,7 @@ trait Constants extends CoreParameter {
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val DIV_STOP = false.B
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// inst rom
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val INST_WID = 32
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val INST_WID = XLEN
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val INST_ADDR_WID = XLEN
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// data ram
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@ -97,6 +97,18 @@ trait AXIConst {
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val RESP_EXOKEY = 1
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val RESP_SLVERR = 2
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val RESP_DECERR = 3
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val AXI_ID_WID = 4
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val AXI_ADDR_WID = 32
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val AXI_DATA_WID = 64
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val AXI_STRB_WID = 8
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val AXI_RESP_WID = 2
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val AXI_LEN_WID = 8
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val AXI_SIZE_WID = 3
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val AXI_BURST_WID = 2
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val AXI_LOCK_WID = 2
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val AXI_CACHE_WID = 4
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val AXI_PROT_WID = 3
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}
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object Const extends Constants with AXIConst with HasExceptionNO
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@ -28,10 +28,11 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
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})
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val out = Output(new Bundle {
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val en = Bool()
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val rlen = UInt(2.W)
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val rlen = UInt(AXI_LEN_WID.W)
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val wen = Bool()
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val addr = UInt(DATA_ADDR_WID.W)
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val wdata = UInt(DATA_WID.W)
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val wstrb = UInt(AXI_STRB_WID.W)
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val addr = UInt(AXI_ADDR_WID.W)
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val wdata = UInt(AXI_DATA_WID.W)
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})
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}
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})
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@ -80,7 +81,20 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
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)
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)
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}
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def genWmask(addr: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> 0x1.U, //0001 << addr(2:0)
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"b01".U -> 0x3.U, //0011
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"b10".U -> 0xf.U, //1111
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"b11".U -> 0xff.U //11111111
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)
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) << addr(2, 0)
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}
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io.dataMemory.out.wdata := genWdata(mem_wdata, op(1, 0))
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io.dataMemory.out.wen := LSUOpType.isStore(op) && io.memoryUnit.in.mem_en
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io.dataMemory.out.wstrb := genWmask(mem_addr, op(1, 0))
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io.dataMemory.out.rlen := op(1, 0)
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}
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@ -26,10 +26,11 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
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})
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val out = Output(new Bundle {
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val en = Bool()
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val rlen = UInt(2.W)
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val wen = UInt(4.W)
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val addr = UInt(DATA_ADDR_WID.W)
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val wdata = UInt(DATA_WID.W)
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val rlen = UInt(AXI_LEN_WID.W)
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val wen = Bool()
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val addr = UInt(AXI_ADDR_WID.W)
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val wdata = UInt(AXI_DATA_WID.W)
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val wstrb = UInt(AXI_STRB_WID.W)
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})
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}
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})
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