From aac7d1ccb8dcee10b6165cf3a912e3c0ba0aa432 Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 27 Nov 2023 17:16:46 +0800 Subject: [PATCH] =?UTF-8?q?fix(mem):=20=E4=BF=AE=E5=A4=8Dwstrb=E9=94=99?= =?UTF-8?q?=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/Core.scala | 7 +- chisel/playground/src/cache/DCache.scala | 27 +++---- chisel/playground/src/cache/ICache.scala | 4 +- chisel/playground/src/defines/Bundles.scala | 72 ++++++++----------- chisel/playground/src/defines/Const.scala | 14 +++- .../pipeline/memory/DataMemoryAccess.scala | 20 +++++- .../src/pipeline/memory/MemoryUnit.scala | 9 +-- 7 files changed, 78 insertions(+), 75 deletions(-) diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index e385248..1edd2ad 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -71,7 +71,7 @@ class Core(implicit val config: CpuConfig) extends Module { decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch decoderUnit.bpu.branch_target := bpu.decoder.branch_target - instFifo.do_flush := ctrl.decoderUnit.do_flush + instFifo.do_flush := ctrl.decoderUnit.do_flush instFifo.ren <> decoderUnit.instFifo.allow_to_go decoderUnit.instFifo.inst <> instFifo.read @@ -122,9 +122,10 @@ class Core(implicit val config: CpuConfig) extends Module { memoryUnit.dataMemory.in.rdata := io.data.rdata io.data.en := memoryUnit.dataMemory.out.en io.data.size := memoryUnit.dataMemory.out.rlen - io.data.wen := memoryUnit.dataMemory.out.wen + io.data.wen := memoryUnit.dataMemory.out.wen io.data.wdata := memoryUnit.dataMemory.out.wdata io.data.addr := memoryUnit.dataMemory.out.addr + io.data.wstrb := memoryUnit.dataMemory.out.wstrb writeBackStage.memoryUnit <> memoryUnit.writeBackStage writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go @@ -140,7 +141,7 @@ class Core(implicit val config: CpuConfig) extends Module { executeUnit.executeStage.inst0.inst_info.op === MOUOpType.fencei io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.fusel === FuType.mou && memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei - io.inst.req := !instFifo.full && !reset.asBool + io.inst.req := !instFifo.full && !reset.asBool io.inst.cpu_ready := ctrl.fetchUnit.allow_to_go io.data.cpu_ready := ctrl.memoryUnit.allow_to_go } diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala index 0a09ef9..67f79d5 100644 --- a/chisel/playground/src/cache/DCache.scala +++ b/chisel/playground/src/cache/DCache.scala @@ -18,24 +18,14 @@ class DCache(implicit config: CpuConfig) extends Module { val s_idle :: s_uncached :: s_writeback :: s_save :: Nil = Enum(4) val status = RegInit(s_idle) - val wstrb_gen = Wire(UInt(8.W)) - wstrb_gen := MuxLookup(io.cpu.size, "b1111_1111".U)( - Seq( - 0.U -> ("b1".U << io.cpu.addr(2, 0)), - 1.U -> ("b11".U << Cat(io.cpu.addr(2, 1), 0.U(1.W))), - 2.U -> ("b1111".U << Cat(io.cpu.addr(2), 0.U(2.W))), - 3.U -> ("b1111_1111".U) - ) - ) - io.cpu.valid := status === s_save val addr_err = io.cpu.addr(63, 32).orR // default val awvalid = RegInit(false.B) - val awaddr = RegInit(0.U(32.W)) - val awsize = RegInit(0.U(3.W)) + val awaddr = RegInit(0.U(AXI_ADDR_WID.W)) + val awsize = RegInit(0.U(AXI_SIZE_WID.W)) io.axi.aw.id := 1.U io.axi.aw.addr := awaddr io.axi.aw.len := 0.U @@ -47,8 +37,8 @@ class DCache(implicit config: CpuConfig) extends Module { io.axi.aw.cache := 0.U val wvalid = RegInit(false.B) - val wdata = RegInit(0.U(XLEN.W)) - val wstrb = RegInit(0.U(4.W)) + val wdata = RegInit(0.U(AXI_DATA_WID.W)) + val wstrb = RegInit(0.U(AXI_STRB_WID.W)) io.axi.w.id := 1.U io.axi.w.data := wdata io.axi.w.strb := wstrb @@ -57,9 +47,9 @@ class DCache(implicit config: CpuConfig) extends Module { io.axi.b.ready := 1.U - val araddr = RegInit(0.U(32.W)) - val arsize = RegInit(0.U(3.W)) - val arlen = RegInit(0.U(8.W)) + val araddr = RegInit(0.U(AXI_ADDR_WID.W)) + val arsize = RegInit(0.U(AXI_SIZE_WID.W)) + val arlen = RegInit(0.U(AXI_LEN_WID.W)) val arvalid = RegInit(false.B) io.axi.ar.id := 1.U io.axi.ar.addr := araddr @@ -87,6 +77,7 @@ class DCache(implicit config: CpuConfig) extends Module { Mux(io.cpu.en, (cached_stall || mmio_read_stall || mmio_write_stall), io.cpu.fence_i), status =/= s_save ) + switch(status) { is(s_idle) { acc_err := false.B @@ -100,7 +91,7 @@ class DCache(implicit config: CpuConfig) extends Module { awsize := Cat(false.B, io.cpu.size) awvalid := true.B wdata := io.cpu.wdata - wstrb := wstrb_gen + wstrb := io.cpu.wstrb wvalid := true.B status := s_writeback }.otherwise { diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index 8f6c574..aeddb06 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -23,7 +23,7 @@ class ICache(implicit config: CpuConfig) extends Module { // default val arvalid = RegInit(false.B) - val araddr = RegInit(0.U(32.W)) + val araddr = RegInit(0.U(AXI_ADDR_WID.W)) io.axi.ar.id := 0.U io.axi.ar.addr := araddr io.axi.ar.len := 0.U @@ -36,7 +36,7 @@ class ICache(implicit config: CpuConfig) extends Module { val rready = RegInit(false.B) val saved = RegInit(VecInit(Seq.fill(config.instFetchNum)(0.U.asTypeOf(new Bundle { - val inst = UInt(32.W) + val inst = UInt(AXI_DATA_WID.W) val valid = Bool() })))) io.axi.r.ready := true.B diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index 573e761..39a59ef 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -130,6 +130,7 @@ class Cache_DCache extends Bundle { val wdata = Output(UInt(XLEN.W)) val cpu_ready = Output(Bool()) val fence_i = Output(Bool()) + val wstrb = Output(UInt(AXI_STRB_WID.W)) val rdata = Input(UInt(XLEN.W)) val valid = Input(Bool()) @@ -141,14 +142,14 @@ class Cache_DCache extends Bundle { // master -> slave class AR extends Bundle { - val id = Output(UInt(4.W)) - val addr = Output(UInt(32.W)) - val len = Output(UInt(8.W)) - val size = Output(UInt(3.W)) - val burst = Output(UInt(2.W)) - val lock = Output(UInt(2.W)) - val cache = Output(UInt(4.W)) - val prot = Output(UInt(3.W)) + val id = Output(UInt(AXI_ID_WID.W)) + val addr = Output(UInt(AXI_ADDR_WID.W)) + val len = Output(UInt(AXI_LEN_WID.W)) + val size = Output(UInt(AXI_SIZE_WID.W)) + val burst = Output(UInt(AXI_BURST_WID.W)) + val lock = Output(UInt(AXI_LOCK_WID.W)) + val cache = Output(UInt(AXI_CACHE_WID.W)) + val prot = Output(UInt(AXI_PROT_WID.W)) val valid = Output(Bool()) val ready = Input(Bool()) @@ -157,31 +158,31 @@ class AR extends Bundle { class R extends Bundle { val ready = Output(Bool()) - val id = Input(UInt(4.W)) - val data = Input(UInt(XLEN.W)) - val resp = Input(UInt(2.W)) + val id = Input(UInt(AXI_ID_WID.W)) + val data = Input(UInt(AXI_DATA_WID.W)) + val resp = Input(UInt(AXI_RESP_WID.W)) val last = Input(Bool()) val valid = Input(Bool()) } class AW extends Bundle { - val id = Output(UInt(4.W)) - val addr = Output(UInt(32.W)) - val len = Output(UInt(8.W)) - val size = Output(UInt(3.W)) - val burst = Output(UInt(2.W)) - val lock = Output(UInt(2.W)) - val cache = Output(UInt(4.W)) - val prot = Output(UInt(3.W)) + val id = Output(UInt(AXI_ID_WID.W)) + val addr = Output(UInt(AXI_ADDR_WID.W)) + val len = Output(UInt(AXI_LEN_WID.W)) + val size = Output(UInt(AXI_SIZE_WID.W)) + val burst = Output(UInt(AXI_BURST_WID.W)) + val lock = Output(UInt(AXI_LOCK_WID.W)) + val cache = Output(UInt(AXI_CACHE_WID.W)) + val prot = Output(UInt(AXI_PROT_WID.W)) val valid = Output(Bool()) val ready = Input(Bool()) } class W extends Bundle { - val id = Output(UInt(4.W)) - val data = Output(UInt(XLEN.W)) - val strb = Output(UInt(4.W)) + val id = Output(UInt(AXI_ID_WID.W)) + val data = Output(UInt(AXI_DATA_WID.W)) + val strb = Output(UInt(AXI_STRB_WID.W)) val last = Output(Bool()) val valid = Output(Bool()) @@ -191,8 +192,8 @@ class W extends Bundle { class B extends Bundle { val ready = Output(Bool()) - val id = Input(UInt(4.W)) - val resp = Input(UInt(2.W)) + val id = Input(UInt(AXI_ID_WID.W)) + val resp = Input(UInt(AXI_RESP_WID.W)) val valid = Input(Bool()) } @@ -225,25 +226,8 @@ class AXI extends Bundle { } class DEBUG extends Bundle { - val wb_pc = Output(UInt(32.W)) + val wb_pc = Output(UInt(PC_WID.W)) val wb_rf_wen = Output(Bool()) - val wb_rf_wnum = Output(UInt(5.W)) - val wb_rf_wdata = Output(UInt(32.W)) -} - -class Ctrl_Sram extends Bundle { - val do_flush = Output(Bool()) -} - -class Ctrl_Stage extends Bundle { - val do_flush = Output(Bool()) - val after_ex = Output(Bool()) -} - -class Sram_Ctrl extends Bundle { - val sram_discard = Output(UInt(2.W)) -} - -class Pipeline_Ctrl extends Bundle { - val ex = Output(Bool()) + val wb_rf_wnum = Output(UInt(REG_ADDR_WID.W)) + val wb_rf_wdata = Output(UInt(DATA_WID.W)) } diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala index ee5db6d..17fcc2c 100644 --- a/chisel/playground/src/defines/Const.scala +++ b/chisel/playground/src/defines/Const.scala @@ -33,7 +33,7 @@ trait Constants extends CoreParameter { val DIV_STOP = false.B // inst rom - val INST_WID = 32 + val INST_WID = XLEN val INST_ADDR_WID = XLEN // data ram @@ -97,6 +97,18 @@ trait AXIConst { val RESP_EXOKEY = 1 val RESP_SLVERR = 2 val RESP_DECERR = 3 + + val AXI_ID_WID = 4 + val AXI_ADDR_WID = 32 + val AXI_DATA_WID = 64 + val AXI_STRB_WID = 8 + val AXI_RESP_WID = 2 + val AXI_LEN_WID = 8 + val AXI_SIZE_WID = 3 + val AXI_BURST_WID = 2 + val AXI_LOCK_WID = 2 + val AXI_CACHE_WID = 4 + val AXI_PROT_WID = 3 } object Const extends Constants with AXIConst with HasExceptionNO diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala index a2ec144..33bab2d 100644 --- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala +++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala @@ -28,10 +28,11 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module { }) val out = Output(new Bundle { val en = Bool() - val rlen = UInt(2.W) + val rlen = UInt(AXI_LEN_WID.W) val wen = Bool() - val addr = UInt(DATA_ADDR_WID.W) - val wdata = UInt(DATA_WID.W) + val wstrb = UInt(AXI_STRB_WID.W) + val addr = UInt(AXI_ADDR_WID.W) + val wdata = UInt(AXI_DATA_WID.W) }) } }) @@ -80,7 +81,20 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module { ) ) } + def genWmask(addr: UInt, sizeEncode: UInt): UInt = { + LookupTree( + sizeEncode, + List( + "b00".U -> 0x1.U, //0001 << addr(2:0) + "b01".U -> 0x3.U, //0011 + "b10".U -> 0xf.U, //1111 + "b11".U -> 0xff.U //11111111 + ) + ) << addr(2, 0) + } + io.dataMemory.out.wdata := genWdata(mem_wdata, op(1, 0)) io.dataMemory.out.wen := LSUOpType.isStore(op) && io.memoryUnit.in.mem_en + io.dataMemory.out.wstrb := genWmask(mem_addr, op(1, 0)) io.dataMemory.out.rlen := op(1, 0) } diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala index 9732dda..7efecec 100644 --- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala +++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala @@ -26,10 +26,11 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module { }) val out = Output(new Bundle { val en = Bool() - val rlen = UInt(2.W) - val wen = UInt(4.W) - val addr = UInt(DATA_ADDR_WID.W) - val wdata = UInt(DATA_WID.W) + val rlen = UInt(AXI_LEN_WID.W) + val wen = Bool() + val addr = UInt(AXI_ADDR_WID.W) + val wdata = UInt(AXI_DATA_WID.W) + val wstrb = UInt(AXI_STRB_WID.W) }) } })