style: inst_info改为info
This commit is contained in:
Liphen
parent
5512fb26ec
commit
8c88660498
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@ -138,10 +138,10 @@ class Core(implicit val config: CpuConfig) extends Module {
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io.debug <> writeBackUnit.debug
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io.inst.fence_i := executeUnit.executeStage.inst0.inst_info.fusel === FuType.mou &&
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executeUnit.executeStage.inst0.inst_info.op === MOUOpType.fencei
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io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.fusel === FuType.mou &&
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memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei
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io.inst.fence_i := executeUnit.executeStage.inst0.info.fusel === FuType.mou &&
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executeUnit.executeStage.inst0.info.op === MOUOpType.fencei
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io.data.fence_i := memoryUnit.memoryStage.inst0.info.fusel === FuType.mou &&
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memoryUnit.memoryStage.inst0.info.op === MOUOpType.fencei
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io.inst.req := !instFifo.full && !reset.asBool
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io.inst.cpu_ready := ctrl.fetchUnit.allow_to_go
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io.data.cpu_ready := ctrl.memoryUnit.allow_to_go
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@ -13,7 +13,7 @@ class Decoder extends Module with HasInstrType {
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})
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// outputs
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val out = Output(new Bundle {
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val inst_info = new InstInfo()
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val info = new InstInfo()
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})
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})
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@ -36,25 +36,25 @@ class Decoder extends Module with HasInstrType {
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val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7))
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io.out.inst_info.valid := false.B
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io.out.inst_info.inst_legal := instrType =/= InstrN
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io.out.inst_info.reg1_ren := src1Type === SrcType.reg || inst(6, 0) === "b0110111".U // fix LUI
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io.out.inst_info.reg1_raddr := Mux(io.out.inst_info.reg1_ren, rs, 0.U)
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io.out.inst_info.reg2_ren := src2Type === SrcType.reg
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io.out.inst_info.reg2_raddr := Mux(io.out.inst_info.reg2_ren, rt, 0.U)
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io.out.inst_info.fusel := fuType
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io.out.inst_info.op := fuOpType
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io.out.info.valid := false.B
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io.out.info.inst_legal := instrType =/= InstrN
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io.out.info.reg1_ren := src1Type === SrcType.reg || inst(6, 0) === "b0110111".U // fix LUI
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io.out.info.reg1_raddr := Mux(io.out.info.reg1_ren, rs, 0.U)
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io.out.info.reg2_ren := src2Type === SrcType.reg
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io.out.info.reg2_raddr := Mux(io.out.info.reg2_ren, rt, 0.U)
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io.out.info.fusel := fuType
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io.out.info.op := fuOpType
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// when(fuType === FuType.bru) {
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// def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
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// when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.inst_info.op := ALUOpType.call }
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// when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.info.op := ALUOpType.call }
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// when(fuOpType === ALUOpType.jalr) {
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// when(isLink(rs)) { io.out.inst_info.op := ALUOpType.ret }
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// when(isLink(rd)) { io.out.inst_info.op := ALUOpType.call }
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// when(isLink(rs)) { io.out.info.op := ALUOpType.ret }
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// when(isLink(rd)) { io.out.info.op := ALUOpType.call }
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// }
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// }
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io.out.inst_info.reg_wen := isrfWen(instrType)
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io.out.inst_info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
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io.out.inst_info.imm := LookupTree(
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io.out.info.reg_wen := isrfWen(instrType)
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io.out.info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
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io.out.info.imm := LookupTree(
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instrType,
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Seq(
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InstrI -> SignedExtend(inst(31, 20), XLEN),
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@ -65,6 +65,6 @@ class Decoder extends Module with HasInstrType {
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InstrJ -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
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)
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)
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io.out.inst_info.inst := inst
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io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
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io.out.info.inst := inst
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io.out.info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
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}
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@ -60,7 +60,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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val pc = io.instFifo.inst.map(_.pc)
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val inst = io.instFifo.inst.map(_.inst)
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val inst_info = decoder.map(_.io.out.inst_info)
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val info = decoder.map(_.io.out.info)
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val priv_mode = io.csr.priv_mode
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issue.allow_to_go := io.ctrl.allow_to_go
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@ -68,20 +68,20 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
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for (i <- 0 until (config.decoderNum)) {
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decoder(i).io.in.inst := inst(i)
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issue.decodeInst(i) := inst_info(i)
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issue.decodeInst(i) := info(i)
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issue.execute(i).mem_wreg := io.forward(i).mem_wreg
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issue.execute(i).reg_waddr := io.forward(i).exe.waddr
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}
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io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go
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io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr
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io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
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io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr
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io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr
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io.regfile(0).src1.raddr := decoder(0).io.out.info.reg1_raddr
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io.regfile(0).src2.raddr := decoder(0).io.out.info.reg2_raddr
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io.regfile(1).src1.raddr := decoder(1).io.out.info.reg1_raddr
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io.regfile(1).src2.raddr := decoder(1).io.out.info.reg2_raddr
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forwardCtrl.in.forward := io.forward
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forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题
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jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go
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jumpCtrl.in.inst_info := decoder(0).io.out.inst_info
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jumpCtrl.in.info := decoder(0).io.out.info
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jumpCtrl.in.forward := io.forward
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jumpCtrl.in.pc := io.instFifo.inst(0).pc
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jumpCtrl.in.src_info := io.executeStage.inst0.src_info
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@ -94,41 +94,41 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go
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io.bpu.id_allow_to_go := io.ctrl.allow_to_go
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io.bpu.pc := io.instFifo.inst(0).pc
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io.bpu.decoded_inst0 := decoder(0).io.out.inst_info
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io.bpu.decoded_inst0 := decoder(0).io.out.info
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io.bpu.pht_index := io.instFifo.inst(0).pht_index
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io.ctrl.inst0.src1.ren := decoder(0).io.out.inst_info.reg1_ren
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io.ctrl.inst0.src1.raddr := decoder(0).io.out.inst_info.reg1_raddr
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io.ctrl.inst0.src2.ren := decoder(0).io.out.inst_info.reg2_ren
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io.ctrl.inst0.src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
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io.ctrl.inst0.src1.ren := decoder(0).io.out.info.reg1_ren
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io.ctrl.inst0.src1.raddr := decoder(0).io.out.info.reg1_raddr
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io.ctrl.inst0.src2.ren := decoder(0).io.out.info.reg2_ren
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io.ctrl.inst0.src2.raddr := decoder(0).io.out.info.reg2_raddr
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io.ctrl.branch := inst0_branch
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io.executeStage.inst0.pc := pc(0)
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io.executeStage.inst0.inst_info := inst_info(0)
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io.executeStage.inst0.inst_info.valid := !io.instFifo.info.empty
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io.executeStage.inst0.info := info(0)
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io.executeStage.inst0.info.valid := !io.instFifo.info.empty
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io.executeStage.inst0.src_info.src1_data := Mux(
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inst_info(0).reg1_ren,
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info(0).reg1_ren,
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forwardCtrl.out.inst(0).src1.rdata,
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SignedExtend(pc(0), INST_ADDR_WID)
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)
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io.executeStage.inst0.src_info.src2_data := Mux(
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inst_info(0).reg2_ren,
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info(0).reg2_ren,
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forwardCtrl.out.inst(0).src2.rdata,
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decoder(0).io.out.inst_info.imm
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decoder(0).io.out.info.imm
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst0.ex.exception.map(_ := false.B)
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io.executeStage.inst0.ex.exception(illegalInstr) := !inst_info(0).inst_legal
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io.executeStage.inst0.ex.exception(illegalInstr) := !info(0).inst_legal
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io.executeStage.inst0.ex.exception(instrAccessFault) := io.instFifo.inst(0).acc_err
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io.executeStage.inst0.ex.exception(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
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io.executeStage.inst0.ex.exception(breakPoint) := inst_info(0).inst(31, 20) === privEbreak &&
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inst_info(0).op === CSROpType.jmp
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io.executeStage.inst0.ex.exception(ecallM) := inst_info(0).inst(31, 20) === privEcall &&
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inst_info(0).op === CSROpType.jmp && priv_mode === ModeM && inst_info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallS) := inst_info(0).inst(31, 20) === privEcall &&
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inst_info(0).op === CSROpType.jmp && priv_mode === ModeS && inst_info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallU) := inst_info(0).inst(31, 20) === privEcall &&
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inst_info(0).op === CSROpType.jmp && priv_mode === ModeU && inst_info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak &&
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info(0).op === CSROpType.jmp
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io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && priv_mode === ModeM && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallS) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && priv_mode === ModeS && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && priv_mode === ModeU && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.tval := Mux(
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io.executeStage.inst0.ex.exception(instrAccessFault) || io.executeStage.inst0.ex.exception(instrAddrMisaligned),
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io.instFifo.inst(0).pc,
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@ -142,31 +142,31 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
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io.executeStage.inst1.pc := pc(1)
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io.executeStage.inst1.inst_info := inst_info(1)
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io.executeStage.inst1.inst_info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
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io.executeStage.inst1.info := info(1)
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io.executeStage.inst1.info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
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io.executeStage.inst1.src_info.src1_data := Mux(
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inst_info(1).reg1_ren,
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info(1).reg1_ren,
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forwardCtrl.out.inst(1).src1.rdata,
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SignedExtend(pc(1), INST_ADDR_WID)
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)
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io.executeStage.inst1.src_info.src2_data := Mux(
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inst_info(1).reg2_ren,
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info(1).reg2_ren,
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forwardCtrl.out.inst(1).src2.rdata,
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decoder(1).io.out.inst_info.imm
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decoder(1).io.out.info.imm
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst1.ex.exception.map(_ := false.B)
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io.executeStage.inst1.ex.exception(illegalInstr) := !inst_info(1).inst_legal
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io.executeStage.inst1.ex.exception(illegalInstr) := !info(1).inst_legal
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io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).acc_err
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io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
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io.executeStage.inst1.ex.exception(breakPoint) := inst_info(1).inst(31, 20) === privEbreak &&
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inst_info(1).op === CSROpType.jmp
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io.executeStage.inst1.ex.exception(ecallM) := inst_info(1).inst(31, 20) === privEcall &&
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inst_info(1).op === CSROpType.jmp && priv_mode === ModeM && inst_info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallS) := inst_info(1).inst(31, 20) === privEcall &&
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inst_info(1).op === CSROpType.jmp && priv_mode === ModeS && inst_info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallU) := inst_info(1).inst(31, 20) === privEcall &&
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inst_info(1).op === CSROpType.jmp && priv_mode === ModeU && inst_info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak &&
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info(1).op === CSROpType.jmp
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io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && priv_mode === ModeM && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && priv_mode === ModeS && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallU) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && priv_mode === ModeU && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.tval := Mux(
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io.executeStage.inst1.ex.exception(instrAccessFault) || io.executeStage.inst1.ex.exception(instrAddrMisaligned),
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@ -12,7 +12,7 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
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val in = Input(new Bundle {
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val allow_to_go = Bool()
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val pc = UInt(PC_WID.W)
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val inst_info = new InstInfo()
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val info = new InstInfo()
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val src_info = new SrcInfo()
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val forward = Vec(config.fuNum, new DataForwardToDecoderUnit())
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})
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@ -24,22 +24,22 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
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})
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})
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val op = io.in.inst_info.op
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val op = io.in.info.op
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val jump_inst = VecInit(ALUOpType.jal).contains(op)
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val jump_register_inst = VecInit(ALUOpType.jalr).contains(op)
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io.out.jump_inst := jump_inst || jump_register_inst
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io.out.jump := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register)
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if (config.decoderNum == 2) {
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io.out.jump_register := jump_register_inst &&
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((io.in.forward(0).exe.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).exe.waddr) ||
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(io.in.forward(1).exe.wen && io.in.inst_info.reg1_raddr === io.in.forward(1).exe.waddr) ||
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(io.in.forward(0).mem.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).mem.waddr) ||
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(io.in.forward(1).mem.wen && io.in.inst_info.reg1_raddr === io.in.forward(1).mem.waddr))
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((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) ||
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(io.in.forward(1).exe.wen && io.in.info.reg1_raddr === io.in.forward(1).exe.waddr) ||
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(io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr) ||
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(io.in.forward(1).mem.wen && io.in.info.reg1_raddr === io.in.forward(1).mem.waddr))
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} else {
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io.out.jump_register := jump_register_inst &&
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((io.in.forward(0).exe.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).exe.waddr) ||
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(io.in.forward(0).mem.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).mem.waddr))
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((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) ||
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(io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr))
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}
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io.out.jump_target := Mux(
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jump_inst,
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@ -21,11 +21,11 @@ class MultSignal extends Bundle {
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}
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class Alu extends Module {
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val io = IO(new Bundle {
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val inst_info = Input(new InstInfo())
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val info = Input(new InstInfo())
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val src_info = Input(new SrcInfo())
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val result = Output(UInt(DATA_WID.W))
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})
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val op = io.inst_info.op
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val op = io.info.op
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val src1 = io.src_info.src1_data
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val src2 = io.src_info.src2_data
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val is_sub = !ALUOpType.isAdd(op)
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@ -8,7 +8,7 @@ import cpu.defines.Const._
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class BranchCtrl extends Module {
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val io = IO(new Bundle {
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val in = new Bundle {
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val inst_info = Input(new InstInfo())
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val info = Input(new InstInfo())
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val src_info = Input(new SrcInfo())
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val pred_branch = Input(Bool())
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}
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@ -18,10 +18,10 @@ class BranchCtrl extends Module {
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}
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})
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val valid =
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io.in.inst_info.fusel === FuType.bru && ALUOpType.isBranch(io.in.inst_info.op) && io.in.inst_info.valid
|
||||
io.in.info.fusel === FuType.bru && ALUOpType.isBranch(io.in.info.op) && io.in.info.valid
|
||||
val src1 = io.in.src_info.src1_data
|
||||
val src2 = io.in.src_info.src2_data
|
||||
val op = io.in.inst_info.op
|
||||
val op = io.in.info.op
|
||||
val is_sub = !ALUOpType.isAdd(op)
|
||||
val adder = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub
|
||||
val xor = src1 ^ src2
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
|
|||
new Bundle {
|
||||
val pc = UInt(PC_WID.W)
|
||||
val ex = new ExceptionInfo()
|
||||
val inst_info = new InstInfo()
|
||||
val info = new InstInfo()
|
||||
}
|
||||
)
|
||||
})
|
||||
|
|
@ -27,7 +27,7 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
|
|||
class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
|
||||
val in = Input(new Bundle {
|
||||
val valid = Bool()
|
||||
val inst_info = new InstInfo()
|
||||
val info = new InstInfo()
|
||||
val src_info = new SrcInfo()
|
||||
val ex = new ExceptionInfo()
|
||||
})
|
||||
|
|
@ -213,18 +213,18 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
|
|||
!(io.memoryUnit.in.inst(1).ex.exception.asUInt.orR || io.memoryUnit.in.inst(1).ex.interrupt.asUInt.orR)
|
||||
val mem_pc = Mux(exc_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc)
|
||||
val mem_ex = Mux(exc_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
|
||||
val mem_inst_info = Mux(exc_sel, io.memoryUnit.in.inst(0).inst_info, io.memoryUnit.in.inst(1).inst_info)
|
||||
val mem_inst_info = Mux(exc_sel, io.memoryUnit.in.inst(0).info, io.memoryUnit.in.inst(1).info)
|
||||
val mem_inst = mem_inst_info.inst
|
||||
val mem_valid = mem_inst_info.valid
|
||||
val mem_addr = mem_inst(31, 20)
|
||||
// 不带前缀的信号为exe阶段的信号
|
||||
val valid = io.executeUnit.in.valid
|
||||
val inst_info = io.executeUnit.in.inst_info
|
||||
val op = io.executeUnit.in.inst_info.op
|
||||
val fusel = io.executeUnit.in.inst_info.fusel
|
||||
val addr = io.executeUnit.in.inst_info.inst(31, 20)
|
||||
val info = io.executeUnit.in.info
|
||||
val op = io.executeUnit.in.info.op
|
||||
val fusel = io.executeUnit.in.info.fusel
|
||||
val addr = io.executeUnit.in.info.inst(31, 20)
|
||||
val src1 = io.executeUnit.in.src_info.src1_data
|
||||
val csri = ZeroExtend(io.executeUnit.in.inst_info.inst(19, 15), XLEN)
|
||||
val csri = ZeroExtend(io.executeUnit.in.info.inst(19, 15), XLEN)
|
||||
val exe_stall = io.ctrl.exe_stall
|
||||
val mem_stall = io.ctrl.mem_stall
|
||||
wdata := LookupTree(
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
|
|||
val en = Bool()
|
||||
val ren = Bool()
|
||||
val wen = Bool()
|
||||
val inst_info = new InstInfo()
|
||||
val info = new InstInfo()
|
||||
val addr = UInt(DATA_ADDR_WID.W)
|
||||
val wdata = UInt(DATA_WID.W)
|
||||
})
|
||||
|
|
@ -22,7 +22,7 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
|
|||
val inst = Vec(
|
||||
config.fuNum,
|
||||
new Bundle {
|
||||
val inst_info = Input(new InstInfo())
|
||||
val info = Input(new InstInfo())
|
||||
val src_info = Input(new SrcInfo())
|
||||
val ex = new Bundle {
|
||||
val in = Input(new ExceptionInfo())
|
||||
|
|
@ -33,37 +33,37 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
|
|||
)
|
||||
})
|
||||
io.mem.out.en := io.inst.map(_.mem_sel).reduce(_ || _)
|
||||
io.mem.out.ren := io.inst(0).mem_sel && LSUOpType.isLoad(io.inst(0).inst_info.op) ||
|
||||
io.inst(1).mem_sel && LSUOpType.isLoad(io.inst(1).inst_info.op)
|
||||
io.mem.out.wen := io.inst(0).mem_sel && LSUOpType.isStore(io.inst(0).inst_info.op) ||
|
||||
io.inst(1).mem_sel && LSUOpType.isStore(io.inst(1).inst_info.op)
|
||||
io.mem.out.inst_info := Mux1H(
|
||||
io.mem.out.ren := io.inst(0).mem_sel && LSUOpType.isLoad(io.inst(0).info.op) ||
|
||||
io.inst(1).mem_sel && LSUOpType.isLoad(io.inst(1).info.op)
|
||||
io.mem.out.wen := io.inst(0).mem_sel && LSUOpType.isStore(io.inst(0).info.op) ||
|
||||
io.inst(1).mem_sel && LSUOpType.isStore(io.inst(1).info.op)
|
||||
io.mem.out.info := Mux1H(
|
||||
Seq(
|
||||
(io.inst(0).inst_info.fusel === FuType.lsu) -> io.inst(0).inst_info,
|
||||
(io.inst(1).inst_info.fusel === FuType.lsu) -> io.inst(1).inst_info
|
||||
(io.inst(0).info.fusel === FuType.lsu) -> io.inst(0).info,
|
||||
(io.inst(1).info.fusel === FuType.lsu) -> io.inst(1).info
|
||||
)
|
||||
)
|
||||
val mem_addr = Wire(Vec(config.fuNum, UInt(DATA_ADDR_WID.W)))
|
||||
mem_addr(0) := io.inst(0).src_info.src1_data + io.inst(0).inst_info.imm
|
||||
mem_addr(1) := io.inst(1).src_info.src1_data + io.inst(1).inst_info.imm
|
||||
mem_addr(0) := io.inst(0).src_info.src1_data + io.inst(0).info.imm
|
||||
mem_addr(1) := io.inst(1).src_info.src1_data + io.inst(1).info.imm
|
||||
io.mem.out.addr := Mux1H(
|
||||
Seq(
|
||||
(io.inst(0).inst_info.fusel === FuType.lsu) -> mem_addr(0),
|
||||
(io.inst(1).inst_info.fusel === FuType.lsu) -> mem_addr(1)
|
||||
(io.inst(0).info.fusel === FuType.lsu) -> mem_addr(0),
|
||||
(io.inst(1).info.fusel === FuType.lsu) -> mem_addr(1)
|
||||
)
|
||||
)
|
||||
io.mem.out.wdata := Mux1H(
|
||||
Seq(
|
||||
(io.inst(0).inst_info.fusel === FuType.lsu) ->
|
||||
(io.inst(0).info.fusel === FuType.lsu) ->
|
||||
io.inst(0).src_info.src2_data,
|
||||
(io.inst(1).inst_info.fusel === FuType.lsu) ->
|
||||
(io.inst(1).info.fusel === FuType.lsu) ->
|
||||
io.inst(1).src_info.src2_data
|
||||
)
|
||||
)
|
||||
val addr_aligned = Wire(Vec(config.fuNum, Bool()))
|
||||
for (i <- 0 until config.fuNum) {
|
||||
addr_aligned(i) := LookupTree(
|
||||
io.inst(i).inst_info.op(1, 0),
|
||||
io.inst(i).info.op(1, 0),
|
||||
List(
|
||||
"b00".U -> true.B, //b
|
||||
"b01".U -> (mem_addr(i)(0) === 0.U), //h
|
||||
|
|
@ -74,17 +74,17 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
|
|||
}
|
||||
|
||||
for (i <- 0 until config.fuNum) {
|
||||
val store_inst = LSUOpType.isStore(io.inst(i).inst_info.op)
|
||||
val store_inst = LSUOpType.isStore(io.inst(i).info.op)
|
||||
io.inst(i).ex.out := io.inst(i).ex.in
|
||||
io.inst(i).ex.out.exception(loadAddrMisaligned) := store_inst && !addr_aligned(i)
|
||||
io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i)
|
||||
}
|
||||
io.inst(0).mem_sel := (io.inst(0).inst_info.fusel === FuType.lsu) &&
|
||||
io.inst(0).mem_sel := (io.inst(0).info.fusel === FuType.lsu) &&
|
||||
!(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&
|
||||
io.inst(0).inst_info.valid
|
||||
io.inst(1).mem_sel := (io.inst(1).inst_info.fusel === FuType.lsu) &&
|
||||
io.inst(0).info.valid
|
||||
io.inst(1).mem_sel := (io.inst(1).info.fusel === FuType.lsu) &&
|
||||
!(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&
|
||||
!(io.inst(1).ex.out.exception.asUInt.orR || io.inst(1).ex.out.interrupt.asUInt.orR) &&
|
||||
io.inst(1).inst_info.valid
|
||||
io.inst(1).info.valid
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ import cpu.{BranchPredictorConfig, CpuConfig}
|
|||
class IdExeInst0 extends Bundle {
|
||||
val config = new BranchPredictorConfig()
|
||||
val pc = UInt(PC_WID.W)
|
||||
val inst_info = new InstInfo()
|
||||
val info = new InstInfo()
|
||||
val src_info = new SrcInfo()
|
||||
val ex = new ExceptionInfo()
|
||||
val jb_info = new Bundle {
|
||||
|
|
@ -26,7 +26,7 @@ class IdExeInst0 extends Bundle {
|
|||
class IdExeInst1 extends Bundle {
|
||||
val allow_to_go = Bool()
|
||||
val pc = UInt(PC_WID.W)
|
||||
val inst_info = new InstInfo()
|
||||
val info = new InstInfo()
|
||||
val src_info = new SrcInfo()
|
||||
val ex = new ExceptionInfo()
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,27 +37,27 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
|
|||
val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
|
||||
|
||||
val valid = VecInit(
|
||||
io.executeStage.inst0.inst_info.valid && io.ctrl.allow_to_go,
|
||||
io.executeStage.inst1.inst_info.valid && io.ctrl.allow_to_go
|
||||
io.executeStage.inst0.info.valid && io.ctrl.allow_to_go,
|
||||
io.executeStage.inst1.info.valid && io.ctrl.allow_to_go
|
||||
)
|
||||
|
||||
io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.inst_info.mem_wreg
|
||||
io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr
|
||||
io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.inst_info.mem_wreg
|
||||
io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr
|
||||
io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.info.mem_wreg
|
||||
io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.info.reg_waddr
|
||||
io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.info.mem_wreg
|
||||
io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.info.reg_waddr
|
||||
io.ctrl.branch := valid(0) && io.ctrl.allow_to_go &&
|
||||
(io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
|
||||
|
||||
val csr_sel0 = valid(0) && io.executeStage.inst0.inst_info.fusel === FuType.csr &&
|
||||
val csr_sel0 = valid(0) && io.executeStage.inst0.info.fusel === FuType.csr &&
|
||||
!(io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR)
|
||||
val csr_sel1 = valid(1) && io.executeStage.inst1.inst_info.fusel === FuType.csr &&
|
||||
val csr_sel1 = valid(1) && io.executeStage.inst1.info.fusel === FuType.csr &&
|
||||
!(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR)
|
||||
io.csr.in.valid := (csr_sel0 || csr_sel1)
|
||||
io.csr.in.inst_info := MuxCase(
|
||||
io.csr.in.info := MuxCase(
|
||||
0.U.asTypeOf(new InstInfo()),
|
||||
Seq(
|
||||
csr_sel0 -> io.executeStage.inst0.inst_info,
|
||||
csr_sel1 -> io.executeStage.inst1.inst_info
|
||||
csr_sel0 -> io.executeStage.inst0.info,
|
||||
csr_sel1 -> io.executeStage.inst1.info
|
||||
)
|
||||
)
|
||||
io.csr.in.src_info := MuxCase(
|
||||
|
|
@ -76,30 +76,30 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
|
|||
)
|
||||
|
||||
// input accessMemCtrl
|
||||
accessMemCtrl.inst(0).inst_info := io.executeStage.inst0.inst_info
|
||||
accessMemCtrl.inst(0).info := io.executeStage.inst0.info
|
||||
accessMemCtrl.inst(0).src_info := io.executeStage.inst0.src_info
|
||||
accessMemCtrl.inst(0).ex.in := io.executeStage.inst0.ex
|
||||
accessMemCtrl.inst(1).inst_info := io.executeStage.inst1.inst_info
|
||||
accessMemCtrl.inst(1).info := io.executeStage.inst1.info
|
||||
accessMemCtrl.inst(1).src_info := io.executeStage.inst1.src_info
|
||||
accessMemCtrl.inst(1).ex.in := io.executeStage.inst1.ex
|
||||
|
||||
// input fu
|
||||
fu.ctrl <> io.ctrl.fu
|
||||
fu.inst(0).pc := io.executeStage.inst0.pc
|
||||
fu.inst(0).mul_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
|
||||
!MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
|
||||
fu.inst(0).div_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
|
||||
MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
|
||||
fu.inst(0).inst_info := io.executeStage.inst0.inst_info
|
||||
fu.inst(0).mul_en := io.executeStage.inst0.info.fusel === FuType.mdu &&
|
||||
!MDUOpType.isDiv(io.executeStage.inst0.info.op)
|
||||
fu.inst(0).div_en := io.executeStage.inst0.info.fusel === FuType.mdu &&
|
||||
MDUOpType.isDiv(io.executeStage.inst0.info.op)
|
||||
fu.inst(0).info := io.executeStage.inst0.info
|
||||
fu.inst(0).src_info := io.executeStage.inst0.src_info
|
||||
fu.inst(0).ex.in :=
|
||||
Mux(io.executeStage.inst0.inst_info.fusel === FuType.lsu, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
|
||||
Mux(io.executeStage.inst0.info.fusel === FuType.lsu, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
|
||||
fu.inst(1).pc := io.executeStage.inst1.pc
|
||||
fu.inst(1).mul_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
|
||||
!MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
|
||||
fu.inst(1).div_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
|
||||
MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
|
||||
fu.inst(1).inst_info := io.executeStage.inst1.inst_info
|
||||
fu.inst(1).mul_en := io.executeStage.inst1.info.fusel === FuType.mdu &&
|
||||
!MDUOpType.isDiv(io.executeStage.inst1.info.op)
|
||||
fu.inst(1).div_en := io.executeStage.inst1.info.fusel === FuType.mdu &&
|
||||
MDUOpType.isDiv(io.executeStage.inst1.info.op)
|
||||
fu.inst(1).info := io.executeStage.inst1.info
|
||||
fu.inst(1).src_info := io.executeStage.inst1.src_info
|
||||
fu.inst(1).ex.in := io.executeStage.inst1.ex
|
||||
fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
|
||||
|
|
@ -127,21 +127,21 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
|
|||
io.memoryStage.inst0.mem.addr := accessMemCtrl.mem.out.addr
|
||||
io.memoryStage.inst0.mem.wdata := accessMemCtrl.mem.out.wdata
|
||||
io.memoryStage.inst0.mem.sel := accessMemCtrl.inst.map(_.mem_sel)
|
||||
io.memoryStage.inst0.mem.inst_info := accessMemCtrl.mem.out.inst_info
|
||||
io.memoryStage.inst0.mem.info := accessMemCtrl.mem.out.info
|
||||
|
||||
io.memoryStage.inst0.pc := io.executeStage.inst0.pc
|
||||
io.memoryStage.inst0.inst_info := io.executeStage.inst0.inst_info
|
||||
io.memoryStage.inst0.info := io.executeStage.inst0.info
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
|
||||
val has_ex0 =
|
||||
(io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR) && io.executeStage.inst0.inst_info.valid
|
||||
(io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR) && io.executeStage.inst0.info.valid
|
||||
io.memoryStage.inst0.ex := Mux(
|
||||
has_ex0,
|
||||
io.executeStage.inst0.ex,
|
||||
MuxLookup(io.executeStage.inst0.inst_info.fusel, io.executeStage.inst0.ex)(
|
||||
MuxLookup(io.executeStage.inst0.info.fusel, io.executeStage.inst0.ex)(
|
||||
Seq(
|
||||
FuType.alu -> fu.inst(0).ex.out,
|
||||
FuType.mdu -> fu.inst(0).ex.out,
|
||||
|
|
@ -152,18 +152,18 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
|
|||
)
|
||||
|
||||
io.memoryStage.inst1.pc := io.executeStage.inst1.pc
|
||||
io.memoryStage.inst1.inst_info := io.executeStage.inst1.inst_info
|
||||
io.memoryStage.inst1.info := io.executeStage.inst1.info
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
|
||||
val has_ex1 =
|
||||
(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR) && io.executeStage.inst1.inst_info.valid
|
||||
(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR) && io.executeStage.inst1.info.valid
|
||||
io.memoryStage.inst1.ex := Mux(
|
||||
has_ex1,
|
||||
io.executeStage.inst1.ex,
|
||||
MuxLookup(io.executeStage.inst1.inst_info.fusel, io.executeStage.inst1.ex)(
|
||||
MuxLookup(io.executeStage.inst1.info.fusel, io.executeStage.inst1.ex)(
|
||||
Seq(
|
||||
FuType.alu -> fu.inst(1).ex.out,
|
||||
FuType.mdu -> fu.inst(1).ex.out,
|
||||
|
|
@ -173,13 +173,13 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
|
|||
)
|
||||
)
|
||||
|
||||
io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.inst_info.reg_wen
|
||||
io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.inst_info.reg_waddr
|
||||
io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.inst_info.fusel)
|
||||
io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.inst_info.mem_wreg
|
||||
io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen
|
||||
io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr
|
||||
io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.info.fusel)
|
||||
io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.info.mem_wreg
|
||||
|
||||
io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.inst_info.reg_wen
|
||||
io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.inst_info.reg_waddr
|
||||
io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.inst_info.fusel)
|
||||
io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.inst_info.mem_wreg
|
||||
io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.info.reg_wen
|
||||
io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.info.reg_waddr
|
||||
io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.info.fusel)
|
||||
io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.info.mem_wreg
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
|
|||
val pc = Input(UInt(PC_WID.W))
|
||||
val mul_en = Input(Bool())
|
||||
val div_en = Input(Bool())
|
||||
val inst_info = Input(new InstInfo())
|
||||
val info = Input(new InstInfo())
|
||||
val src_info = Input(new SrcInfo())
|
||||
val ex = new Bundle {
|
||||
val in = Input(new ExceptionInfo())
|
||||
|
|
@ -40,14 +40,14 @@ class Fu(implicit val config: CpuConfig) extends Module {
|
|||
// val div = Module(new Div()).io
|
||||
val branchCtrl = Module(new BranchCtrl()).io
|
||||
|
||||
branchCtrl.in.inst_info := io.inst(0).inst_info
|
||||
branchCtrl.in.info := io.inst(0).info
|
||||
branchCtrl.in.src_info := io.inst(0).src_info
|
||||
branchCtrl.in.pred_branch := io.branch.pred_branch
|
||||
io.branch.branch := branchCtrl.out.branch
|
||||
io.branch.pred_fail := branchCtrl.out.pred_fail
|
||||
|
||||
for (i <- 0 until (config.fuNum)) {
|
||||
alu(i).io.inst_info := io.inst(i).inst_info
|
||||
alu(i).io.info := io.inst(i).info
|
||||
alu(i).io.src_info := io.inst(i).src_info
|
||||
// alu(i).io.mul.result := mul.result
|
||||
// alu(i).io.mul.ready := mul.ready
|
||||
|
|
@ -74,7 +74,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
|
|||
io.stall_req := false.B
|
||||
|
||||
io.inst(0).result.alu := Mux(
|
||||
ALUOpType.isBru(io.inst(0).inst_info.op),
|
||||
ALUOpType.isBru(io.inst(0).info.op),
|
||||
io.inst(0).pc + 4.U,
|
||||
alu(0).io.result
|
||||
)
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
|
|||
val memoryUnit = new Bundle {
|
||||
val in = Input(new Bundle {
|
||||
val mem_en = Bool()
|
||||
val inst_info = new InstInfo()
|
||||
val info = new InstInfo()
|
||||
val mem_wdata = UInt(DATA_WID.W)
|
||||
val mem_addr = UInt(DATA_ADDR_WID.W)
|
||||
val mem_sel = Vec(config.fuNum, Bool())
|
||||
|
|
@ -44,7 +44,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
|
|||
val mem_addr2 = mem_addr(1, 0)
|
||||
val mem_rdata = io.dataMemory.in.rdata
|
||||
val mem_wdata = io.memoryUnit.in.mem_wdata
|
||||
val op = io.memoryUnit.in.inst_info.op
|
||||
val op = io.memoryUnit.in.info.op
|
||||
io.dataMemory.out.en := io.memoryUnit.in.mem_en &&
|
||||
(io.memoryUnit.in.mem_sel(0) &&
|
||||
!(io.memoryUnit.in.ex(0).exception.asUInt.orR || io.memoryUnit.in.ex(0).interrupt.asUInt.orR) ||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ import cpu.CpuConfig
|
|||
|
||||
class ExeMemInst1 extends Bundle {
|
||||
val pc = UInt(PC_WID.W)
|
||||
val inst_info = new InstInfo()
|
||||
val info = new InstInfo()
|
||||
val rd_info = new RdInfo()
|
||||
val ex = new ExceptionInfo()
|
||||
}
|
||||
|
|
@ -18,7 +18,7 @@ class ExeMemInst0(implicit val config: CpuConfig) extends ExeMemInst1 {
|
|||
val en = Bool()
|
||||
val ren = Bool()
|
||||
val wen = Bool()
|
||||
val inst_info = new InstInfo()
|
||||
val info = new InstInfo()
|
||||
val addr = UInt(DATA_ADDR_WID.W)
|
||||
val wdata = UInt(DATA_WID.W)
|
||||
val sel = Vec(config.fuNum, Bool())
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
|
|||
|
||||
val dataMemoryAccess = Module(new DataMemoryAccess()).io
|
||||
dataMemoryAccess.memoryUnit.in.mem_en := io.memoryStage.inst0.mem.en
|
||||
dataMemoryAccess.memoryUnit.in.inst_info := io.memoryStage.inst0.mem.inst_info
|
||||
dataMemoryAccess.memoryUnit.in.info := io.memoryStage.inst0.mem.info
|
||||
dataMemoryAccess.memoryUnit.in.mem_wdata := io.memoryStage.inst0.mem.wdata
|
||||
dataMemoryAccess.memoryUnit.in.mem_addr := io.memoryStage.inst0.mem.addr
|
||||
dataMemoryAccess.memoryUnit.in.mem_sel := io.memoryStage.inst0.mem.sel
|
||||
|
|
@ -35,48 +35,48 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
|
|||
dataMemoryAccess.dataMemory.in.rdata := io.dataMemory.in.rdata
|
||||
io.dataMemory.out := dataMemoryAccess.dataMemory.out
|
||||
|
||||
io.decoderUnit(0).wen := io.writeBackStage.inst0.inst_info.reg_wen
|
||||
io.decoderUnit(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
|
||||
io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.inst_info.fusel)
|
||||
io.decoderUnit(1).wen := io.writeBackStage.inst1.inst_info.reg_wen
|
||||
io.decoderUnit(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
|
||||
io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.inst_info.fusel)
|
||||
io.decoderUnit(0).wen := io.writeBackStage.inst0.info.reg_wen
|
||||
io.decoderUnit(0).waddr := io.writeBackStage.inst0.info.reg_waddr
|
||||
io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
|
||||
io.decoderUnit(1).wen := io.writeBackStage.inst1.info.reg_wen
|
||||
io.decoderUnit(1).waddr := io.writeBackStage.inst1.info.reg_waddr
|
||||
io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
|
||||
|
||||
io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc
|
||||
io.writeBackStage.inst0.inst_info := io.memoryStage.inst0.inst_info
|
||||
io.writeBackStage.inst0.info := io.memoryStage.inst0.info
|
||||
io.writeBackStage.inst0.rd_info.wdata := io.memoryStage.inst0.rd_info.wdata
|
||||
io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
|
||||
io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex
|
||||
io.writeBackStage.inst0.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
|
||||
LSUOpType.isLoad(io.memoryStage.inst0.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
LSUOpType.isLoad(io.memoryStage.inst0.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst0.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
|
||||
LSUOpType.isStore(io.memoryStage.inst0.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst0.commit := io.memoryStage.inst0.inst_info.valid
|
||||
LSUOpType.isStore(io.memoryStage.inst0.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst0.commit := io.memoryStage.inst0.info.valid
|
||||
|
||||
io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
|
||||
io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info
|
||||
io.writeBackStage.inst1.info := io.memoryStage.inst1.info
|
||||
io.writeBackStage.inst1.rd_info.wdata := io.memoryStage.inst1.rd_info.wdata
|
||||
io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
|
||||
io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex
|
||||
io.writeBackStage.inst1.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
|
||||
LSUOpType.isLoad(io.memoryStage.inst1.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
LSUOpType.isLoad(io.memoryStage.inst1.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst1.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
|
||||
LSUOpType.isStore(io.memoryStage.inst1.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst1.commit := io.memoryStage.inst1.inst_info.valid &&
|
||||
LSUOpType.isStore(io.memoryStage.inst1.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
|
||||
io.writeBackStage.inst1.commit := io.memoryStage.inst1.info.valid &&
|
||||
!(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
|
||||
|
||||
io.csr.in.inst(0).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.pc, 0.U)
|
||||
io.csr.in.inst(0).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.ex, 0.U.asTypeOf(new ExceptionInfo()))
|
||||
io.csr.in.inst(0).inst_info := Mux(
|
||||
io.csr.in.inst(0).info := Mux(
|
||||
io.ctrl.allow_to_go,
|
||||
io.writeBackStage.inst0.inst_info,
|
||||
io.writeBackStage.inst0.info,
|
||||
0.U.asTypeOf(new InstInfo())
|
||||
)
|
||||
io.csr.in.inst(1).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.pc, 0.U)
|
||||
io.csr.in.inst(1).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.ex, 0.U.asTypeOf(new ExceptionInfo()))
|
||||
io.csr.in.inst(1).inst_info := Mux(
|
||||
io.csr.in.inst(1).info := Mux(
|
||||
io.ctrl.allow_to_go,
|
||||
io.writeBackStage.inst1.inst_info,
|
||||
io.writeBackStage.inst1.info,
|
||||
0.U.asTypeOf(new InstInfo())
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ import cpu.CpuConfig
|
|||
|
||||
class MemWbInst extends Bundle {
|
||||
val pc = UInt(PC_WID.W)
|
||||
val inst_info = new InstInfo()
|
||||
val info = new InstInfo()
|
||||
val rd_info = new RdInfo()
|
||||
val commit = Bool()
|
||||
val ex = new ExceptionInfo()
|
||||
|
|
|
|||
|
|
@ -15,18 +15,18 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
|
|||
val debug = new DEBUG()
|
||||
})
|
||||
|
||||
io.regfile(0).wen := io.writeBackStage.inst0.inst_info.reg_wen &&
|
||||
io.regfile(0).wen := io.writeBackStage.inst0.info.reg_wen &&
|
||||
io.ctrl.allow_to_go &&
|
||||
!(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
|
||||
io.regfile(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
|
||||
io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.inst_info.fusel)
|
||||
io.regfile(0).waddr := io.writeBackStage.inst0.info.reg_waddr
|
||||
io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
|
||||
|
||||
io.regfile(1).wen :=
|
||||
io.writeBackStage.inst1.inst_info.reg_wen && io.ctrl.allow_to_go &&
|
||||
io.writeBackStage.inst1.info.reg_wen && io.ctrl.allow_to_go &&
|
||||
!(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR) &&
|
||||
!(io.writeBackStage.inst1.ex.exception.asUInt.orR || io.writeBackStage.inst1.ex.interrupt.asUInt.orR)
|
||||
io.regfile(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
|
||||
io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.inst_info.fusel)
|
||||
io.regfile(1).waddr := io.writeBackStage.inst1.info.reg_waddr
|
||||
io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
|
||||
|
||||
if (config.hasCommitBuffer) {
|
||||
val buffer = Module(new CommitBuffer()).io
|
||||
|
|
|
|||
Loading…
Reference in New Issue