diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala
index 73230da..3dbc9e4 100644
--- a/chisel/playground/src/Core.scala
+++ b/chisel/playground/src/Core.scala
@@ -138,10 +138,10 @@ class Core(implicit val config: CpuConfig) extends Module {
 
   io.debug <> writeBackUnit.debug
 
-  io.inst.fence_i := executeUnit.executeStage.inst0.inst_info.fusel === FuType.mou &&
-    executeUnit.executeStage.inst0.inst_info.op === MOUOpType.fencei
-  io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.fusel === FuType.mou &&
-    memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei
+  io.inst.fence_i := executeUnit.executeStage.inst0.info.fusel === FuType.mou &&
+    executeUnit.executeStage.inst0.info.op === MOUOpType.fencei
+  io.data.fence_i := memoryUnit.memoryStage.inst0.info.fusel === FuType.mou &&
+    memoryUnit.memoryStage.inst0.info.op === MOUOpType.fencei
   io.inst.req       := !instFifo.full && !reset.asBool
   io.inst.cpu_ready := ctrl.fetchUnit.allow_to_go
   io.data.cpu_ready := ctrl.memoryUnit.allow_to_go
diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala
index a911c0f..6b636b3 100644
--- a/chisel/playground/src/pipeline/decoder/Decoder.scala
+++ b/chisel/playground/src/pipeline/decoder/Decoder.scala
@@ -13,7 +13,7 @@ class Decoder extends Module with HasInstrType {
     })
     // outputs
     val out = Output(new Bundle {
-      val inst_info = new InstInfo()
+      val info = new InstInfo()
     })
   })
 
@@ -36,25 +36,25 @@ class Decoder extends Module with HasInstrType {
 
   val (rs, rt, rd) = (inst(19, 15), inst(24, 20), inst(11, 7))
 
-  io.out.inst_info.valid      := false.B
-  io.out.inst_info.inst_legal := instrType =/= InstrN
-  io.out.inst_info.reg1_ren   := src1Type === SrcType.reg || inst(6, 0) === "b0110111".U // fix LUI
-  io.out.inst_info.reg1_raddr := Mux(io.out.inst_info.reg1_ren, rs, 0.U)
-  io.out.inst_info.reg2_ren   := src2Type === SrcType.reg
-  io.out.inst_info.reg2_raddr := Mux(io.out.inst_info.reg2_ren, rt, 0.U)
-  io.out.inst_info.fusel      := fuType
-  io.out.inst_info.op         := fuOpType
+  io.out.info.valid      := false.B
+  io.out.info.inst_legal := instrType =/= InstrN
+  io.out.info.reg1_ren   := src1Type === SrcType.reg || inst(6, 0) === "b0110111".U // fix LUI
+  io.out.info.reg1_raddr := Mux(io.out.info.reg1_ren, rs, 0.U)
+  io.out.info.reg2_ren   := src2Type === SrcType.reg
+  io.out.info.reg2_raddr := Mux(io.out.info.reg2_ren, rt, 0.U)
+  io.out.info.fusel      := fuType
+  io.out.info.op         := fuOpType
   // when(fuType === FuType.bru) {
   //   def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
-  //   when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.inst_info.op := ALUOpType.call }
+  //   when(isLink(rd) && fuOpType === ALUOpType.jal) { io.out.info.op := ALUOpType.call }
   //   when(fuOpType === ALUOpType.jalr) {
-  //     when(isLink(rs)) { io.out.inst_info.op := ALUOpType.ret }
-  //     when(isLink(rd)) { io.out.inst_info.op := ALUOpType.call }
+  //     when(isLink(rs)) { io.out.info.op := ALUOpType.ret }
+  //     when(isLink(rd)) { io.out.info.op := ALUOpType.call }
   //   }
   // }
-  io.out.inst_info.reg_wen   := isrfWen(instrType)
-  io.out.inst_info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
-  io.out.inst_info.imm := LookupTree(
+  io.out.info.reg_wen   := isrfWen(instrType)
+  io.out.info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
+  io.out.info.imm := LookupTree(
     instrType,
     Seq(
       InstrI  -> SignedExtend(inst(31, 20), XLEN),
@@ -65,6 +65,6 @@ class Decoder extends Module with HasInstrType {
       InstrJ  -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
     )
   )
-  io.out.inst_info.inst     := inst
-  io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
+  io.out.info.inst     := inst
+  io.out.info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
 }
diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
index 3bb9af4..5f75033 100644
--- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
+++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala
@@ -60,7 +60,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
 
   val pc        = io.instFifo.inst.map(_.pc)
   val inst      = io.instFifo.inst.map(_.inst)
-  val inst_info = decoder.map(_.io.out.inst_info)
+  val info = decoder.map(_.io.out.info)
   val priv_mode = io.csr.priv_mode
 
   issue.allow_to_go          := io.ctrl.allow_to_go
@@ -68,20 +68,20 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
   for (i <- 0 until (config.decoderNum)) {
     decoder(i).io.in.inst      := inst(i)
-    issue.decodeInst(i)        := inst_info(i)
+    issue.decodeInst(i)        := info(i)
     issue.execute(i).mem_wreg  := io.forward(i).mem_wreg
     issue.execute(i).reg_waddr := io.forward(i).exe.waddr
   }
   io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go
 
-  io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr
-  io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
-  io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr
-  io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr
+  io.regfile(0).src1.raddr := decoder(0).io.out.info.reg1_raddr
+  io.regfile(0).src2.raddr := decoder(0).io.out.info.reg2_raddr
+  io.regfile(1).src1.raddr := decoder(1).io.out.info.reg1_raddr
+  io.regfile(1).src2.raddr := decoder(1).io.out.info.reg2_raddr
   forwardCtrl.in.forward   := io.forward
   forwardCtrl.in.regfile   := io.regfile // TODO:这里的连接可能有问题
   jumpCtrl.in.allow_to_go  := io.ctrl.allow_to_go
-  jumpCtrl.in.inst_info    := decoder(0).io.out.inst_info
+  jumpCtrl.in.info    := decoder(0).io.out.info
   jumpCtrl.in.forward      := io.forward
   jumpCtrl.in.pc           := io.instFifo.inst(0).pc
   jumpCtrl.in.src_info     := io.executeStage.inst0.src_info
@@ -94,41 +94,41 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go
   io.bpu.id_allow_to_go      := io.ctrl.allow_to_go
   io.bpu.pc                  := io.instFifo.inst(0).pc
-  io.bpu.decoded_inst0       := decoder(0).io.out.inst_info
+  io.bpu.decoded_inst0       := decoder(0).io.out.info
   io.bpu.pht_index           := io.instFifo.inst(0).pht_index
 
-  io.ctrl.inst0.src1.ren   := decoder(0).io.out.inst_info.reg1_ren
-  io.ctrl.inst0.src1.raddr := decoder(0).io.out.inst_info.reg1_raddr
-  io.ctrl.inst0.src2.ren   := decoder(0).io.out.inst_info.reg2_ren
-  io.ctrl.inst0.src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
+  io.ctrl.inst0.src1.ren   := decoder(0).io.out.info.reg1_ren
+  io.ctrl.inst0.src1.raddr := decoder(0).io.out.info.reg1_raddr
+  io.ctrl.inst0.src2.ren   := decoder(0).io.out.info.reg2_ren
+  io.ctrl.inst0.src2.raddr := decoder(0).io.out.info.reg2_raddr
   io.ctrl.branch           := inst0_branch
 
   io.executeStage.inst0.pc              := pc(0)
-  io.executeStage.inst0.inst_info       := inst_info(0)
-  io.executeStage.inst0.inst_info.valid := !io.instFifo.info.empty
+  io.executeStage.inst0.info       := info(0)
+  io.executeStage.inst0.info.valid := !io.instFifo.info.empty
   io.executeStage.inst0.src_info.src1_data := Mux(
-    inst_info(0).reg1_ren,
+    info(0).reg1_ren,
     forwardCtrl.out.inst(0).src1.rdata,
     SignedExtend(pc(0), INST_ADDR_WID)
   )
   io.executeStage.inst0.src_info.src2_data := Mux(
-    inst_info(0).reg2_ren,
+    info(0).reg2_ren,
     forwardCtrl.out.inst(0).src2.rdata,
-    decoder(0).io.out.inst_info.imm
+    decoder(0).io.out.info.imm
   )
   (0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i))
   io.executeStage.inst0.ex.exception.map(_                := false.B)
-  io.executeStage.inst0.ex.exception(illegalInstr)        := !inst_info(0).inst_legal
+  io.executeStage.inst0.ex.exception(illegalInstr)        := !info(0).inst_legal
   io.executeStage.inst0.ex.exception(instrAccessFault)    := io.instFifo.inst(0).acc_err
   io.executeStage.inst0.ex.exception(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
-  io.executeStage.inst0.ex.exception(breakPoint) := inst_info(0).inst(31, 20) === privEbreak &&
-    inst_info(0).op === CSROpType.jmp
-  io.executeStage.inst0.ex.exception(ecallM) := inst_info(0).inst(31, 20) === privEcall &&
-    inst_info(0).op === CSROpType.jmp && priv_mode === ModeM && inst_info(0).fusel === FuType.csr
-  io.executeStage.inst0.ex.exception(ecallS) := inst_info(0).inst(31, 20) === privEcall &&
-    inst_info(0).op === CSROpType.jmp && priv_mode === ModeS && inst_info(0).fusel === FuType.csr
-  io.executeStage.inst0.ex.exception(ecallU) := inst_info(0).inst(31, 20) === privEcall &&
-    inst_info(0).op === CSROpType.jmp && priv_mode === ModeU && inst_info(0).fusel === FuType.csr
+  io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak &&
+    info(0).op === CSROpType.jmp
+  io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall &&
+    info(0).op === CSROpType.jmp && priv_mode === ModeM && info(0).fusel === FuType.csr
+  io.executeStage.inst0.ex.exception(ecallS) := info(0).inst(31, 20) === privEcall &&
+    info(0).op === CSROpType.jmp && priv_mode === ModeS && info(0).fusel === FuType.csr
+  io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall &&
+    info(0).op === CSROpType.jmp && priv_mode === ModeU && info(0).fusel === FuType.csr
   io.executeStage.inst0.ex.tval := Mux(
     io.executeStage.inst0.ex.exception(instrAccessFault) || io.executeStage.inst0.ex.exception(instrAddrMisaligned),
     io.instFifo.inst(0).pc,
@@ -142,31 +142,31 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
 
   io.executeStage.inst1.pc              := pc(1)
-  io.executeStage.inst1.inst_info       := inst_info(1)
-  io.executeStage.inst1.inst_info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
+  io.executeStage.inst1.info       := info(1)
+  io.executeStage.inst1.info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
   io.executeStage.inst1.src_info.src1_data := Mux(
-    inst_info(1).reg1_ren,
+    info(1).reg1_ren,
     forwardCtrl.out.inst(1).src1.rdata,
     SignedExtend(pc(1), INST_ADDR_WID)
   )
   io.executeStage.inst1.src_info.src2_data := Mux(
-    inst_info(1).reg2_ren,
+    info(1).reg2_ren,
     forwardCtrl.out.inst(1).src2.rdata,
-    decoder(1).io.out.inst_info.imm
+    decoder(1).io.out.info.imm
   )
   (0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i))
   io.executeStage.inst1.ex.exception.map(_                := false.B)
-  io.executeStage.inst1.ex.exception(illegalInstr)        := !inst_info(1).inst_legal
+  io.executeStage.inst1.ex.exception(illegalInstr)        := !info(1).inst_legal
   io.executeStage.inst1.ex.exception(instrAccessFault)    := io.instFifo.inst(1).acc_err
   io.executeStage.inst1.ex.exception(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
-  io.executeStage.inst1.ex.exception(breakPoint) := inst_info(1).inst(31, 20) === privEbreak &&
-    inst_info(1).op === CSROpType.jmp
-  io.executeStage.inst1.ex.exception(ecallM) := inst_info(1).inst(31, 20) === privEcall &&
-    inst_info(1).op === CSROpType.jmp && priv_mode === ModeM && inst_info(1).fusel === FuType.csr
-  io.executeStage.inst1.ex.exception(ecallS) := inst_info(1).inst(31, 20) === privEcall &&
-    inst_info(1).op === CSROpType.jmp && priv_mode === ModeS && inst_info(1).fusel === FuType.csr
-  io.executeStage.inst1.ex.exception(ecallU) := inst_info(1).inst(31, 20) === privEcall &&
-    inst_info(1).op === CSROpType.jmp && priv_mode === ModeU && inst_info(1).fusel === FuType.csr
+  io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak &&
+    info(1).op === CSROpType.jmp
+  io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall &&
+    info(1).op === CSROpType.jmp && priv_mode === ModeM && info(1).fusel === FuType.csr
+  io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall &&
+    info(1).op === CSROpType.jmp && priv_mode === ModeS && info(1).fusel === FuType.csr
+  io.executeStage.inst1.ex.exception(ecallU) := info(1).inst(31, 20) === privEcall &&
+    info(1).op === CSROpType.jmp && priv_mode === ModeU && info(1).fusel === FuType.csr
 
   io.executeStage.inst1.ex.tval := Mux(
     io.executeStage.inst1.ex.exception(instrAccessFault) || io.executeStage.inst1.ex.exception(instrAddrMisaligned),
diff --git a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
index 60b185f..13d0146 100644
--- a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
+++ b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala
@@ -12,7 +12,7 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
     val in = Input(new Bundle {
       val allow_to_go = Bool()
       val pc          = UInt(PC_WID.W)
-      val inst_info   = new InstInfo()
+      val info   = new InstInfo()
       val src_info    = new SrcInfo()
       val forward     = Vec(config.fuNum, new DataForwardToDecoderUnit())
     })
@@ -24,22 +24,22 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
     })
   })
 
-  val op                 = io.in.inst_info.op
+  val op                 = io.in.info.op
   val jump_inst          = VecInit(ALUOpType.jal).contains(op)
   val jump_register_inst = VecInit(ALUOpType.jalr).contains(op)
   io.out.jump_inst := jump_inst || jump_register_inst
   io.out.jump      := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register)
   if (config.decoderNum == 2) {
     io.out.jump_register := jump_register_inst &&
-    ((io.in.forward(0).exe.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).exe.waddr) ||
-    (io.in.forward(1).exe.wen && io.in.inst_info.reg1_raddr === io.in.forward(1).exe.waddr) ||
-    (io.in.forward(0).mem.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).mem.waddr) ||
-    (io.in.forward(1).mem.wen && io.in.inst_info.reg1_raddr === io.in.forward(1).mem.waddr))
+    ((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) ||
+    (io.in.forward(1).exe.wen && io.in.info.reg1_raddr === io.in.forward(1).exe.waddr) ||
+    (io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr) ||
+    (io.in.forward(1).mem.wen && io.in.info.reg1_raddr === io.in.forward(1).mem.waddr))
 
   } else {
     io.out.jump_register := jump_register_inst &&
-    ((io.in.forward(0).exe.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).exe.waddr) ||
-    (io.in.forward(0).mem.wen && io.in.inst_info.reg1_raddr === io.in.forward(0).mem.waddr))
+    ((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) ||
+    (io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr))
   }
   io.out.jump_target := Mux(
     jump_inst,
diff --git a/chisel/playground/src/pipeline/execute/ALU.scala b/chisel/playground/src/pipeline/execute/ALU.scala
index 9d5900c..068aba4 100644
--- a/chisel/playground/src/pipeline/execute/ALU.scala
+++ b/chisel/playground/src/pipeline/execute/ALU.scala
@@ -21,11 +21,11 @@ class MultSignal extends Bundle {
 }
 class Alu extends Module {
   val io = IO(new Bundle {
-    val inst_info = Input(new InstInfo())
+    val info = Input(new InstInfo())
     val src_info  = Input(new SrcInfo())
     val result    = Output(UInt(DATA_WID.W))
   })
-  val op     = io.inst_info.op
+  val op     = io.info.op
   val src1   = io.src_info.src1_data
   val src2   = io.src_info.src2_data
   val is_sub = !ALUOpType.isAdd(op)
diff --git a/chisel/playground/src/pipeline/execute/BranchCtrl.scala b/chisel/playground/src/pipeline/execute/BranchCtrl.scala
index e04112d..8e6770a 100644
--- a/chisel/playground/src/pipeline/execute/BranchCtrl.scala
+++ b/chisel/playground/src/pipeline/execute/BranchCtrl.scala
@@ -8,7 +8,7 @@ import cpu.defines.Const._
 class BranchCtrl extends Module {
   val io = IO(new Bundle {
     val in = new Bundle {
-      val inst_info   = Input(new InstInfo())
+      val info   = Input(new InstInfo())
       val src_info    = Input(new SrcInfo())
       val pred_branch = Input(Bool())
     }
@@ -18,10 +18,10 @@ class BranchCtrl extends Module {
     }
   })
   val valid =
-    io.in.inst_info.fusel === FuType.bru && ALUOpType.isBranch(io.in.inst_info.op) && io.in.inst_info.valid
+    io.in.info.fusel === FuType.bru && ALUOpType.isBranch(io.in.info.op) && io.in.info.valid
   val src1   = io.in.src_info.src1_data
   val src2   = io.in.src_info.src2_data
-  val op     = io.in.inst_info.op
+  val op     = io.in.info.op
   val is_sub = !ALUOpType.isAdd(op)
   val adder  = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub
   val xor    = src1 ^ src2
diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala
index f3b754b..ba5a9d8 100644
--- a/chisel/playground/src/pipeline/execute/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/Csr.scala
@@ -14,7 +14,7 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
       new Bundle {
         val pc        = UInt(PC_WID.W)
         val ex        = new ExceptionInfo()
-        val inst_info = new InstInfo()
+        val info = new InstInfo()
       }
     )
   })
@@ -27,7 +27,7 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
 class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
   val in = Input(new Bundle {
     val valid     = Bool()
-    val inst_info = new InstInfo()
+    val info = new InstInfo()
     val src_info  = new SrcInfo()
     val ex        = new ExceptionInfo()
   })
@@ -213,18 +213,18 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
       !(io.memoryUnit.in.inst(1).ex.exception.asUInt.orR || io.memoryUnit.in.inst(1).ex.interrupt.asUInt.orR)
   val mem_pc        = Mux(exc_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc)
   val mem_ex        = Mux(exc_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
-  val mem_inst_info = Mux(exc_sel, io.memoryUnit.in.inst(0).inst_info, io.memoryUnit.in.inst(1).inst_info)
+  val mem_inst_info = Mux(exc_sel, io.memoryUnit.in.inst(0).info, io.memoryUnit.in.inst(1).info)
   val mem_inst      = mem_inst_info.inst
   val mem_valid     = mem_inst_info.valid
   val mem_addr      = mem_inst(31, 20)
   // 不带前缀的信号为exe阶段的信号
   val valid     = io.executeUnit.in.valid
-  val inst_info = io.executeUnit.in.inst_info
-  val op        = io.executeUnit.in.inst_info.op
-  val fusel     = io.executeUnit.in.inst_info.fusel
-  val addr      = io.executeUnit.in.inst_info.inst(31, 20)
+  val info = io.executeUnit.in.info
+  val op        = io.executeUnit.in.info.op
+  val fusel     = io.executeUnit.in.info.fusel
+  val addr      = io.executeUnit.in.info.inst(31, 20)
   val src1      = io.executeUnit.in.src_info.src1_data
-  val csri      = ZeroExtend(io.executeUnit.in.inst_info.inst(19, 15), XLEN)
+  val csri      = ZeroExtend(io.executeUnit.in.info.inst(19, 15), XLEN)
   val exe_stall = io.ctrl.exe_stall
   val mem_stall = io.ctrl.mem_stall
   wdata := LookupTree(
diff --git a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
index 3d0055d..d96b7be 100644
--- a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
+++ b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
@@ -13,7 +13,7 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
         val en        = Bool()
         val ren       = Bool()
         val wen       = Bool()
-        val inst_info = new InstInfo()
+        val info = new InstInfo()
         val addr      = UInt(DATA_ADDR_WID.W)
         val wdata     = UInt(DATA_WID.W)
       })
@@ -22,7 +22,7 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
     val inst = Vec(
       config.fuNum,
       new Bundle {
-        val inst_info = Input(new InstInfo())
+        val info = Input(new InstInfo())
         val src_info  = Input(new SrcInfo())
         val ex = new Bundle {
           val in  = Input(new ExceptionInfo())
@@ -33,37 +33,37 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
     )
   })
   io.mem.out.en := io.inst.map(_.mem_sel).reduce(_ || _)
-  io.mem.out.ren := io.inst(0).mem_sel && LSUOpType.isLoad(io.inst(0).inst_info.op) ||
-    io.inst(1).mem_sel && LSUOpType.isLoad(io.inst(1).inst_info.op)
-  io.mem.out.wen := io.inst(0).mem_sel && LSUOpType.isStore(io.inst(0).inst_info.op) ||
-    io.inst(1).mem_sel && LSUOpType.isStore(io.inst(1).inst_info.op)
-  io.mem.out.inst_info := Mux1H(
+  io.mem.out.ren := io.inst(0).mem_sel && LSUOpType.isLoad(io.inst(0).info.op) ||
+    io.inst(1).mem_sel && LSUOpType.isLoad(io.inst(1).info.op)
+  io.mem.out.wen := io.inst(0).mem_sel && LSUOpType.isStore(io.inst(0).info.op) ||
+    io.inst(1).mem_sel && LSUOpType.isStore(io.inst(1).info.op)
+  io.mem.out.info := Mux1H(
     Seq(
-      (io.inst(0).inst_info.fusel === FuType.lsu) -> io.inst(0).inst_info,
-      (io.inst(1).inst_info.fusel === FuType.lsu) -> io.inst(1).inst_info
+      (io.inst(0).info.fusel === FuType.lsu) -> io.inst(0).info,
+      (io.inst(1).info.fusel === FuType.lsu) -> io.inst(1).info
     )
   )
   val mem_addr = Wire(Vec(config.fuNum, UInt(DATA_ADDR_WID.W)))
-  mem_addr(0) := io.inst(0).src_info.src1_data + io.inst(0).inst_info.imm
-  mem_addr(1) := io.inst(1).src_info.src1_data + io.inst(1).inst_info.imm
+  mem_addr(0) := io.inst(0).src_info.src1_data + io.inst(0).info.imm
+  mem_addr(1) := io.inst(1).src_info.src1_data + io.inst(1).info.imm
   io.mem.out.addr := Mux1H(
     Seq(
-      (io.inst(0).inst_info.fusel === FuType.lsu) -> mem_addr(0),
-      (io.inst(1).inst_info.fusel === FuType.lsu) -> mem_addr(1)
+      (io.inst(0).info.fusel === FuType.lsu) -> mem_addr(0),
+      (io.inst(1).info.fusel === FuType.lsu) -> mem_addr(1)
     )
   )
   io.mem.out.wdata := Mux1H(
     Seq(
-      (io.inst(0).inst_info.fusel === FuType.lsu) ->
+      (io.inst(0).info.fusel === FuType.lsu) ->
         io.inst(0).src_info.src2_data,
-      (io.inst(1).inst_info.fusel === FuType.lsu) ->
+      (io.inst(1).info.fusel === FuType.lsu) ->
         io.inst(1).src_info.src2_data
     )
   )
   val addr_aligned = Wire(Vec(config.fuNum, Bool()))
   for (i <- 0 until config.fuNum) {
     addr_aligned(i) := LookupTree(
-      io.inst(i).inst_info.op(1, 0),
+      io.inst(i).info.op(1, 0),
       List(
         "b00".U -> true.B, //b
         "b01".U -> (mem_addr(i)(0) === 0.U), //h
@@ -74,17 +74,17 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
   }
 
   for (i <- 0 until config.fuNum) {
-    val store_inst = LSUOpType.isStore(io.inst(i).inst_info.op)
+    val store_inst = LSUOpType.isStore(io.inst(i).info.op)
     io.inst(i).ex.out                                := io.inst(i).ex.in
     io.inst(i).ex.out.exception(loadAddrMisaligned)  := store_inst && !addr_aligned(i)
     io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i)
   }
-  io.inst(0).mem_sel := (io.inst(0).inst_info.fusel === FuType.lsu) &&
+  io.inst(0).mem_sel := (io.inst(0).info.fusel === FuType.lsu) &&
     !(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&
-    io.inst(0).inst_info.valid
-  io.inst(1).mem_sel := (io.inst(1).inst_info.fusel === FuType.lsu) &&
+    io.inst(0).info.valid
+  io.inst(1).mem_sel := (io.inst(1).info.fusel === FuType.lsu) &&
     !(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&
     !(io.inst(1).ex.out.exception.asUInt.orR || io.inst(1).ex.out.interrupt.asUInt.orR) &&
-    io.inst(1).inst_info.valid
+    io.inst(1).info.valid
 
 }
diff --git a/chisel/playground/src/pipeline/execute/ExecuteStage.scala b/chisel/playground/src/pipeline/execute/ExecuteStage.scala
index f166948..99d2029 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteStage.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteStage.scala
@@ -9,7 +9,7 @@ import cpu.{BranchPredictorConfig, CpuConfig}
 class IdExeInst0 extends Bundle {
   val config    = new BranchPredictorConfig()
   val pc        = UInt(PC_WID.W)
-  val inst_info = new InstInfo()
+  val info = new InstInfo()
   val src_info  = new SrcInfo()
   val ex        = new ExceptionInfo()
   val jb_info = new Bundle {
@@ -26,7 +26,7 @@ class IdExeInst0 extends Bundle {
 class IdExeInst1 extends Bundle {
   val allow_to_go = Bool()
   val pc          = UInt(PC_WID.W)
-  val inst_info   = new InstInfo()
+  val info   = new InstInfo()
   val src_info    = new SrcInfo()
   val ex          = new ExceptionInfo()
 }
diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index d551929..4c104eb 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -37,27 +37,27 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
 
   val valid = VecInit(
-    io.executeStage.inst0.inst_info.valid && io.ctrl.allow_to_go,
-    io.executeStage.inst1.inst_info.valid && io.ctrl.allow_to_go
+    io.executeStage.inst0.info.valid && io.ctrl.allow_to_go,
+    io.executeStage.inst1.info.valid && io.ctrl.allow_to_go
   )
 
-  io.ctrl.inst(0).mem_wreg  := io.executeStage.inst0.inst_info.mem_wreg
-  io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr
-  io.ctrl.inst(1).mem_wreg  := io.executeStage.inst1.inst_info.mem_wreg
-  io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr
+  io.ctrl.inst(0).mem_wreg  := io.executeStage.inst0.info.mem_wreg
+  io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.info.reg_waddr
+  io.ctrl.inst(1).mem_wreg  := io.executeStage.inst1.info.mem_wreg
+  io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.info.reg_waddr
   io.ctrl.branch := valid(0) && io.ctrl.allow_to_go &&
     (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
 
-  val csr_sel0 = valid(0) && io.executeStage.inst0.inst_info.fusel === FuType.csr &&
+  val csr_sel0 = valid(0) && io.executeStage.inst0.info.fusel === FuType.csr &&
     !(io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR)
-  val csr_sel1 = valid(1) && io.executeStage.inst1.inst_info.fusel === FuType.csr &&
+  val csr_sel1 = valid(1) && io.executeStage.inst1.info.fusel === FuType.csr &&
     !(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR)
   io.csr.in.valid := (csr_sel0 || csr_sel1)
-  io.csr.in.inst_info := MuxCase(
+  io.csr.in.info := MuxCase(
     0.U.asTypeOf(new InstInfo()),
     Seq(
-      csr_sel0 -> io.executeStage.inst0.inst_info,
-      csr_sel1 -> io.executeStage.inst1.inst_info
+      csr_sel0 -> io.executeStage.inst0.info,
+      csr_sel1 -> io.executeStage.inst1.info
     )
   )
   io.csr.in.src_info := MuxCase(
@@ -76,30 +76,30 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   )
 
   // input accessMemCtrl
-  accessMemCtrl.inst(0).inst_info := io.executeStage.inst0.inst_info
+  accessMemCtrl.inst(0).info := io.executeStage.inst0.info
   accessMemCtrl.inst(0).src_info  := io.executeStage.inst0.src_info
   accessMemCtrl.inst(0).ex.in     := io.executeStage.inst0.ex
-  accessMemCtrl.inst(1).inst_info := io.executeStage.inst1.inst_info
+  accessMemCtrl.inst(1).info := io.executeStage.inst1.info
   accessMemCtrl.inst(1).src_info  := io.executeStage.inst1.src_info
   accessMemCtrl.inst(1).ex.in     := io.executeStage.inst1.ex
 
   // input fu
   fu.ctrl <> io.ctrl.fu
   fu.inst(0).pc := io.executeStage.inst0.pc
-  fu.inst(0).mul_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
-    !MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
-  fu.inst(0).div_en := io.executeStage.inst0.inst_info.fusel === FuType.mdu &&
-    MDUOpType.isDiv(io.executeStage.inst0.inst_info.op)
-  fu.inst(0).inst_info := io.executeStage.inst0.inst_info
+  fu.inst(0).mul_en := io.executeStage.inst0.info.fusel === FuType.mdu &&
+    !MDUOpType.isDiv(io.executeStage.inst0.info.op)
+  fu.inst(0).div_en := io.executeStage.inst0.info.fusel === FuType.mdu &&
+    MDUOpType.isDiv(io.executeStage.inst0.info.op)
+  fu.inst(0).info := io.executeStage.inst0.info
   fu.inst(0).src_info  := io.executeStage.inst0.src_info
   fu.inst(0).ex.in :=
-    Mux(io.executeStage.inst0.inst_info.fusel === FuType.lsu, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
+    Mux(io.executeStage.inst0.info.fusel === FuType.lsu, accessMemCtrl.inst(0).ex.out, io.executeStage.inst0.ex)
   fu.inst(1).pc := io.executeStage.inst1.pc
-  fu.inst(1).mul_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
-    !MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
-  fu.inst(1).div_en := io.executeStage.inst1.inst_info.fusel === FuType.mdu &&
-    MDUOpType.isDiv(io.executeStage.inst1.inst_info.op)
-  fu.inst(1).inst_info  := io.executeStage.inst1.inst_info
+  fu.inst(1).mul_en := io.executeStage.inst1.info.fusel === FuType.mdu &&
+    !MDUOpType.isDiv(io.executeStage.inst1.info.op)
+  fu.inst(1).div_en := io.executeStage.inst1.info.fusel === FuType.mdu &&
+    MDUOpType.isDiv(io.executeStage.inst1.info.op)
+  fu.inst(1).info  := io.executeStage.inst1.info
   fu.inst(1).src_info   := io.executeStage.inst1.src_info
   fu.inst(1).ex.in      := io.executeStage.inst1.ex
   fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
@@ -127,21 +127,21 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.memoryStage.inst0.mem.addr      := accessMemCtrl.mem.out.addr
   io.memoryStage.inst0.mem.wdata     := accessMemCtrl.mem.out.wdata
   io.memoryStage.inst0.mem.sel       := accessMemCtrl.inst.map(_.mem_sel)
-  io.memoryStage.inst0.mem.inst_info := accessMemCtrl.mem.out.inst_info
+  io.memoryStage.inst0.mem.info := accessMemCtrl.mem.out.info
 
   io.memoryStage.inst0.pc                        := io.executeStage.inst0.pc
-  io.memoryStage.inst0.inst_info                 := io.executeStage.inst0.inst_info
+  io.memoryStage.inst0.info                 := io.executeStage.inst0.info
   io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
   io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
   io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
   io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
   io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
   val has_ex0 =
-    (io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR) && io.executeStage.inst0.inst_info.valid
+    (io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR) && io.executeStage.inst0.info.valid
   io.memoryStage.inst0.ex := Mux(
     has_ex0,
     io.executeStage.inst0.ex,
-    MuxLookup(io.executeStage.inst0.inst_info.fusel, io.executeStage.inst0.ex)(
+    MuxLookup(io.executeStage.inst0.info.fusel, io.executeStage.inst0.ex)(
       Seq(
         FuType.alu -> fu.inst(0).ex.out,
         FuType.mdu -> fu.inst(0).ex.out,
@@ -152,18 +152,18 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   )
 
   io.memoryStage.inst1.pc                        := io.executeStage.inst1.pc
-  io.memoryStage.inst1.inst_info                 := io.executeStage.inst1.inst_info
+  io.memoryStage.inst1.info                 := io.executeStage.inst1.info
   io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
   io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
   io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
   io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
   io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
   val has_ex1 =
-    (io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR) && io.executeStage.inst1.inst_info.valid
+    (io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR) && io.executeStage.inst1.info.valid
   io.memoryStage.inst1.ex := Mux(
     has_ex1,
     io.executeStage.inst1.ex,
-    MuxLookup(io.executeStage.inst1.inst_info.fusel, io.executeStage.inst1.ex)(
+    MuxLookup(io.executeStage.inst1.info.fusel, io.executeStage.inst1.ex)(
       Seq(
         FuType.alu -> fu.inst(1).ex.out,
         FuType.mdu -> fu.inst(1).ex.out,
@@ -173,13 +173,13 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     )
   )
 
-  io.decoderUnit.forward(0).exe.wen      := io.memoryStage.inst0.inst_info.reg_wen
-  io.decoderUnit.forward(0).exe.waddr    := io.memoryStage.inst0.inst_info.reg_waddr
-  io.decoderUnit.forward(0).exe.wdata    := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.inst_info.fusel)
-  io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.inst_info.mem_wreg
+  io.decoderUnit.forward(0).exe.wen      := io.memoryStage.inst0.info.reg_wen
+  io.decoderUnit.forward(0).exe.waddr    := io.memoryStage.inst0.info.reg_waddr
+  io.decoderUnit.forward(0).exe.wdata    := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.info.fusel)
+  io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.info.mem_wreg
 
-  io.decoderUnit.forward(1).exe.wen      := io.memoryStage.inst1.inst_info.reg_wen
-  io.decoderUnit.forward(1).exe.waddr    := io.memoryStage.inst1.inst_info.reg_waddr
-  io.decoderUnit.forward(1).exe.wdata    := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.inst_info.fusel)
-  io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.inst_info.mem_wreg
+  io.decoderUnit.forward(1).exe.wen      := io.memoryStage.inst1.info.reg_wen
+  io.decoderUnit.forward(1).exe.waddr    := io.memoryStage.inst1.info.reg_waddr
+  io.decoderUnit.forward(1).exe.wdata    := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.info.fusel)
+  io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.info.mem_wreg
 }
diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala
index bec0f98..683ed3f 100644
--- a/chisel/playground/src/pipeline/execute/Fu.scala
+++ b/chisel/playground/src/pipeline/execute/Fu.scala
@@ -15,7 +15,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
         val pc        = Input(UInt(PC_WID.W))
         val mul_en    = Input(Bool())
         val div_en    = Input(Bool())
-        val inst_info = Input(new InstInfo())
+        val info = Input(new InstInfo())
         val src_info  = Input(new SrcInfo())
         val ex = new Bundle {
           val in  = Input(new ExceptionInfo())
@@ -40,14 +40,14 @@ class Fu(implicit val config: CpuConfig) extends Module {
 //   val div        = Module(new Div()).io
   val branchCtrl = Module(new BranchCtrl()).io
 
-  branchCtrl.in.inst_info   := io.inst(0).inst_info
+  branchCtrl.in.info   := io.inst(0).info
   branchCtrl.in.src_info    := io.inst(0).src_info
   branchCtrl.in.pred_branch := io.branch.pred_branch
   io.branch.branch          := branchCtrl.out.branch
   io.branch.pred_fail       := branchCtrl.out.pred_fail
 
   for (i <- 0 until (config.fuNum)) {
-    alu(i).io.inst_info := io.inst(i).inst_info
+    alu(i).io.info := io.inst(i).info
     alu(i).io.src_info  := io.inst(i).src_info
     // alu(i).io.mul.result        := mul.result
     // alu(i).io.mul.ready         := mul.ready
@@ -74,7 +74,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
   io.stall_req := false.B
 
   io.inst(0).result.alu := Mux(
-    ALUOpType.isBru(io.inst(0).inst_info.op),
+    ALUOpType.isBru(io.inst(0).info.op),
     io.inst(0).pc + 4.U,
     alu(0).io.result
   )
diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
index 9d43164..1630d08 100644
--- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
+++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
@@ -26,7 +26,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
     val memoryUnit = new Bundle {
       val in = Input(new Bundle {
         val mem_en    = Bool()
-        val inst_info = new InstInfo()
+        val info = new InstInfo()
         val mem_wdata = UInt(DATA_WID.W)
         val mem_addr  = UInt(DATA_ADDR_WID.W)
         val mem_sel   = Vec(config.fuNum, Bool())
@@ -44,7 +44,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
   val mem_addr2 = mem_addr(1, 0)
   val mem_rdata = io.dataMemory.in.rdata
   val mem_wdata = io.memoryUnit.in.mem_wdata
-  val op        = io.memoryUnit.in.inst_info.op
+  val op        = io.memoryUnit.in.info.op
   io.dataMemory.out.en := io.memoryUnit.in.mem_en &&
     (io.memoryUnit.in.mem_sel(0) &&
       !(io.memoryUnit.in.ex(0).exception.asUInt.orR || io.memoryUnit.in.ex(0).interrupt.asUInt.orR) ||
diff --git a/chisel/playground/src/pipeline/memory/MemoryStage.scala b/chisel/playground/src/pipeline/memory/MemoryStage.scala
index 9b48b6f..9649486 100644
--- a/chisel/playground/src/pipeline/memory/MemoryStage.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryStage.scala
@@ -8,7 +8,7 @@ import cpu.CpuConfig
 
 class ExeMemInst1 extends Bundle {
   val pc        = UInt(PC_WID.W)
-  val inst_info = new InstInfo()
+  val info = new InstInfo()
   val rd_info   = new RdInfo()
   val ex        = new ExceptionInfo()
 }
@@ -18,7 +18,7 @@ class ExeMemInst0(implicit val config: CpuConfig) extends ExeMemInst1 {
     val en        = Bool()
     val ren       = Bool()
     val wen       = Bool()
-    val inst_info = new InstInfo()
+    val info = new InstInfo()
     val addr      = UInt(DATA_ADDR_WID.W)
     val wdata     = UInt(DATA_WID.W)
     val sel       = Vec(config.fuNum, Bool())
diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
index 05634de..7099d7d 100644
--- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
@@ -25,7 +25,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
 
   val dataMemoryAccess = Module(new DataMemoryAccess()).io
   dataMemoryAccess.memoryUnit.in.mem_en    := io.memoryStage.inst0.mem.en
-  dataMemoryAccess.memoryUnit.in.inst_info := io.memoryStage.inst0.mem.inst_info
+  dataMemoryAccess.memoryUnit.in.info := io.memoryStage.inst0.mem.info
   dataMemoryAccess.memoryUnit.in.mem_wdata := io.memoryStage.inst0.mem.wdata
   dataMemoryAccess.memoryUnit.in.mem_addr  := io.memoryStage.inst0.mem.addr
   dataMemoryAccess.memoryUnit.in.mem_sel   := io.memoryStage.inst0.mem.sel
@@ -35,48 +35,48 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
   dataMemoryAccess.dataMemory.in.rdata     := io.dataMemory.in.rdata
   io.dataMemory.out                        := dataMemoryAccess.dataMemory.out
 
-  io.decoderUnit(0).wen   := io.writeBackStage.inst0.inst_info.reg_wen
-  io.decoderUnit(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
-  io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.inst_info.fusel)
-  io.decoderUnit(1).wen   := io.writeBackStage.inst1.inst_info.reg_wen
-  io.decoderUnit(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
-  io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.inst_info.fusel)
+  io.decoderUnit(0).wen   := io.writeBackStage.inst0.info.reg_wen
+  io.decoderUnit(0).waddr := io.writeBackStage.inst0.info.reg_waddr
+  io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
+  io.decoderUnit(1).wen   := io.writeBackStage.inst1.info.reg_wen
+  io.decoderUnit(1).waddr := io.writeBackStage.inst1.info.reg_waddr
+  io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
 
   io.writeBackStage.inst0.pc                        := io.memoryStage.inst0.pc
-  io.writeBackStage.inst0.inst_info                 := io.memoryStage.inst0.inst_info
+  io.writeBackStage.inst0.info                 := io.memoryStage.inst0.info
   io.writeBackStage.inst0.rd_info.wdata             := io.memoryStage.inst0.rd_info.wdata
   io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
   io.writeBackStage.inst0.ex                        := io.memoryStage.inst0.ex
   io.writeBackStage.inst0.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
-    LSUOpType.isLoad(io.memoryStage.inst0.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
+    LSUOpType.isLoad(io.memoryStage.inst0.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
   io.writeBackStage.inst0.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
-    LSUOpType.isStore(io.memoryStage.inst0.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
-  io.writeBackStage.inst0.commit := io.memoryStage.inst0.inst_info.valid
+    LSUOpType.isStore(io.memoryStage.inst0.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
+  io.writeBackStage.inst0.commit := io.memoryStage.inst0.info.valid
 
   io.writeBackStage.inst1.pc                        := io.memoryStage.inst1.pc
-  io.writeBackStage.inst1.inst_info                 := io.memoryStage.inst1.inst_info
+  io.writeBackStage.inst1.info                 := io.memoryStage.inst1.info
   io.writeBackStage.inst1.rd_info.wdata             := io.memoryStage.inst1.rd_info.wdata
   io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
   io.writeBackStage.inst1.ex                        := io.memoryStage.inst1.ex
   io.writeBackStage.inst1.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
-    LSUOpType.isLoad(io.memoryStage.inst1.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
+    LSUOpType.isLoad(io.memoryStage.inst1.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
   io.writeBackStage.inst1.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
-    LSUOpType.isStore(io.memoryStage.inst1.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
-  io.writeBackStage.inst1.commit := io.memoryStage.inst1.inst_info.valid &&
+    LSUOpType.isStore(io.memoryStage.inst1.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
+  io.writeBackStage.inst1.commit := io.memoryStage.inst1.info.valid &&
     !(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
 
   io.csr.in.inst(0).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.pc, 0.U)
   io.csr.in.inst(0).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.ex, 0.U.asTypeOf(new ExceptionInfo()))
-  io.csr.in.inst(0).inst_info := Mux(
+  io.csr.in.inst(0).info := Mux(
     io.ctrl.allow_to_go,
-    io.writeBackStage.inst0.inst_info,
+    io.writeBackStage.inst0.info,
     0.U.asTypeOf(new InstInfo())
   )
   io.csr.in.inst(1).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.pc, 0.U)
   io.csr.in.inst(1).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.ex, 0.U.asTypeOf(new ExceptionInfo()))
-  io.csr.in.inst(1).inst_info := Mux(
+  io.csr.in.inst(1).info := Mux(
     io.ctrl.allow_to_go,
-    io.writeBackStage.inst1.inst_info,
+    io.writeBackStage.inst1.info,
     0.U.asTypeOf(new InstInfo())
   )
 
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
index 8e7e360..160a557 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
@@ -8,7 +8,7 @@ import cpu.CpuConfig
 
 class MemWbInst extends Bundle {
   val pc        = UInt(PC_WID.W)
-  val inst_info = new InstInfo()
+  val info = new InstInfo()
   val rd_info   = new RdInfo()
   val commit     = Bool()
   val ex        = new ExceptionInfo()
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 93aa26e..3c4c4dd 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -15,18 +15,18 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
     val debug          = new DEBUG()
   })
 
-  io.regfile(0).wen := io.writeBackStage.inst0.inst_info.reg_wen &&
+  io.regfile(0).wen := io.writeBackStage.inst0.info.reg_wen &&
     io.ctrl.allow_to_go &&
     !(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
-  io.regfile(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
-  io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.inst_info.fusel)
+  io.regfile(0).waddr := io.writeBackStage.inst0.info.reg_waddr
+  io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
 
   io.regfile(1).wen :=
-    io.writeBackStage.inst1.inst_info.reg_wen && io.ctrl.allow_to_go &&
+    io.writeBackStage.inst1.info.reg_wen && io.ctrl.allow_to_go &&
       !(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR) &&
       !(io.writeBackStage.inst1.ex.exception.asUInt.orR || io.writeBackStage.inst1.ex.interrupt.asUInt.orR)
-  io.regfile(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
-  io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.inst_info.fusel)
+  io.regfile(1).waddr := io.writeBackStage.inst1.info.reg_waddr
+  io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
 
   if (config.hasCommitBuffer) {
     val buffer = Module(new CommitBuffer()).io