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fix(csr): 修复mpp写问题

This commit is contained in:
Liphen 2023-11-30 18:43:53 +08:00
parent 69f5974661
commit 5512fb26ec
1 changed files with 11 additions and 3 deletions
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14
chisel/playground/src/pipeline/execute/Csr.scala
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@ -100,6 +100,9 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
val pmpaddr3 = RegInit(UInt(XLEN.W), 0.U)
val pmpaddrWmask = "h3fffffff".U(64.W) // 32bit physical address
val rdata = Wire(UInt(XLEN.W))
val wdata = Wire(UInt(XLEN.W))
// Side Effect
def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
@ -107,6 +110,12 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
mstatusNew
}
val mstatus_wmask = Mux(
wdata.asTypeOf(new Mstatus).mpp === ModeM || wdata.asTypeOf(new Mstatus).mpp === ModeU,
"h0000000000021888".U(64.W),
"h0000000000020088".U(64.W)
)
// CSR reg map
val mapping = Map(
// User Trap Setup
@ -151,7 +160,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
MaskedRegMap(Mimpid, mimpid, 0.U, MaskedRegMap.Unwritable),
MaskedRegMap(Mhartid, mhartid, 0.U, MaskedRegMap.Unwritable),
// Machine Trap Setup
MaskedRegMap(Mstatus, mstatus, "h0000000000021888".U(64.W)),
MaskedRegMap(Mstatus, mstatus, mstatus_wmask),
MaskedRegMap(Misa, misa), // now MXL, EXT is not changeable
// MaskedRegMap(Medeleg, medeleg, "hbbff".U(64.W)), TODO
// MaskedRegMap(Mideleg, mideleg, "h222".U(64.W)),
@ -214,12 +223,11 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
val op = io.executeUnit.in.inst_info.op
val fusel = io.executeUnit.in.inst_info.fusel
val addr = io.executeUnit.in.inst_info.inst(31, 20)
val rdata = Wire(UInt(XLEN.W))
val src1 = io.executeUnit.in.src_info.src1_data
val csri = ZeroExtend(io.executeUnit.in.inst_info.inst(19, 15), XLEN)
val exe_stall = io.ctrl.exe_stall
val mem_stall = io.ctrl.mem_stall
val wdata = LookupTree(
wdata := LookupTree(
op,
List(
CSROpType.wrt -> src1,