fix(csr): 修复例外传递bug
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6728817004
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69f5974661
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@ -243,7 +243,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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// Fix Mip/Sip write
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val fixMapping = Map(
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MaskedRegMap(Mip, mipReg.asUInt, mipFixMask)
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// MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask) TODO
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// MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask) //TODO
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)
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val rdataDummy = Wire(UInt(XLEN.W))
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MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen && !illegal_access, wdata)
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@ -303,10 +303,11 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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ret_target := mepc(VADDR_WID - 1, 0)
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}
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io.decoderUnit.priv_mode := priv_mode
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io.executeUnit.out.ex := io.executeUnit.in.ex
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io.executeUnit.out.ex.exception(illegalInstr) := (illegal_addr || illegal_access) && wen
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io.executeUnit.out.rdata := rdata
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io.memoryUnit.out.flush := has_exc_int || ret
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io.memoryUnit.out.flush_pc := Mux(has_exc_int, trap_target, ret_target)
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io.decoderUnit.priv_mode := priv_mode
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io.executeUnit.out.ex := io.executeUnit.in.ex
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io.executeUnit.out.ex.exception(illegalInstr) :=
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(illegal_addr || illegal_access) && wen | io.executeUnit.in.ex.exception(illegalInstr)
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io.executeUnit.out.rdata := rdata
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io.memoryUnit.out.flush := has_exc_int || ret
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io.memoryUnit.out.flush_pc := Mux(has_exc_int, trap_target, ret_target)
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}
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@ -53,20 +53,26 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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val csr_sel1 = valid(1) && io.executeStage.inst1.inst_info.fusel === FuType.csr &&
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!(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR)
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io.csr.in.valid := (csr_sel0 || csr_sel1)
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io.csr.in.inst_info := Mux(
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csr_sel0 && !csr_sel1,
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io.executeStage.inst0.inst_info,
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io.executeStage.inst1.inst_info
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io.csr.in.inst_info := MuxCase(
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0.U.asTypeOf(new InstInfo()),
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Seq(
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csr_sel0 -> io.executeStage.inst0.inst_info,
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csr_sel1 -> io.executeStage.inst1.inst_info
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)
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)
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io.csr.in.src_info := Mux(
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csr_sel0 && !csr_sel1,
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io.executeStage.inst0.src_info,
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io.executeStage.inst1.src_info
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io.csr.in.src_info := MuxCase(
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0.U.asTypeOf(new SrcInfo()),
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Seq(
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csr_sel0 -> io.executeStage.inst0.src_info,
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csr_sel1 -> io.executeStage.inst1.src_info
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)
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)
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io.csr.in.ex := Mux(
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csr_sel0 && !csr_sel1,
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io.executeStage.inst0.ex,
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io.executeStage.inst1.ex
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io.csr.in.ex := MuxCase(
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0.U.asTypeOf(new ExceptionInfo()),
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Seq(
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csr_sel0 -> io.executeStage.inst0.ex,
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csr_sel1 -> io.executeStage.inst1.ex
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)
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)
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// input accessMemCtrl
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@ -130,10 +136,18 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
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io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
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io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
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io.memoryStage.inst0.ex := MuxLookup(io.executeStage.inst0.inst_info.fusel, fu.inst(0).ex.out)(
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Seq(
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FuType.lsu -> accessMemCtrl.inst(0).ex.out,
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FuType.csr -> io.csr.out.ex
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val has_ex0 =
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(io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR) && io.executeStage.inst0.inst_info.valid
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io.memoryStage.inst0.ex := Mux(
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has_ex0,
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io.executeStage.inst0.ex,
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MuxLookup(io.executeStage.inst0.inst_info.fusel, io.executeStage.inst0.ex)(
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Seq(
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FuType.alu -> fu.inst(0).ex.out,
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FuType.mdu -> fu.inst(0).ex.out,
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FuType.lsu -> accessMemCtrl.inst(0).ex.out,
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FuType.csr -> io.csr.out.ex
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)
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)
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)
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@ -144,10 +158,18 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
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io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
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io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
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io.memoryStage.inst1.ex := MuxLookup(io.executeStage.inst1.inst_info.fusel, fu.inst(1).ex.out)(
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Seq(
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FuType.lsu -> accessMemCtrl.inst(1).ex.out,
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FuType.csr -> io.csr.out.ex
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val has_ex1 =
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(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR) && io.executeStage.inst1.inst_info.valid
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io.memoryStage.inst1.ex := Mux(
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has_ex1,
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io.executeStage.inst1.ex,
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MuxLookup(io.executeStage.inst1.inst_info.fusel, io.executeStage.inst1.ex)(
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Seq(
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FuType.alu -> fu.inst(1).ex.out,
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FuType.mdu -> fu.inst(1).ex.out,
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FuType.lsu -> accessMemCtrl.inst(1).ex.out,
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FuType.csr -> io.csr.out.ex
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)
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)
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)
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