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feat(mem): 增加acc例外

This commit is contained in:
Liphen 2023-11-29 17:20:45 +08:00
parent b170d374ee
commit 1b3ce1e739
3 changed files with 38 additions and 37 deletions
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15
chisel/playground/src/Core.scala
View File

@ -119,13 +119,14 @@ class Core(implicit val config: CpuConfig) extends Module {
csr.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go
csr.ext_int := io.ext_int
memoryUnit.dataMemory.in.rdata := io.data.rdata
io.data.en := memoryUnit.dataMemory.out.en
io.data.size := memoryUnit.dataMemory.out.rlen
io.data.wen := memoryUnit.dataMemory.out.wen
io.data.wdata := memoryUnit.dataMemory.out.wdata
io.data.addr := memoryUnit.dataMemory.out.addr
io.data.wstrb := memoryUnit.dataMemory.out.wstrb
memoryUnit.dataMemory.in.rdata := io.data.rdata
memoryUnit.dataMemory.in.acc_err := io.data.acc_err
io.data.en := memoryUnit.dataMemory.out.en
io.data.size := memoryUnit.dataMemory.out.rlen
io.data.wen := memoryUnit.dataMemory.out.wen
io.data.wdata := memoryUnit.dataMemory.out.wdata
io.data.addr := memoryUnit.dataMemory.out.addr
io.data.wstrb := memoryUnit.dataMemory.out.wstrb
writeBackStage.memoryUnit <> memoryUnit.writeBackStage
writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go

33
chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
View File

@ -6,6 +6,21 @@ import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
class DataMemoryAccess_DataMemory extends Bundle {
val in = Input(new Bundle {
val acc_err = Bool()
val rdata = UInt(DATA_WID.W)
})
val out = Output(new Bundle {
val en = Bool()
val rlen = UInt(AXI_LEN_WID.W)
val wen = Bool()
val wstrb = UInt(AXI_STRB_WID.W)
val addr = UInt(AXI_ADDR_WID.W)
val wdata = UInt(AXI_DATA_WID.W)
})
}
class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
val io = IO(new Bundle {
val memoryUnit = new Bundle {
@ -18,23 +33,12 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
val ex = Vec(config.fuNum, new ExceptionInfo())
})
val out = Output(new Bundle {
val rdata = Output(UInt(DATA_WID.W))
val acc_err = Bool()
val rdata = Output(UInt(DATA_WID.W))
})
}
val dataMemory = new Bundle {
val in = Input(new Bundle {
val rdata = UInt(DATA_WID.W)
})
val out = Output(new Bundle {
val en = Bool()
val rlen = UInt(AXI_LEN_WID.W)
val wen = Bool()
val wstrb = UInt(AXI_STRB_WID.W)
val addr = UInt(AXI_ADDR_WID.W)
val wdata = UInt(AXI_DATA_WID.W)
})
}
val dataMemory = new DataMemoryAccess_DataMemory()
})
val mem_addr = io.memoryUnit.in.mem_addr
val mem_addr2 = mem_addr(1, 0)
@ -61,6 +65,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
"b111".U -> mem_rdata(63, 56)
)
)
io.memoryUnit.out.acc_err := io.dataMemory.in.acc_err
io.memoryUnit.out.rdata := MuxLookup(op, rdata(XLEN - 1, 0))(
List(
LSUOpType.lb -> SignedExtend(rdata(7, 0), XLEN),

27
chisel/playground/src/pipeline/memory/MemoryUnit.scala
View File

@ -20,19 +20,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
val decoderUnit = Output(Vec(config.fuNum, new RegWrite()))
val csr = Flipped(new CsrMemoryUnit())
val writeBackStage = Output(new MemoryUnitWriteBackUnit())
val dataMemory = new Bundle {
val in = Input(new Bundle {
val rdata = UInt(DATA_WID.W)
})
val out = Output(new Bundle {
val en = Bool()
val rlen = UInt(AXI_LEN_WID.W)
val wen = Bool()
val addr = UInt(AXI_ADDR_WID.W)
val wdata = UInt(AXI_DATA_WID.W)
val wstrb = UInt(AXI_STRB_WID.W)
})
}
val dataMemory = new DataMemoryAccess_DataMemory()
})
val dataMemoryAccess = Module(new DataMemoryAccess()).io
@ -43,6 +31,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
dataMemoryAccess.memoryUnit.in.mem_sel := io.memoryStage.inst0.mem.sel
dataMemoryAccess.memoryUnit.in.ex(0) := io.memoryStage.inst0.ex
dataMemoryAccess.memoryUnit.in.ex(1) := io.memoryStage.inst1.ex
dataMemoryAccess.dataMemory.in.acc_err := io.dataMemory.in.acc_err
dataMemoryAccess.dataMemory.in.rdata := io.dataMemory.in.rdata
io.dataMemory.out := dataMemoryAccess.dataMemory.out
@ -58,15 +47,21 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
io.writeBackStage.inst0.rd_info.wdata := io.memoryStage.inst0.rd_info.wdata
io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex
io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception
io.writeBackStage.inst0.commit := io.memoryStage.inst0.inst_info.valid
io.writeBackStage.inst0.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
LSUOpType.isLoad(io.memoryStage.inst0.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
io.writeBackStage.inst0.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
LSUOpType.isStore(io.memoryStage.inst0.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
io.writeBackStage.inst0.commit := io.memoryStage.inst0.inst_info.valid
io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info
io.writeBackStage.inst1.rd_info.wdata := io.memoryStage.inst1.rd_info.wdata
io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex
io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception
io.writeBackStage.inst1.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
LSUOpType.isLoad(io.memoryStage.inst1.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
io.writeBackStage.inst1.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
LSUOpType.isStore(io.memoryStage.inst1.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
io.writeBackStage.inst1.commit := io.memoryStage.inst1.inst_info.valid &&
!(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)