feat(mem): 增加acc例外
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b170d374ee
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1b3ce1e739
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@ -119,13 +119,14 @@ class Core(implicit val config: CpuConfig) extends Module {
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csr.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go
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csr.ext_int := io.ext_int
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memoryUnit.dataMemory.in.rdata := io.data.rdata
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io.data.en := memoryUnit.dataMemory.out.en
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io.data.size := memoryUnit.dataMemory.out.rlen
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io.data.wen := memoryUnit.dataMemory.out.wen
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io.data.wdata := memoryUnit.dataMemory.out.wdata
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io.data.addr := memoryUnit.dataMemory.out.addr
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io.data.wstrb := memoryUnit.dataMemory.out.wstrb
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memoryUnit.dataMemory.in.rdata := io.data.rdata
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memoryUnit.dataMemory.in.acc_err := io.data.acc_err
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io.data.en := memoryUnit.dataMemory.out.en
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io.data.size := memoryUnit.dataMemory.out.rlen
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io.data.wen := memoryUnit.dataMemory.out.wen
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io.data.wdata := memoryUnit.dataMemory.out.wdata
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io.data.addr := memoryUnit.dataMemory.out.addr
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io.data.wstrb := memoryUnit.dataMemory.out.wstrb
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writeBackStage.memoryUnit <> memoryUnit.writeBackStage
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writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go
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@ -6,6 +6,21 @@ import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class DataMemoryAccess_DataMemory extends Bundle {
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val in = Input(new Bundle {
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val acc_err = Bool()
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val rdata = UInt(DATA_WID.W)
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})
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val out = Output(new Bundle {
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val en = Bool()
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val rlen = UInt(AXI_LEN_WID.W)
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val wen = Bool()
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val wstrb = UInt(AXI_STRB_WID.W)
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val addr = UInt(AXI_ADDR_WID.W)
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val wdata = UInt(AXI_DATA_WID.W)
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})
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}
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class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val memoryUnit = new Bundle {
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@ -18,23 +33,12 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
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val ex = Vec(config.fuNum, new ExceptionInfo())
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})
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val out = Output(new Bundle {
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val rdata = Output(UInt(DATA_WID.W))
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val acc_err = Bool()
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val rdata = Output(UInt(DATA_WID.W))
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})
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}
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val dataMemory = new Bundle {
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val in = Input(new Bundle {
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val rdata = UInt(DATA_WID.W)
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})
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val out = Output(new Bundle {
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val en = Bool()
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val rlen = UInt(AXI_LEN_WID.W)
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val wen = Bool()
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val wstrb = UInt(AXI_STRB_WID.W)
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val addr = UInt(AXI_ADDR_WID.W)
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val wdata = UInt(AXI_DATA_WID.W)
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})
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}
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val dataMemory = new DataMemoryAccess_DataMemory()
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})
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val mem_addr = io.memoryUnit.in.mem_addr
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val mem_addr2 = mem_addr(1, 0)
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@ -61,6 +65,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
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"b111".U -> mem_rdata(63, 56)
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)
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)
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io.memoryUnit.out.acc_err := io.dataMemory.in.acc_err
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io.memoryUnit.out.rdata := MuxLookup(op, rdata(XLEN - 1, 0))(
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List(
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LSUOpType.lb -> SignedExtend(rdata(7, 0), XLEN),
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@ -20,19 +20,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
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val decoderUnit = Output(Vec(config.fuNum, new RegWrite()))
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val csr = Flipped(new CsrMemoryUnit())
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val writeBackStage = Output(new MemoryUnitWriteBackUnit())
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val dataMemory = new Bundle {
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val in = Input(new Bundle {
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val rdata = UInt(DATA_WID.W)
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})
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val out = Output(new Bundle {
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val en = Bool()
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val rlen = UInt(AXI_LEN_WID.W)
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val wen = Bool()
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val addr = UInt(AXI_ADDR_WID.W)
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val wdata = UInt(AXI_DATA_WID.W)
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val wstrb = UInt(AXI_STRB_WID.W)
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})
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}
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val dataMemory = new DataMemoryAccess_DataMemory()
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})
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val dataMemoryAccess = Module(new DataMemoryAccess()).io
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@ -43,6 +31,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
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dataMemoryAccess.memoryUnit.in.mem_sel := io.memoryStage.inst0.mem.sel
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dataMemoryAccess.memoryUnit.in.ex(0) := io.memoryStage.inst0.ex
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dataMemoryAccess.memoryUnit.in.ex(1) := io.memoryStage.inst1.ex
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dataMemoryAccess.dataMemory.in.acc_err := io.dataMemory.in.acc_err
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dataMemoryAccess.dataMemory.in.rdata := io.dataMemory.in.rdata
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io.dataMemory.out := dataMemoryAccess.dataMemory.out
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@ -58,15 +47,21 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
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io.writeBackStage.inst0.rd_info.wdata := io.memoryStage.inst0.rd_info.wdata
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io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
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io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex
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io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception
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io.writeBackStage.inst0.commit := io.memoryStage.inst0.inst_info.valid
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io.writeBackStage.inst0.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
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LSUOpType.isLoad(io.memoryStage.inst0.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
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io.writeBackStage.inst0.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(0) &&
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LSUOpType.isStore(io.memoryStage.inst0.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
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io.writeBackStage.inst0.commit := io.memoryStage.inst0.inst_info.valid
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io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
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io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info
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io.writeBackStage.inst1.rd_info.wdata := io.memoryStage.inst1.rd_info.wdata
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io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
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io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex
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io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception
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io.writeBackStage.inst1.ex.exception(loadAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
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LSUOpType.isLoad(io.memoryStage.inst1.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
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io.writeBackStage.inst1.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
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LSUOpType.isStore(io.memoryStage.inst1.inst_info.op) && dataMemoryAccess.memoryUnit.out.acc_err
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io.writeBackStage.inst1.commit := io.memoryStage.inst1.inst_info.valid &&
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!(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
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