Liphen
|
e1639e6f8b
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fix(tlb): 修复数据宽度问题
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2023-12-25 14:01:31 +08:00 |
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Liphen
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e646ee4a4c
|
docs(cache): 增加注释
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2023-12-24 16:21:53 +08:00 |
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Liphen
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c1cf6f8b7d
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perf(CacheConfig): 将所有的定义搬至config中
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2023-12-24 15:20:27 +08:00 |
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Liphen
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03ccee30f6
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style(icache): module使用小驼峰命名法
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2023-12-24 14:14:40 +08:00 |
|
Liphen
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881b1eca3c
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refactor: 删除PC_WID
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2023-12-24 14:13:05 +08:00 |
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Liphen
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82b0912046
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fix(icache): 修复lru、valid存在的问题
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2023-12-24 14:04:29 +08:00 |
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Liphen
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812a371571
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refactor(issue): 修改变量名方便看波形
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2023-12-24 13:33:08 +08:00 |
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Liphen
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a94958d7c9
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refactor: 调整变量名，删除fuNum
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2023-12-24 13:17:55 +08:00 |
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Liphen
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61f0692e2a
|
docs: 增加AXI文档
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2023-12-23 20:44:37 +08:00 |
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Liphen
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f67f96976a
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fix(icache): 配置成任意取指
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2023-12-23 13:44:45 +08:00 |
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Liphen
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442f51d5a4
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fix(icache): 修复之前icache遗留的问题
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2023-12-23 11:47:35 +08:00 |
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Liphen
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f4e0e1b5be
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refactor: nset改为nindex
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2023-12-22 18:12:56 +08:00 |
|
Liphen
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969237a09f
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fix: 修复dcache的size
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2023-12-22 17:57:19 +08:00 |
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Liphen
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faa9fca6b9
|
refactor(axi): 将常量移动到cache-axi中
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2023-12-22 14:56:31 +08:00 |
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Liphen
|
c0bdc5a097
|
refactor: 部分常量换成XLEN
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2023-12-22 14:28:13 +08:00 |
|
Liphen
|
76c0f446da
|
feat: 增加dcache
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2023-12-22 14:18:32 +08:00 |
|
Liphen
|
9001ab435c
|
修改commit信号
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2023-12-21 16:33:20 +08:00 |
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Liphen
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8a9b71ab4c
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Merge branch 'cache' into icache
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2023-12-21 15:38:16 +08:00 |
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Liphen
|
9d597adfa1
|
refactor(csr): mem改为单输入
|
2023-12-21 15:38:02 +08:00 |
|
Liphen
|
301199c756
|
feat: 添加icache成功生成Verilog
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2023-12-21 15:24:57 +08:00 |
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Liphen
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f13b9f009f
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refactor(const): 删除无用信号
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2023-12-19 15:47:11 +08:00 |
|
Liphen
|
3134b79c54
|
增加puamips的cache文件
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2023-12-19 15:08:24 +08:00 |
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Liphen
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41da1f4c3e
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refactor: 修改info内信号名
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2023-12-19 14:47:40 +08:00 |
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Liphen
|
90efc32bca
|
feat(csr): 修改misa的ext段
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2023-12-18 16:59:25 +08:00 |
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Liphen
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534e608337
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feat: 修改PC初值
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2023-12-18 15:26:45 +08:00 |
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Liphen
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ef9db0c29d
|
feat: 下一步添加cache
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2023-12-13 19:54:44 +08:00 |
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Liphen
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6f065a9c67
|
perf: 缩减op信号，增加bru
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2023-12-13 19:40:01 +08:00 |
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Liphen
|
908fd0a377
|
增加mmio
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2023-12-13 17:59:38 +08:00 |
|
Liphen
|
6bd22ee617
|
refactor(issue): 美化代码
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2023-12-13 16:31:36 +08:00 |
|
Liphen
|
5860aa9fa1
|
Add count target to Makefile
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2023-12-13 14:19:53 +08:00 |
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Liphen
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0fdfec4323
|
refactor(mdu): 删除无用代码
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2023-12-13 14:19:34 +08:00 |
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Liphen
|
5101abc727
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refactor: 删去无用信号
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2023-12-13 13:00:35 +08:00 |
|
Liphen
|
6678952dde
|
Remove unused code and update variable assignment in Core and Ctrl classes
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2023-12-11 15:20:40 +08:00 |
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Liphen
|
cface2454d
|
Remove unused variables in Core and Csr classes
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2023-12-11 15:08:56 +08:00 |
|
Liphen
|
7df36c2c38
|
refactor: 美化代码
|
2023-12-11 15:04:58 +08:00 |
|
Liphen
|
de26a56cc2
|
feat(csr): 增加tvec模式功能
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2023-12-11 11:23:46 +08:00 |
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Liphen
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711e375959
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Add Signal.md to playground/doc directory
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2023-12-10 22:33:46 +08:00 |
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Liphen
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452b8ad995
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删除mem_wreg
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2023-12-10 22:23:22 +08:00 |
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Liphen
|
5fa965062f
|
Refactor DecoderUnit and Csr classes
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2023-12-10 22:02:16 +08:00 |
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Liphen
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2ff3d1c000
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fix: mem有例外时，exe不应当读写csr
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2023-12-09 17:53:56 +08:00 |
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Liphen
|
86add2c2c8
|
将mou搬到mem级
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2023-12-09 17:48:49 +08:00 |
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Liphen
|
2a16d26278
|
feat: 通过所有测试用例
|
2023-12-07 21:14:40 +08:00 |
|
Liphen
|
87fc0f60ee
|
fix(issue): 修复双发时inst1不能为跳转
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2023-12-07 17:42:11 +08:00 |
|
Liphen
|
44ac8853b8
|
fix: 修复访存ready信号
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2023-12-07 17:41:47 +08:00 |
|
Liphen
|
9524ee9919
|
fix(dcache): 解决写请求发生了两次的问题
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2023-12-07 17:04:04 +08:00 |
|
Liphen
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ff56c013ef
|
fix(mem): addr错误
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2023-12-07 16:42:18 +08:00 |
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Liphen
|
f6412b0e8c
|
fix(mem): 修复access
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2023-12-07 16:23:42 +08:00 |
|
Liphen
|
f7ee8c4c87
|
成功生成verilog
|
2023-12-07 16:08:45 +08:00 |
|
Liphen
|
6f02672358
|
refactor: 将访存全部重构一下
|
2023-12-07 15:02:22 +08:00 |
|
Liphen
|
681162954f
|
Fix register write-after-read and load stall
issues in Issue.scala
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2023-12-06 15:14:51 +08:00 |