Refactor DecoderUnit and Csr classes
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Liphen
parent
2ff3d1c000
commit
5fa965062f
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@ -58,10 +58,10 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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val forwardCtrl = Module(new ForwardCtrl()).io
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val issue = Module(new Issue()).io
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val pc = io.instFifo.inst.map(_.pc)
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val inst = io.instFifo.inst.map(_.inst)
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val info = decoder.map(_.io.out.info)
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val priv_mode = io.csr.priv_mode
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val pc = io.instFifo.inst.map(_.pc)
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val inst = io.instFifo.inst.map(_.inst)
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val info = decoder.map(_.io.out.info)
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val mode = io.csr.mode
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issue.allow_to_go := io.ctrl.allow_to_go
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issue.instFifo := io.instFifo.info
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@ -127,11 +127,11 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak &&
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info(0).op === CSROpType.jmp && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && priv_mode === ModeM && info(0).fusel === FuType.csr
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info(0).op === CSROpType.jmp && mode === ModeM && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallS) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && priv_mode === ModeS && info(0).fusel === FuType.csr
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info(0).op === CSROpType.jmp && mode === ModeS && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && priv_mode === ModeU && info(0).fusel === FuType.csr
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info(0).op === CSROpType.jmp && mode === ModeU && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.tval := MuxCase(
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0.U,
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Seq(
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@ -170,11 +170,11 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak &&
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info(1).op === CSROpType.jmp && info(0).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && priv_mode === ModeM && info(1).fusel === FuType.csr
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info(1).op === CSROpType.jmp && mode === ModeM && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && priv_mode === ModeS && info(1).fusel === FuType.csr
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info(1).op === CSROpType.jmp && mode === ModeS && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallU) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && priv_mode === ModeU && info(1).fusel === FuType.csr
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info(1).op === CSROpType.jmp && mode === ModeU && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.tval := MuxCase(
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0.U,
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@ -44,7 +44,7 @@ class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
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}
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class CsrDecoderUnit extends Bundle {
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val priv_mode = Output(Priv())
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val mode = Output(Priv())
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val interrupt = Output(UInt(INT_WID.W))
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}
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@ -211,7 +211,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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MaskedRegMap(Tdata1, tdata1, 0.U, MaskedRegMap.Unwritable)
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) //++ perfCntsLoMapping
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val priv_mode = RegInit(Priv.m) // 当前特权模式
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val mode = RegInit(Priv.m) // 当前特权模式
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// interrupts
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val mtip = io.ext_int.ti
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@ -226,7 +226,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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val interrupt_enable = Wire(UInt(INT_WID.W)) // 不用考虑ideleg
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interrupt_enable := Fill(
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INT_WID,
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(((priv_mode === ModeM) && mstatus.asTypeOf(new Mstatus()).ie.m) || (priv_mode < ModeM))
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(((mode === ModeM) && mstatus.asTypeOf(new Mstatus()).ie.m) || (mode < ModeM))
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)
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io.decoderUnit.interrupt := mie(11, 0) & mip_has_interrupt.asUInt & interrupt_enable.asUInt
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@ -266,13 +266,14 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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)
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val satp_legal = (wdata.asTypeOf(new Satp()).mode === 0.U) || (wdata.asTypeOf(new Satp()).mode === 8.U)
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val wen = (valid && op =/= CSROpType.jmp) && (addr =/= Satp.U || satp_legal)
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val write = (valid && op =/= CSROpType.jmp) && (addr =/= Satp.U || satp_legal)
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val only_read = VecInit(CSROpType.set, CSROpType.seti, CSROpType.clr, CSROpType.clri).contains(op) && src1 === 0.U
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val illegal_mode = priv_mode < addr(9, 8)
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val illegal_write = wen && (addr(11, 10) === "b11".U) && !only_read
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val illegal_mode = mode < addr(9, 8)
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val illegal_write = write && (addr(11, 10) === "b11".U) && !only_read
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val illegal_access = illegal_mode || illegal_write
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val wen = write && !illegal_access
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MaskedRegMap.generate(mapping, addr, rdata, wen && !illegal_access, wdata)
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MaskedRegMap.generate(mapping, addr, rdata, wen, wdata)
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val illegal_addr = MaskedRegMap.isIllegalAddr(mapping, addr)
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// Fix Mip/Sip write
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val fixMapping = Map(
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@ -280,7 +281,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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// MaskedRegMap(Sip, mipReg.asUInt, sipMask, MaskedRegMap.NoSideEffect, sipMask) //TODO
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)
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val rdataDummy = Wire(UInt(XLEN.W))
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MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen && !illegal_access, wdata)
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MaskedRegMap.generate(fixMapping, addr, rdataDummy, wen, wdata)
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// CSR inst decode
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val ret = Wire(Bool())
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@ -327,10 +328,10 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
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mcause := causeNO
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mepc := SignedExtend(mem_pc, XLEN)
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mstatusNew.mpp := priv_mode
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mstatusNew.mpp := mode
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mstatusNew.pie.m := mstatusOld.ie.m
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mstatusNew.ie.m := false.B
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priv_mode := ModeM
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mode := ModeM
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when(tval_wen) { mtval := 0.U }
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mstatus := mstatusNew.asUInt
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}
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@ -345,7 +346,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
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// mstatusNew.mpp.m := ModeU //TODO: add mode U
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mstatusNew.ie.m := mstatusOld.pie.m
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priv_mode := mstatusOld.mpp
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mode := mstatusOld.mpp
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mstatusNew.pie.m := true.B
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mstatusNew.mpp := ModeU
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mstatus := mstatusNew.asUInt
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@ -353,10 +354,10 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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ret_target := mepc(VADDR_WID - 1, 0)
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}
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io.decoderUnit.priv_mode := priv_mode
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io.executeUnit.out.ex := io.executeUnit.in.ex
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io.decoderUnit.mode := mode
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io.executeUnit.out.ex := io.executeUnit.in.ex
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io.executeUnit.out.ex.exception(illegalInstr) :=
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(illegal_addr || illegal_access) && wen | io.executeUnit.in.ex.exception(illegalInstr)
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(illegal_addr || illegal_access) && write | io.executeUnit.in.ex.exception(illegalInstr)
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io.executeUnit.out.rdata := rdata
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io.memoryUnit.out.flush := has_exc_int || ret
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io.memoryUnit.out.flush_pc := Mux(has_exc_int, trap_target, ret_target)
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