refactor: 将访存全部重构一下
This commit is contained in:
Liphen
parent
681162954f
commit
6f02672358
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@ -103,6 +103,23 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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val rdata = Wire(UInt(XLEN.W))
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val wdata = Wire(UInt(XLEN.W))
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// Atom LR/SC Control Bits
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val setLr = WireInit(Bool(), false.B)
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val setLrVal = WireInit(Bool(), false.B)
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val setLrAddr = WireInit(UInt(XLEN.W), DontCare) //TODO : need check
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val lr = RegInit(Bool(), false.B)
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val lrAddr = RegInit(UInt(XLEN.W), 0.U)
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BoringUtils.addSink(setLr, "set_lr")
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BoringUtils.addSink(setLrVal, "set_lr_val")
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BoringUtils.addSink(setLrAddr, "set_lr_addr")
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BoringUtils.addSource(lr, "lr")
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BoringUtils.addSource(lrAddr, "lr_addr")
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when(setLr) {
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lr := setLrVal
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lrAddr := setLrAddr
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}
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// Side Effect
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def mstatusUpdateSideEffect(mstatus: UInt): UInt = {
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val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
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@ -325,8 +342,8 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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mstatusNew.pie.m := true.B
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mstatusNew.mpp := ModeU
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mstatus := mstatusNew.asUInt
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// lr := false.B //TODO: add原子操作
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ret_target := mepc(VADDR_WID - 1, 0)
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lr := false.B
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ret_target := mepc(VADDR_WID - 1, 0)
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}
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io.decoderUnit.priv_mode := priv_mode
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@ -1,92 +0,0 @@
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package cpu.pipeline.execute
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import chisel3._
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import chisel3.util._
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import cpu.CpuConfig
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import cpu.defines._
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import cpu.defines.Const._
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class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val mem = new Bundle {
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val out = Output(new Bundle {
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val en = Bool()
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val ren = Bool()
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val wen = Bool()
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val info = new InstInfo()
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val addr = UInt(DATA_ADDR_WID.W)
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val wdata = UInt(DATA_WID.W)
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})
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}
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val inst = Vec(
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config.fuNum,
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new Bundle {
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val info = Input(new InstInfo())
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val src_info = Input(new SrcInfo())
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val ex = new Bundle {
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val in = Input(new ExceptionInfo())
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val out = Output(new ExceptionInfo())
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}
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val mem_sel = Output(Bool())
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}
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)
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})
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io.mem.out.en := io.inst.map(_.mem_sel).reduce(_ || _)
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io.mem.out.ren := io.inst(0).mem_sel && LSUOpType.isLoad(io.inst(0).info.op) ||
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io.inst(1).mem_sel && LSUOpType.isLoad(io.inst(1).info.op)
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io.mem.out.wen := io.inst(0).mem_sel && LSUOpType.isStore(io.inst(0).info.op) ||
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io.inst(1).mem_sel && LSUOpType.isStore(io.inst(1).info.op)
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io.mem.out.info := Mux1H(
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Seq(
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(io.inst(0).info.fusel === FuType.lsu) -> io.inst(0).info,
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(io.inst(1).info.fusel === FuType.lsu) -> io.inst(1).info
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)
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)
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val mem_addr = Wire(Vec(config.fuNum, UInt(DATA_ADDR_WID.W)))
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mem_addr(0) := io.inst(0).src_info.src1_data + io.inst(0).info.imm
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mem_addr(1) := io.inst(1).src_info.src1_data + io.inst(1).info.imm
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io.mem.out.addr := Mux1H(
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Seq(
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(io.inst(0).info.fusel === FuType.lsu) -> mem_addr(0),
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(io.inst(1).info.fusel === FuType.lsu) -> mem_addr(1)
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)
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)
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io.mem.out.wdata := Mux1H(
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Seq(
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(io.inst(0).info.fusel === FuType.lsu) ->
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io.inst(0).src_info.src2_data,
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(io.inst(1).info.fusel === FuType.lsu) ->
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io.inst(1).src_info.src2_data
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)
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)
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val addr_aligned = Wire(Vec(config.fuNum, Bool()))
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for (i <- 0 until config.fuNum) {
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addr_aligned(i) := LookupTree(
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io.inst(i).info.op(1, 0),
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List(
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"b00".U -> true.B, //b
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"b01".U -> (mem_addr(i)(0) === 0.U), //h
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"b10".U -> (mem_addr(i)(1, 0) === 0.U), //w
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"b11".U -> (mem_addr(i)(2, 0) === 0.U) //d
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)
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)
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}
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for (i <- 0 until config.fuNum) {
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val store_inst = LSUOpType.isStore(io.inst(i).info.op)
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io.inst(i).ex.out := io.inst(i).ex.in
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io.inst(i).ex.out.exception(loadAddrMisaligned) := !store_inst && !addr_aligned(i)
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io.inst(i).ex.out.exception(storeAddrMisaligned) := store_inst && !addr_aligned(i)
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io.inst(i).ex.out.tval := Mux(
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io.inst(i).ex.in.exception.asUInt.orR,
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io.inst(i).ex.in.tval,
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mem_addr(i)
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)
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}
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io.inst(0).mem_sel := (io.inst(0).info.fusel === FuType.lsu) &&
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!(HasExcInt(io.inst(0).ex.out)) && io.inst(0).info.valid
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io.inst(1).mem_sel := (io.inst(1).info.fusel === FuType.lsu) &&
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!(HasExcInt(io.inst(0).ex.out)) && !(HasExcInt(io.inst(1).ex.out)) && io.inst(1).info.valid
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}
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@ -33,8 +33,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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val memoryStage = Output(new ExecuteUnitMemoryUnit())
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})
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val fu = Module(new Fu()).io
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val accessMemCtrl = Module(new ExeAccessMemCtrl()).io
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val fu = Module(new Fu()).io
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val valid = VecInit(
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io.executeStage.inst0.info.valid && io.ctrl.allow_to_go,
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@ -88,13 +87,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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fusel(1) === FuType.lsu && valid(1) &&
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!(HasExcInt(io.executeStage.inst1.ex))
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)
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// input accessMemCtrl
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accessMemCtrl.inst(0).info := Mux(is_lsu(0), io.executeStage.inst0.info, 0.U.asTypeOf(new InstInfo()))
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accessMemCtrl.inst(0).src_info := Mux(is_lsu(0), io.executeStage.inst0.src_info, 0.U.asTypeOf(new SrcInfo()))
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accessMemCtrl.inst(0).ex.in := Mux(is_lsu(0), io.executeStage.inst0.ex, 0.U.asTypeOf(new ExceptionInfo()))
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accessMemCtrl.inst(1).info := Mux(is_lsu(1), io.executeStage.inst1.info, 0.U.asTypeOf(new InstInfo()))
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accessMemCtrl.inst(1).src_info := Mux(is_lsu(1), io.executeStage.inst1.src_info, 0.U.asTypeOf(new SrcInfo()))
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accessMemCtrl.inst(1).ex.in := Mux(is_lsu(1), io.executeStage.inst1.ex, 0.U.asTypeOf(new ExceptionInfo()))
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// input fu
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fu.ctrl <> io.ctrl.fu
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@ -119,14 +111,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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io.ctrl.fu_stall := fu.stall_req
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io.memoryStage.inst0.mem.en := accessMemCtrl.mem.out.en
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io.memoryStage.inst0.mem.ren := accessMemCtrl.mem.out.ren
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io.memoryStage.inst0.mem.wen := accessMemCtrl.mem.out.wen
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io.memoryStage.inst0.mem.addr := accessMemCtrl.mem.out.addr
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io.memoryStage.inst0.mem.wdata := accessMemCtrl.mem.out.wdata
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io.memoryStage.inst0.mem.sel := accessMemCtrl.inst.map(_.mem_sel)
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io.memoryStage.inst0.mem.info := accessMemCtrl.mem.out.info
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io.memoryStage.inst0.pc := io.executeStage.inst0.pc
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io.memoryStage.inst0.info := io.executeStage.inst0.info
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io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
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@ -141,7 +125,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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io.executeStage.inst0.ex,
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MuxLookup(io.executeStage.inst0.info.fusel, io.executeStage.inst0.ex)(
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Seq(
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FuType.lsu -> accessMemCtrl.inst(0).ex.out,
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FuType.csr -> io.csr.out.ex
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)
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)
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@ -166,7 +149,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
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io.executeStage.inst1.ex,
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MuxLookup(io.executeStage.inst1.info.fusel, io.executeStage.inst1.ex)(
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Seq(
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FuType.lsu -> accessMemCtrl.inst(1).ex.out,
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FuType.csr -> io.csr.out.ex
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)
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)
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@ -0,0 +1,48 @@
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package cpu.pipeline.memory
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class AtomAlu extends Module {
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val io = IO(new Bundle {
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val in = Input(new Bundle {
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val rdata = Input(UInt(XLEN.W)) // load data
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val wdata = Input(UInt(XLEN.W)) // reg data
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val info = new InstInfo()
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})
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val out = Output(new Bundle {
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val result = Output(UInt(XLEN.W))
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})
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})
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val src1 = io.in.rdata
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val src2 = io.in.wdata
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val op = io.in.info.op
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val is_sub = !LSUOpType.isAdd(op)
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val sum = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub
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val oxr = src1 ^ src2
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val sltu = !sum(XLEN)
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val slt = oxr(XLEN - 1) ^ sltu
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val is_word = !io.in.info.inst(12)
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val res = LookupTreeDefault(
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op(5, 0),
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sum,
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List(
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LSUOpType.amoswap -> src2,
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LSUOpType.amoadd -> sum,
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LSUOpType.amoxor -> oxr,
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LSUOpType.amoand -> (src1 & src2),
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LSUOpType.amoor -> (src1 | src2),
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LSUOpType.amomin -> Mux(slt(0), src1, src2),
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LSUOpType.amomax -> Mux(slt(0), src2, src1),
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LSUOpType.amominu -> Mux(sltu(0), src1, src2),
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LSUOpType.amomaxu -> Mux(sltu(0), src2, src1)
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)
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)
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io.out.result := Mux(is_word, SignedExtend(res(31, 0), 64), res(XLEN - 1, 0))
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}
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@ -0,0 +1,140 @@
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package cpu.pipeline.memory
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class LSExe extends Module {
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val io = IO(new Bundle {
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val dataMemory = new DataMemoryAccess_DataMemory()
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val in = Input(new Bundle {
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val mem_en = Bool()
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val mem_addr = UInt(DATA_ADDR_WID.W)
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val wdata = UInt(DATA_WID.W)
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val info = new InstInfo()
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})
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val out = Output(new Bundle {
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val loadAddrMisaligned = Bool()
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val storeAddrMisaligned = Bool()
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val rdata = UInt(DATA_WID.W)
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})
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})
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def genWmask(addr: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> 0x1.U, //0001 << addr(2:0)
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"b01".U -> 0x3.U, //0011
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"b10".U -> 0xf.U, //1111
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"b11".U -> 0xff.U //11111111
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)
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) << addr(2, 0)
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}
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def genWdata(data: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> Fill(8, data(7, 0)),
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"b01".U -> Fill(4, data(15, 0)),
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"b10".U -> Fill(2, data(31, 0)),
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"b11".U -> data
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)
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)
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}
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def genWmask32(addr: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> 0x1.U, //0001 << addr(1:0)
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"b01".U -> 0x3.U, //0011
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"b10".U -> 0xf.U //1111
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)
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) << addr(1, 0)
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}
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def genWdata32(data: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> Fill(4, data(7, 0)),
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"b01".U -> Fill(2, data(15, 0)),
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"b10".U -> data
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)
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)
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}
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val valid = io.in.mem_en
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val addr = io.in.mem_addr
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val addrLatch = RegNext(addr)
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val op = io.in.info.op
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val isStore = valid && LSUOpType.isStore(op)
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val partialLoad = !isStore && (op =/= LSUOpType.ld)
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val size = op(1, 0)
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val reqAddr = if (XLEN == 32) SignedExtend(addr, VADDR_WID) else addr(VADDR_WID - 1, 0)
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val reqWdata = if (XLEN == 32) genWdata32(io.in.wdata, size) else genWdata(io.in.wdata, size)
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val reqWmask = if (XLEN == 32) genWmask32(addr, size) else genWmask(addr, size)
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io.dataMemory.out.en := valid && !io.out.storeAddrMisaligned && !io.out.loadAddrMisaligned
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io.dataMemory.out.rlen := size
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io.dataMemory.out.wen := isStore
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io.dataMemory.out.wstrb := reqWmask
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io.dataMemory.out.addr := reqAddr
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io.dataMemory.out.wdata := reqWdata
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val rdata = io.dataMemory.in.rdata
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val acc_err = io.dataMemory.in.acc_err
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val rdataSel64 = LookupTree(
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addrLatch(2, 0),
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List(
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"b000".U -> rdata(63, 0),
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"b001".U -> rdata(63, 8),
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"b010".U -> rdata(63, 16),
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"b011".U -> rdata(63, 24),
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"b100".U -> rdata(63, 32),
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"b101".U -> rdata(63, 40),
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"b110".U -> rdata(63, 48),
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"b111".U -> rdata(63, 56)
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)
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)
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val rdataSel32 = LookupTree(
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addrLatch(1, 0),
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List(
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"b00".U -> rdata(31, 0),
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"b01".U -> rdata(31, 8),
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"b10".U -> rdata(31, 16),
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"b11".U -> rdata(31, 24)
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)
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)
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val rdataSel = if (XLEN == 32) rdataSel32 else rdataSel64
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val rdataPartialLoad = LookupTree(
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op,
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List(
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LSUOpType.lb -> SignedExtend(rdataSel(7, 0), XLEN),
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LSUOpType.lh -> SignedExtend(rdataSel(15, 0), XLEN),
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LSUOpType.lw -> SignedExtend(rdataSel(31, 0), XLEN),
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LSUOpType.lbu -> ZeroExtend(rdataSel(7, 0), XLEN),
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LSUOpType.lhu -> ZeroExtend(rdataSel(15, 0), XLEN),
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LSUOpType.lwu -> ZeroExtend(rdataSel(31, 0), XLEN)
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)
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)
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val addrAligned = LookupTree(
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op(1, 0),
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List(
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"b00".U -> true.B, //b
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"b01".U -> (addr(0) === 0.U), //h
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"b10".U -> (addr(1, 0) === 0.U), //w
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"b11".U -> (addr(2, 0) === 0.U) //d
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)
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)
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val is_amo = valid && LSUOpType.isAMO(op)
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io.out.rdata := Mux(partialLoad, rdataPartialLoad, rdataSel)
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io.out.loadAddrMisaligned := valid && !isStore && !is_amo && !addrAligned
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io.out.storeAddrMisaligned := valid && (isStore || is_amo) && !addrAligned
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}
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@ -6,29 +6,17 @@ import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class ExeMemInst1 extends Bundle {
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val pc = UInt(PC_WID.W)
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val info = new InstInfo()
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val rd_info = new RdInfo()
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val ex = new ExceptionInfo()
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}
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class ExeMemInst0(implicit val config: CpuConfig) extends ExeMemInst1 {
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val mem = new Bundle {
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val en = Bool()
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val ren = Bool()
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val wen = Bool()
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val info = new InstInfo()
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val addr = UInt(DATA_ADDR_WID.W)
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val wdata = UInt(DATA_WID.W)
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val sel = Vec(config.fuNum, Bool())
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}
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class ExeMemInst extends Bundle {
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val pc = UInt(PC_WID.W)
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val info = new InstInfo()
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val rd_info = new RdInfo()
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val src_info = new SrcInfo()
|
||||
val ex = new ExceptionInfo()
|
||||
}
|
||||
|
||||
class ExecuteUnitMemoryUnit(implicit val config: CpuConfig) extends Bundle {
|
||||
|
||||
val inst0 = new ExeMemInst0()
|
||||
val inst1 = new ExeMemInst1()
|
||||
val inst0 = new ExeMemInst()
|
||||
val inst1 = new ExeMemInst()
|
||||
}
|
||||
|
||||
class MemoryStage(implicit val config: CpuConfig) extends Module {
|
||||
|
|
@ -40,12 +28,12 @@ class MemoryStage(implicit val config: CpuConfig) extends Module {
|
|||
val executeUnit = Input(new ExecuteUnitMemoryUnit())
|
||||
val memoryUnit = Output(new ExecuteUnitMemoryUnit())
|
||||
})
|
||||
val inst0 = RegInit(0.U.asTypeOf(new ExeMemInst0()))
|
||||
val inst1 = RegInit(0.U.asTypeOf(new ExeMemInst1()))
|
||||
val inst0 = RegInit(0.U.asTypeOf(new ExeMemInst()))
|
||||
val inst1 = RegInit(0.U.asTypeOf(new ExeMemInst()))
|
||||
|
||||
when(io.ctrl.clear) {
|
||||
inst0 := 0.U.asTypeOf(new ExeMemInst0())
|
||||
inst1 := 0.U.asTypeOf(new ExeMemInst1())
|
||||
inst0 := 0.U.asTypeOf(new ExeMemInst())
|
||||
inst1 := 0.U.asTypeOf(new ExeMemInst())
|
||||
}.elsewhen(io.ctrl.allow_to_go) {
|
||||
inst0 := io.executeUnit.inst0
|
||||
inst1 := io.executeUnit.inst1
|
||||
|
|
|
|||
|
|
@ -2,10 +2,12 @@ import cpu._
|
|||
import circt.stage._
|
||||
|
||||
import cpu.pipeline.execute.Csr
|
||||
import cpu.pipeline.memory.LSExe
|
||||
import cpu.pipeline.memory.AtomAlu
|
||||
|
||||
object TestMain extends App {
|
||||
implicit val config = new CpuConfig()
|
||||
def top = new Csr()
|
||||
def top = new AtomAlu()
|
||||
val useMFC = false // use MLIR-based firrtl compiler
|
||||
val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
|
||||
if (useMFC) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue