yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix register write-after-read and load stall 

issues in Issue.scala
This commit is contained in:
Liphen 2023-12-06 15:14:51 +08:00
parent ecbaa40d88
commit 681162954f
1 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
chisel/playground/src/pipeline/decoder/Issue.scala
View File

@ -39,12 +39,16 @@ class Issue(implicit val config: CpuConfig) extends Module {
// 写后读冲突
val load_stall =
io.execute(0).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr ||
inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) ||
io.execute(1).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr ||
inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr)
io.execute(0).mem_wreg && io.execute(0).reg_waddr.orR &&
(inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr ||
inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) ||
io.execute(1).mem_wreg && io.execute(1).reg_waddr.orR &&
(inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr ||
inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr)
val raw_reg =
inst0.reg_wen && (inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren || inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren)
inst0.reg_wen && inst0.reg_waddr.orR &&
(inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren ||
inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren)
val data_conflict = raw_reg || load_stall
// 指令0为bru指令