From 681162954f84eb063aaa552b6ce8f3e189efed59 Mon Sep 17 00:00:00 2001 From: Liphen Date: Wed, 6 Dec 2023 15:14:51 +0800 Subject: [PATCH] Fix register write-after-read and load stall issues in Issue.scala --- chisel/playground/src/pipeline/decoder/Issue.scala | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/chisel/playground/src/pipeline/decoder/Issue.scala b/chisel/playground/src/pipeline/decoder/Issue.scala index 966bb52..1002c2f 100644 --- a/chisel/playground/src/pipeline/decoder/Issue.scala +++ b/chisel/playground/src/pipeline/decoder/Issue.scala @@ -39,12 +39,16 @@ class Issue(implicit val config: CpuConfig) extends Module { // 写后读冲突 val load_stall = - io.execute(0).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr || - inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) || - io.execute(1).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr || - inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr) + io.execute(0).mem_wreg && io.execute(0).reg_waddr.orR && + (inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr || + inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) || + io.execute(1).mem_wreg && io.execute(1).reg_waddr.orR && + (inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr || + inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr) val raw_reg = - inst0.reg_wen && (inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren || inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren) + inst0.reg_wen && inst0.reg_waddr.orR && + (inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren || + inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren) val data_conflict = raw_reg || load_stall // 指令0为bru指令