fix(icache): 修复lru、valid存在的问题
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Liphen
parent
812a371571
commit
82b0912046
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@ -28,7 +28,7 @@ case class BranchPredictorConfig(
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val phtDepth: Int = 6)
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case class CacheConfig(
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nway: Int = 2, // 路数
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nway: Int = 2, // 路数，目前只支持2路
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nbank: Int, // 每个项目中的bank数
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nindex: Int, // 每路的项目数
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bytesPerBank: Int // 每个bank中的字节数
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@ -14,10 +14,12 @@ class Cache(implicit config: CpuConfig) extends Module {
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val axi = new AXI()
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})
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// 每个 bank 存 2 条 32 bit 指令
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implicit val iCacheConfig =
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CacheConfig(nindex = 64, nbank = 4, bytesPerBank = (INST_WID / 8) * config.instFetchNum) // 每个 bank 存 2 条 32 bit 指令
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CacheConfig(nindex = 64, nbank = 4, bytesPerBank = (INST_WID / 8) * config.instFetchNum)
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// 每个 bank 存 1 条 XLEN bit 数据
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implicit val dCacheConfig =
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CacheConfig(nindex = 128, nbank = 8, bytesPerBank = XLEN / 8) // 每个 bank 存 1 条 XLEN bit 数据
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CacheConfig(nindex = 128, nbank = 8, bytesPerBank = XLEN / 8)
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val icache = Module(new ICache(iCacheConfig))
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val dcache = Module(new DCache(dCacheConfig))
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@ -53,14 +53,15 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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// * 128 bit for 4 inst * //
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// =========================================================
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// | valid | tag | bank 0 | bank 1 | bank 2 | bank 3 |
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// | 1111 | 20 | 128 | 128 | 128 | 128 |
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// | 1 | 20 | 128 | 128 | 128 | 128 |
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// =========================================================
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// | bank |
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// | inst 0 | inst 1 | inst 2 | inst 3 |
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// | 32 | 32 | 32 | 32 |
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// =====================================
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val valid = RegInit(VecInit(Seq.fill(nindex)(VecInit(Seq.fill(nbank)(false.B)))))
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// nway 路，每路 nindex 行，每行 nbank 个 bank，每行的nbank共用一个valid
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val valid = RegInit(VecInit(Seq.fill(nway)(VecInit(Seq.fill(nindex)(false.B)))))
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// * should choose next addr * //
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val should_next_addr = (state === s_idle && !tlb_fill) || (state === s_save)
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@ -74,9 +75,6 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B)))
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val tag_wdata = RegInit(0.U(tagWidth.W))
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// * lru * //
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val lru = RegInit(VecInit(Seq.fill(nindex * nbank)(false.B))) // TODO:检查lru的正确性
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// * itlb * //
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when(tlb_fill) { tlb_fill := false.B }
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io.cpu.tlb.fill := tlb_fill
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@ -88,6 +86,14 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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valid := 0.U.asTypeOf(valid)
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}
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// * virtual index * //
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val virtual_index = io.cpu.addr(0)(indexWidth + offsetWidth - 1, offsetWidth)
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// * lru * //// TODO:检查lru的正确性，增加可拓展性，目前只支持两路的cache
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val lru = RegInit(VecInit(Seq.fill(nindex)(false.B)))
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// 需要替换的路号
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val replace_way = lru(virtual_index)
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// * replace index * //
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val replace_index = RegInit(0.U(indexWidth.W))
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// 用于控制写入一行cache条目中的哪个bank, 一个bank可能有多次写入
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@ -95,21 +101,18 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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VecInit(Seq.fill(nway)(VecInit(Seq.fill(nbank)(VecInit(Seq.fill(instBlocksPerBank)((false.B)))))))
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)
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// * virtual index * //
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val virtual_index = io.cpu.addr(0)(indexWidth + offsetWidth - 1, offsetWidth)
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// * cache hit * //
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val tag_compare_valid = VecInit(Seq.tabulate(nway)(i => tag(i) === io.cpu.tlb.tag && valid(virtual_index)(i)))
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val tag_compare_valid = VecInit(Seq.tabulate(nway)(i => tag(i) === io.cpu.tlb.tag && valid(i)(virtual_index)))
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val cache_hit = tag_compare_valid.contains(true.B)
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val cache_hit_available = cache_hit && io.cpu.tlb.translation_ok && !io.cpu.tlb.uncached
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val sel = tag_compare_valid(1)
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val select_way = tag_compare_valid(1) // 1路命中时值为1，0路命中时值为0 //TODO:支持更多路数
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// | bank |
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// | inst 0 | inst 1 |
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// | 32 | 32 |
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// 将一个 bank 中的指令分成 instFetchNum 份，每份 INST_WID bit
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val inst_in_bank = VecInit(
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Seq.tabulate(instFetchNum)(i => data(sel)(bank_index).asUInt((i + 1) * INST_WID - 1, i * INST_WID))
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Seq.tabulate(instFetchNum)(i => data(select_way)(bank_index).asUInt((i + 1) * INST_WID - 1, i * INST_WID))
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)
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// 将 inst_in_bank 中的指令按照 bank_offset 位偏移量重新排列
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@ -142,6 +145,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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// bank tag ram
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for { i <- 0 until nway } {
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// 每一个条目中有nbank个bank，每个bank存储instFetchNum个指令
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// 每次写入cache时将写完一整个cache行
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val bank =
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Seq.fill(nbank)(
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Seq.fill(instBlocksPerBank)(
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@ -168,6 +172,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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}
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for { i <- 0 until nway } {
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// 实例化了nway个tag ram
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val tag_bram = Module(new LUTRam(nindex, tagWidth))
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tag_bram.io.raddr := tag_raddr
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tag(i) := tag_bram.io.rdata
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@ -226,13 +231,13 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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arvalid := true.B
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replace_index := virtual_index
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repalce_wstrb(lru(virtual_index)).map(_.map(_ := false.B))
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repalce_wstrb(lru(virtual_index))(0)(0) := true.B // 从第一个bank的第一个指令块开始写入
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tag_wstrb(lru(virtual_index)) := true.B
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tag_wdata := io.cpu.tlb.tag
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valid(virtual_index)(lru(virtual_index)) := true.B
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repalce_wstrb(replace_way).map(_.map(_ := false.B))
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repalce_wstrb(replace_way)(0)(0) := true.B // 从第一个bank的第一个指令块开始写入
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tag_wstrb(replace_way) := true.B
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tag_wdata := io.cpu.tlb.tag
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valid(replace_way)(virtual_index) := true.B
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}.elsewhen(!io.cpu.icache_stall) {
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lru(virtual_index) := ~sel
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replace_way := ~select_way
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when(!io.cpu.cpu_ready) {
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state := s_save
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(1 until instFetchNum).foreach(i => saved(i).inst := inst(i))
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@ -266,12 +271,12 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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// * burst transport * //
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when(!io.axi.r.bits.last) {
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// 左移写掩码，写入下一个bank，或是同一个bank的下一个指令
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repalce_wstrb(lru(virtual_index)) :=
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((repalce_wstrb(lru(virtual_index)).asUInt << 1)).asTypeOf(repalce_wstrb(lru(virtual_index)))
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repalce_wstrb(replace_way) :=
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((repalce_wstrb(replace_way).asUInt << 1)).asTypeOf(repalce_wstrb(replace_way))
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}.otherwise {
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rready := false.B
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repalce_wstrb(lru(virtual_index)).map(_.map(_ := false.B))
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tag_wstrb(lru(virtual_index)) := false.B
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repalce_wstrb(replace_way).map(_.map(_ := false.B))
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tag_wstrb(replace_way) := false.B
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}
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}.elsewhen(!io.axi.r.ready) {
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state := s_idle
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