Liphen
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881b1eca3c
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refactor: 删除PC_WID
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2023-12-24 14:13:05 +08:00 |
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Liphen
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82b0912046
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fix(icache): 修复lru、valid存在的问题
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2023-12-24 14:04:29 +08:00 |
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Liphen
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61f0692e2a
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docs: 增加AXI文档
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2023-12-23 20:44:37 +08:00 |
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Liphen
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f67f96976a
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fix(icache): 配置成任意取指
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2023-12-23 13:44:45 +08:00 |
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Liphen
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442f51d5a4
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fix(icache): 修复之前icache遗留的问题
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2023-12-23 11:47:35 +08:00 |
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Liphen
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f4e0e1b5be
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refactor: nset改为nindex
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2023-12-22 18:12:56 +08:00 |
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Liphen
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969237a09f
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fix: 修复dcache的size
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2023-12-22 17:57:19 +08:00 |
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Liphen
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faa9fca6b9
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refactor(axi): 将常量移动到cache-axi中
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2023-12-22 14:56:31 +08:00 |
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Liphen
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c0bdc5a097
|
refactor: 部分常量换成XLEN
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2023-12-22 14:28:13 +08:00 |
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Liphen
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76c0f446da
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feat: 增加dcache
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2023-12-22 14:18:32 +08:00 |
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Liphen
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301199c756
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feat: 添加icache成功生成Verilog
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2023-12-21 15:24:57 +08:00 |
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Liphen
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3134b79c54
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增加puamips的cache文件
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2023-12-19 15:08:24 +08:00 |
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Liphen
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452b8ad995
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删除mem_wreg
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2023-12-10 22:23:22 +08:00 |
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Liphen
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2a16d26278
|
feat: 通过所有测试用例
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2023-12-07 21:14:40 +08:00 |
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Liphen
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44ac8853b8
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fix: 修复访存ready信号
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2023-12-07 17:41:47 +08:00 |
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Liphen
|
9524ee9919
|
fix(dcache): 解决写请求发生了两次的问题
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2023-12-07 17:04:04 +08:00 |
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Liphen
|
36840d6abe
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refactor(exe): 重构部分跳转信号
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2023-12-01 16:12:30 +08:00 |
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Liphen
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8a3e85b201
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删除addr_err
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2023-12-01 14:14:14 +08:00 |
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Liphen
|
ec946d5def
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revert(icache): 回退取指read next addr
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2023-11-30 15:45:40 +08:00 |
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Liphen
|
160daec1e2
|
fix(icache): 修复无cache时的取指问题
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2023-11-29 21:31:54 +08:00 |
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Liphen
|
1aeb3180ce
|
style(cache): 优化了下acc err写法
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2023-11-29 21:12:58 +08:00 |
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Liphen
|
610323dec9
|
fix: 例外判断缺少了int
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2023-11-29 15:37:45 +08:00 |
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Liphen
|
7195770448
|
fix(icache): acc err时应该把valid置为1
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2023-11-28 16:46:33 +08:00 |
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Liphen
|
588d94988b
|
fix(id): 输出的addr条件错误
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2023-11-28 15:14:19 +08:00 |
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Liphen
|
aac7d1ccb8
|
fix(mem): 修复wstrb错误
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2023-11-27 17:16:46 +08:00 |
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Liphen
|
e3366efc56
|
fix(icache): 修复stall逻辑
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2023-11-27 16:01:17 +08:00 |
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Liphen
|
b30026d57c
|
fix(dcache): 修改stall逻辑
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2023-11-27 15:22:49 +08:00 |
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Liphen
|
53860c99c6
|
fix(exe): 修复mem addr错误
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2023-11-27 14:55:04 +08:00 |
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Liphen
|
152bc91507
|
fix(dcache): 修复取数据问题
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2023-11-27 14:14:19 +08:00 |
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Liphen
|
94352e1687
|
fix(ExeAccessMem): 修复mem en信号错误
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2023-11-26 15:43:30 +08:00 |
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Liphen
|
fbeb9413ab
|
fix(icache): 修复取指bug
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2023-11-26 14:49:22 +08:00 |
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Liphen
|
703b70adf4
|
修改变量名
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2023-11-26 12:15:14 +08:00 |
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Liphen
|
7daed5b3a5
|
修改信号名
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2023-11-26 11:29:59 +08:00 |
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Liphen
|
3000c5b424
|
fix: 可以正常取指令了
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2023-11-24 12:05:47 +08:00 |
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Liphen
|
31eadb3bf3
|
feat: 成功读取到指令
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2023-11-23 21:51:57 +08:00 |
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Liphen
|
e909de6dfb
|
增加instrAddrMisaligned
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2023-11-22 13:42:59 +08:00 |
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Liphen
|
b657c0c7f0
|
ICache改为双取指
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2023-11-20 13:58:08 +08:00 |
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Liphen
|
ebbdd5b3b7
|
重构了下core
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2023-11-14 12:11:53 +08:00 |
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Liphen
|
f229789a12
|
feat: 修改并成功生成无cache的axi
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2023-11-13 17:56:41 +08:00 |
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Liphen
|
401149f111
|
feat: 增加cache至axi的转接桥
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2023-11-13 15:55:16 +08:00 |
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Liphen
|
e266678e90
|
修改cache代码
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2023-11-12 16:27:30 +08:00 |
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Liphen
|
8913ae5da0
|
修改了部分前端设计，去除cache、tlb
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2023-11-12 15:50:49 +08:00 |
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Liphen
|
3c7beb03c6
|
增加pua-mips代码
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2023-11-07 17:58:40 +08:00 |