ICache改为双取指

chisel/playground/src/CpuConfig.scala

@@ -12,10 +12,10 @@ case class CpuConfig(
   val hasUMode: Boolean = false, // 是否有U模式
   // 模块配置
   val hasCommitBuffer: Boolean = false, // 是否有提交缓存
-  val decoderNum:      Int     = 1, // 同时访问寄存器的指令数
-  val commitNum:       Int     = 1, // 同时提交的指令数
-  val fuNum:           Int     = 1, // 功能单元数
-  val instFetchNum:    Int     = 1, // iCache取到的指令数量
+  val decoderNum:      Int     = 2, // 同时访问寄存器的指令数
+  val commitNum:       Int     = 2, // 同时提交的指令数
+  val fuNum:           Int     = 2, // 功能单元数
+  val instFetchNum:    Int     = 2, // iCache取到的指令数量
   val instFifoDepth:   Int     = 8, // 指令缓存深度
   val mulClockNum:     Int     = 2, // 乘法器的时钟周期数
   val divClockNum:     Int     = 8, // 除法器的时钟周期数

chisel/playground/src/cache/ICache.scala

@@ -17,8 +17,8 @@ class ICache(implicit config: CpuConfig) extends Module {
   val s_idle :: s_read :: s_finishwait :: Nil = Enum(3)
   val status                                  = RegInit(s_idle)
 
-  io.cpu.valid := status === s_finishwait
-  val addr_err = io.cpu.addr.orR
+  io.cpu.valid.map(_ := status === s_finishwait)
+  val addr_err = io.cpu.addr(0).orR
 
   // default
   io.axi.ar.id    := 0.U
@@ -28,13 +28,13 @@ class ICache(implicit config: CpuConfig) extends Module {
   io.axi.ar.lock  := 0.U
   io.axi.ar.burst := BURST_FIXED.U
   val arvalid = RegInit(false.B)
-  io.axi.ar.valid := arvalid
-  io.axi.ar.prot  := 0.U
-  io.axi.ar.cache := 0.U
-  io.axi.r.ready  := true.B
-  io.cpu.rdata    := 0.U
-  io.cpu.acc_err  := false.B
-  io.cpu.stall    := false.B
+  io.axi.ar.valid    := arvalid
+  io.axi.ar.prot     := 0.U
+  io.axi.ar.cache    := 0.U
+  io.axi.r.ready     := true.B
+  io.cpu.rdata.map(_ := 0.U)
+  io.cpu.acc_err     := false.B
+  io.cpu.stall       := false.B
 
   switch(status) {
     is(s_idle) {
@@ -43,7 +43,7 @@ class ICache(implicit config: CpuConfig) extends Module {
           io.cpu.acc_err := true.B
           status         := s_finishwait
         }.otherwise {
-          io.axi.ar.addr := Cat(io.cpu.addr(31, 2), 0.U(2.W))
+          io.axi.ar.addr := Cat(io.cpu.addr(0)(31, 2), 0.U(2.W))
           arvalid        := true.B
           status         := s_read
         }
@@ -54,9 +54,10 @@ class ICache(implicit config: CpuConfig) extends Module {
         arvalid := false.B
       }
       when(io.axi.r.valid) {
-        io.cpu.rdata   := Mux(io.axi.ar.addr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0))
-        io.cpu.acc_err := io.axi.r.resp =/= RESP_OKEY.U
-        status         := s_finishwait
+        io.cpu.rdata(0) := Mux(io.axi.ar.addr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0))
+        io.cpu.rdata(1) := Mux(io.axi.ar.addr(2), 0.U, io.axi.r.data(63, 32))
+        io.cpu.acc_err  := io.axi.r.resp =/= RESP_OKEY.U
+        status          := s_finishwait
       }
     }
     is(s_finishwait) {
@@ -67,7 +68,7 @@ class ICache(implicit config: CpuConfig) extends Module {
             io.cpu.acc_err := true.B
             status         := s_finishwait
           }.otherwise {
-            io.axi.ar.addr := Cat(io.cpu.addr(31, 2), 0.U(2.W))
+            io.axi.ar.addr := Cat(io.cpu.addr(0)(31, 2), 0.U(2.W))
             arvalid        := true.B
             status         := s_read
           }

chisel/playground/src/defines/Bundles.scala

@@ -107,12 +107,12 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
   // read inst request from cpu
   val en      = Output(Bool())
   val ready   = Output(Bool())
-  val addr    = Output(UInt(INST_ADDR_WID.W)) // virtual address and next virtual address
+  val addr    = Output(Vec(config.instFetchNum,UInt(INST_ADDR_WID.W))) // virtual address and next virtual address
   val fence_i = Output(Bool())
 
   // read inst result
-  val rdata   = Input(UInt(INST_WID.W))
-  val valid   = Input(Bool())
+  val rdata   = Input(Vec(config.instFetchNum,UInt(INST_WID.W)))
+  val valid   = Input(Vec(config.instFetchNum,Bool()))
   val acc_err = Input(Bool())
   val stall   = Input(Bool())
 }

chisel/playground/src/defines/Util.scala

@@ -58,7 +58,7 @@ object Util {
 
   object LookupTreeDefault {
     def apply[T <: Data](key: UInt, default: T, mapping: Iterable[(UInt, T)]): T =
-      MuxLookup(key, default, mapping.toSeq)
+      MuxLookup(key, default)(mapping.toSeq)
   }
 
 }

chisel/playground/test/src/TestMain.scala

@@ -3,10 +3,11 @@ import circt.stage._
 import cache.Cache
 import cpu.pipeline.decoder.Decoder
 import cpu.pipeline.decoder.DecoderUnit
+import cache.ICache
 
 object TestMain extends App {
   implicit val config = new CpuConfig()
-  def top             = new DecoderUnit()
+  def top             = new Cache()
   val useMFC          = false // use MLIR-based firrtl compiler
   val generator       = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
   if (useMFC) {