style(cache): 优化了下acc err写法
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@ -65,17 +65,17 @@ class DCache(implicit config: CpuConfig) extends Module {
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val saved_rdata = RegInit(0.U(DATA_WID.W))
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val acc_err = RegInit(false.B)
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io.cpu.rdata := saved_rdata
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io.cpu.acc_err := acc_err
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val mmio_read_stall = !io.cpu.wen.orR
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val mmio_write_stall = io.cpu.wen.orR && !io.axi.w.ready
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val cached_stall = false.B
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io.cpu.dcache_stall := Mux(
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status === s_idle,
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status === s_idle && !acc_err,
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Mux(io.cpu.en, (cached_stall || mmio_read_stall || mmio_write_stall), io.cpu.fence_i),
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status =/= s_save
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)
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io.cpu.rdata := saved_rdata
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io.cpu.acc_err := acc_err
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switch(status) {
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is(s_idle) {
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@ -40,25 +40,26 @@ class ICache(implicit config: CpuConfig) extends Module {
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}))))
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io.axi.r.ready := true.B
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val acc_err = RegInit(false.B)
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io.cpu.acc_err := acc_err
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val acc_err = RegInit(false.B)
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val addr_err = io.cpu.addr(read_next_addr)(63, 32).orR
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(0 until config.instFetchNum).foreach(i => {
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io.cpu.inst(i) := saved(i).inst
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io.cpu.inst_valid(i) := saved(i).valid || acc_err
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io.cpu.inst(i) := Mux(status === s_idle && !acc_err, 0.U, saved(i).inst)
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io.cpu.inst_valid(i) := Mux(status === s_idle && !acc_err, false.B, saved(i).valid) && io.cpu.req
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})
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val addr_err = io.cpu.addr(read_next_addr)(63, 32).orR
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io.cpu.addr_err := addr_err
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io.cpu.icache_stall := Mux(status === s_idle, io.cpu.req, status =/= s_save)
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io.cpu.addr_err := addr_err
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io.cpu.acc_err := acc_err
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io.cpu.icache_stall := Mux(status === s_idle && !acc_err, io.cpu.req, status =/= s_save)
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switch(status) {
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is(s_idle) {
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acc_err := false.B
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when(io.cpu.req) {
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when(addr_err) {
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acc_err := true.B
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status := s_save
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acc_err := true.B
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saved(0).valid := true.B
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status := s_save
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}.otherwise {
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araddr := pc
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arvalid := true.B
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