feat: 增加cache至axi的转接桥
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Liphen
parent
e266678e90
commit
401149f111
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@ -10,71 +10,76 @@ class CacheAXIInterface extends Module {
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val dcache = Flipped(new DCache_AXIInterface())
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val axi = new AXI()
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})
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val ar_sel = Wire(Bool())
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val ar_sel_lock = RegInit(false.B)
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val ar_sel_lock_val = RegInit(false.B)
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// pass-through aw {
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io.axi.aw.id := io.dcache.aw.id
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io.axi.aw.addr := io.dcache.aw.addr
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io.axi.aw.len := io.dcache.aw.len
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io.axi.aw.size := io.dcache.aw.size
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io.axi.aw.burst := io.dcache.aw.burst
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io.axi.aw.valid := io.dcache.aw.valid
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io.axi.aw.prot := io.dcache.aw.prot
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io.axi.aw.cache := io.dcache.aw.cache
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io.axi.aw.lock := io.dcache.aw.lock
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io.dcache.aw.ready := io.axi.aw.ready
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// pass-through aw }
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// pass-through w {
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io.axi.w.id := io.dcache.w.id
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io.axi.w.data := io.dcache.w.data
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io.axi.w.strb := io.dcache.w.strb
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io.axi.w.last := io.dcache.w.last
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io.axi.w.valid := io.dcache.w.valid
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io.dcache.w.ready := io.axi.w.ready
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// pass-through aw }
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// pass-through b {
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io.dcache.b.id := io.axi.b.id
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io.dcache.b.valid := io.axi.b.valid
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io.dcache.b.resp := io.axi.b.resp
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io.axi.b.ready := io.dcache.b.ready
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// pass-through b }
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// mux ar {
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// we need to lock ar to avoid signals change during handshake
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val ar_sel_lock = RegInit(false.B)
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val ar_sel_val = RegInit(false.B)
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val ar_sel = Mux(ar_sel_lock, ar_sel_val, io.dcache.ar.valid)
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when(io.axi.ar.valid) {
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when(io.axi.ar.ready) {
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ar_sel_lock := false.B
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}.otherwise {
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ar_sel_lock := true.B
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ar_sel_lock_val := ar_sel
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ar_sel_lock := true.B
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ar_sel_val := ar_sel
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}
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}
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io.axi.ar.id := Cat(0.U(3.W), ar_sel)
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io.axi.ar.addr := Mux(ar_sel, io.dcache.ar.addr, io.icache.ar.addr)
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io.axi.ar.len := Mux(ar_sel, io.dcache.ar.len, io.icache.ar.len)
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io.axi.ar.size := Mux(ar_sel, io.dcache.ar.size, io.icache.ar.size)
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io.axi.ar.burst := Mux(ar_sel, io.dcache.ar.burst, io.icache.ar.burst)
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io.axi.ar.valid := Mux(ar_sel, io.dcache.ar.valid, io.icache.ar.valid)
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io.axi.ar.prot := Mux(ar_sel, io.dcache.ar.prot, io.icache.ar.prot)
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io.axi.ar.cache := Mux(ar_sel, io.dcache.ar.cache, io.icache.ar.cache)
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io.axi.ar.lock := Mux(ar_sel, io.dcache.ar.lock, io.icache.ar.lock)
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io.icache.ar.ready := !ar_sel && io.axi.ar.ready
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io.dcache.ar.ready := ar_sel && io.axi.ar.ready
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// mux ar }
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ar_sel := Mux(ar_sel_lock, ar_sel_lock_val, !io.icache.ar.valid && io.dcache.ar.valid)
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val r_sel = io.axi.r.bits.id(0)
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// ===----------------------------------------------------------------===
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// dcache
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// ===----------------------------------------------------------------===
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io.dcache.ar.ready := io.axi.ar.ready && ar_sel
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io.dcache.r.bits.data := Mux(r_sel, io.axi.r.bits.data, 0.U)
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io.dcache.r.bits.last := Mux(r_sel, io.axi.r.bits.last, 0.U)
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io.dcache.r.valid := Mux(r_sel, io.axi.r.valid, 0.U)
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io.dcache.aw.ready := io.axi.aw.ready
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io.dcache.w.ready := io.axi.w.ready
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io.dcache.b.valid := io.axi.b.valid
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// ===----------------------------------------------------------------===
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// icache
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// ===----------------------------------------------------------------===
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io.icache.ar.ready := io.axi.ar.ready && !ar_sel
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io.icache.r.bits.data := Mux(!r_sel, io.axi.r.bits.data, 0.U)
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io.icache.r.bits.last := Mux(!r_sel, io.axi.r.bits.last, 0.U)
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io.icache.r.valid := Mux(!r_sel, io.axi.r.valid, 0.U)
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// ===----------------------------------------------------------------===
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// axi
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// ===----------------------------------------------------------------===
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io.axi.ar.bits.id := ar_sel
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io.axi.ar.bits.addr := Mux(ar_sel, io.dcache.ar.bits.addr, io.icache.ar.bits.addr)
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io.axi.ar.bits.len := Mux(ar_sel, io.dcache.ar.bits.len, io.icache.ar.bits.len)
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io.axi.ar.bits.size := Mux(ar_sel, io.dcache.ar.bits.size, io.icache.ar.bits.size)
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io.axi.ar.bits.burst := 1.U
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io.axi.ar.bits.lock := 0.U
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io.axi.ar.bits.cache := 0.U
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io.axi.ar.bits.prot := 0.U
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io.axi.ar.valid := Mux(ar_sel, io.dcache.ar.valid, io.icache.ar.valid)
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io.axi.r.ready := Mux(~r_sel, io.icache.r.ready, io.dcache.r.ready)
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io.axi.aw.bits.id := 0.U
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io.axi.aw.bits.addr := io.dcache.aw.bits.addr
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io.axi.aw.bits.len := io.dcache.aw.bits.len
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io.axi.aw.bits.size := io.dcache.aw.bits.size
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io.axi.aw.bits.burst := 1.U
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io.axi.aw.bits.lock := 0.U
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io.axi.aw.bits.cache := 0.U
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io.axi.aw.bits.prot := 0.U
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io.axi.aw.valid := io.dcache.aw.valid
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io.axi.w.bits.id := 0.U
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io.axi.w.bits.data := io.dcache.w.bits.data
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io.axi.w.bits.strb := io.dcache.w.bits.strb
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io.axi.w.bits.last := io.dcache.w.bits.last
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io.axi.w.valid := io.dcache.w.valid
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io.axi.b.ready := io.dcache.b.ready
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// mux r based on rid {
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val r_sel = io.axi.r.id(0)
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io.icache.r.id := io.axi.r.id
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io.icache.r.data := io.axi.r.data
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io.icache.r.resp := io.axi.r.resp
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io.icache.r.last := io.axi.r.last
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io.icache.r.valid := !r_sel && io.axi.r.valid
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io.dcache.r.id := io.axi.r.id
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io.dcache.r.data := io.axi.r.data
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io.dcache.r.resp := io.axi.r.resp
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io.dcache.r.last := io.axi.r.last
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io.dcache.r.valid := r_sel && io.axi.r.valid
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io.axi.r.ready := Mux(r_sel, io.dcache.r.ready, io.icache.r.ready)
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// mux r based on rid }
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}
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