From 401149f11118e5a53ad098926ba2f7f9c190b704 Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 13 Nov 2023 15:55:16 +0800 Subject: [PATCH] =?UTF-8?q?feat:=20=E5=A2=9E=E5=8A=A0cache=E8=87=B3axi?= =?UTF-8?q?=E7=9A=84=E8=BD=AC=E6=8E=A5=E6=A1=A5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../src/cache/CacheAXIInterface.scala | 125 +++++++++--------- 1 file changed, 65 insertions(+), 60 deletions(-) diff --git a/chisel/playground/src/cache/CacheAXIInterface.scala b/chisel/playground/src/cache/CacheAXIInterface.scala index d32aaa2..d378eef 100644 --- a/chisel/playground/src/cache/CacheAXIInterface.scala +++ b/chisel/playground/src/cache/CacheAXIInterface.scala @@ -10,71 +10,76 @@ class CacheAXIInterface extends Module { val dcache = Flipped(new DCache_AXIInterface()) val axi = new AXI() }) - val ar_sel = Wire(Bool()) - val ar_sel_lock = RegInit(false.B) - val ar_sel_lock_val = RegInit(false.B) + + // pass-through aw { + io.axi.aw.id := io.dcache.aw.id + io.axi.aw.addr := io.dcache.aw.addr + io.axi.aw.len := io.dcache.aw.len + io.axi.aw.size := io.dcache.aw.size + io.axi.aw.burst := io.dcache.aw.burst + io.axi.aw.valid := io.dcache.aw.valid + io.axi.aw.prot := io.dcache.aw.prot + io.axi.aw.cache := io.dcache.aw.cache + io.axi.aw.lock := io.dcache.aw.lock + io.dcache.aw.ready := io.axi.aw.ready + // pass-through aw } + + // pass-through w { + io.axi.w.id := io.dcache.w.id + io.axi.w.data := io.dcache.w.data + io.axi.w.strb := io.dcache.w.strb + io.axi.w.last := io.dcache.w.last + io.axi.w.valid := io.dcache.w.valid + io.dcache.w.ready := io.axi.w.ready + // pass-through aw } + + // pass-through b { + io.dcache.b.id := io.axi.b.id + io.dcache.b.valid := io.axi.b.valid + io.dcache.b.resp := io.axi.b.resp + io.axi.b.ready := io.dcache.b.ready + // pass-through b } + + // mux ar { + // we need to lock ar to avoid signals change during handshake + val ar_sel_lock = RegInit(false.B) + val ar_sel_val = RegInit(false.B) + val ar_sel = Mux(ar_sel_lock, ar_sel_val, io.dcache.ar.valid) + when(io.axi.ar.valid) { when(io.axi.ar.ready) { ar_sel_lock := false.B }.otherwise { - ar_sel_lock := true.B - ar_sel_lock_val := ar_sel + ar_sel_lock := true.B + ar_sel_val := ar_sel } + } + io.axi.ar.id := Cat(0.U(3.W), ar_sel) + io.axi.ar.addr := Mux(ar_sel, io.dcache.ar.addr, io.icache.ar.addr) + io.axi.ar.len := Mux(ar_sel, io.dcache.ar.len, io.icache.ar.len) + io.axi.ar.size := Mux(ar_sel, io.dcache.ar.size, io.icache.ar.size) + io.axi.ar.burst := Mux(ar_sel, io.dcache.ar.burst, io.icache.ar.burst) + io.axi.ar.valid := Mux(ar_sel, io.dcache.ar.valid, io.icache.ar.valid) + io.axi.ar.prot := Mux(ar_sel, io.dcache.ar.prot, io.icache.ar.prot) + io.axi.ar.cache := Mux(ar_sel, io.dcache.ar.cache, io.icache.ar.cache) + io.axi.ar.lock := Mux(ar_sel, io.dcache.ar.lock, io.icache.ar.lock) + io.icache.ar.ready := !ar_sel && io.axi.ar.ready + io.dcache.ar.ready := ar_sel && io.axi.ar.ready + // mux ar } - ar_sel := Mux(ar_sel_lock, ar_sel_lock_val, !io.icache.ar.valid && io.dcache.ar.valid) - val r_sel = io.axi.r.bits.id(0) - - // ===----------------------------------------------------------------=== - // dcache - // ===----------------------------------------------------------------=== - io.dcache.ar.ready := io.axi.ar.ready && ar_sel - io.dcache.r.bits.data := Mux(r_sel, io.axi.r.bits.data, 0.U) - io.dcache.r.bits.last := Mux(r_sel, io.axi.r.bits.last, 0.U) - io.dcache.r.valid := Mux(r_sel, io.axi.r.valid, 0.U) - - io.dcache.aw.ready := io.axi.aw.ready - io.dcache.w.ready := io.axi.w.ready - io.dcache.b.valid := io.axi.b.valid - - // ===----------------------------------------------------------------=== - // icache - // ===----------------------------------------------------------------=== - io.icache.ar.ready := io.axi.ar.ready && !ar_sel - io.icache.r.bits.data := Mux(!r_sel, io.axi.r.bits.data, 0.U) - io.icache.r.bits.last := Mux(!r_sel, io.axi.r.bits.last, 0.U) - io.icache.r.valid := Mux(!r_sel, io.axi.r.valid, 0.U) - - // ===----------------------------------------------------------------=== - // axi - // ===----------------------------------------------------------------=== - io.axi.ar.bits.id := ar_sel - io.axi.ar.bits.addr := Mux(ar_sel, io.dcache.ar.bits.addr, io.icache.ar.bits.addr) - io.axi.ar.bits.len := Mux(ar_sel, io.dcache.ar.bits.len, io.icache.ar.bits.len) - io.axi.ar.bits.size := Mux(ar_sel, io.dcache.ar.bits.size, io.icache.ar.bits.size) - io.axi.ar.bits.burst := 1.U - io.axi.ar.bits.lock := 0.U - io.axi.ar.bits.cache := 0.U - io.axi.ar.bits.prot := 0.U - io.axi.ar.valid := Mux(ar_sel, io.dcache.ar.valid, io.icache.ar.valid) - - io.axi.r.ready := Mux(~r_sel, io.icache.r.ready, io.dcache.r.ready) - - io.axi.aw.bits.id := 0.U - io.axi.aw.bits.addr := io.dcache.aw.bits.addr - io.axi.aw.bits.len := io.dcache.aw.bits.len - io.axi.aw.bits.size := io.dcache.aw.bits.size - io.axi.aw.bits.burst := 1.U - io.axi.aw.bits.lock := 0.U - io.axi.aw.bits.cache := 0.U - io.axi.aw.bits.prot := 0.U - io.axi.aw.valid := io.dcache.aw.valid - - io.axi.w.bits.id := 0.U - io.axi.w.bits.data := io.dcache.w.bits.data - io.axi.w.bits.strb := io.dcache.w.bits.strb - io.axi.w.bits.last := io.dcache.w.bits.last - io.axi.w.valid := io.dcache.w.valid - - io.axi.b.ready := io.dcache.b.ready + // mux r based on rid { + val r_sel = io.axi.r.id(0) + io.icache.r.id := io.axi.r.id + io.icache.r.data := io.axi.r.data + io.icache.r.resp := io.axi.r.resp + io.icache.r.last := io.axi.r.last + io.icache.r.valid := !r_sel && io.axi.r.valid + io.dcache.r.id := io.axi.r.id + io.dcache.r.data := io.axi.r.data + io.dcache.r.resp := io.axi.r.resp + io.dcache.r.last := io.axi.r.last + io.dcache.r.valid := r_sel && io.axi.r.valid + io.axi.r.ready := Mux(r_sel, io.dcache.r.ready, io.icache.r.ready) + // mux r based on rid } }