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fix(id): 输出的addr条件错误

This commit is contained in:
Liphen 2023-11-28 15:14:19 +08:00
parent aac7d1ccb8
commit 588d94988b
2 changed files with 3 additions and 4 deletions
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3
chisel/playground/src/cache/DCache.scala vendored
View File

@ -49,11 +49,10 @@ class DCache(implicit config: CpuConfig) extends Module {
val araddr = RegInit(0.U(AXI_ADDR_WID.W))
val arsize = RegInit(0.U(AXI_SIZE_WID.W))
val arlen = RegInit(0.U(AXI_LEN_WID.W))
val arvalid = RegInit(false.B)
io.axi.ar.id := 1.U
io.axi.ar.addr := araddr
io.axi.ar.len := arlen
io.axi.ar.len := 0.U
io.axi.ar.size := arsize
io.axi.ar.burst := BURST_INCR.U
io.axi.ar.valid := arvalid

4
chisel/playground/src/pipeline/decoder/Decoder.scala
View File

@ -39,9 +39,9 @@ class Decoder extends Module with HasInstrType {
io.out.inst_info.valid := false.B
io.out.inst_info.inst_legal := instrType =/= InstrN
io.out.inst_info.reg1_ren := src1Type === SrcType.reg || inst(6, 0) === "b0110111".U // fix LUI
io.out.inst_info.reg1_raddr := Mux(src1Type === SrcType.reg, rs, 0.U)
io.out.inst_info.reg1_raddr := Mux(io.out.inst_info.reg1_ren, rs, 0.U)
io.out.inst_info.reg2_ren := src2Type === SrcType.reg
io.out.inst_info.reg2_raddr := Mux(src2Type === SrcType.reg, rt, 0.U)
io.out.inst_info.reg2_raddr := Mux(io.out.inst_info.reg2_ren, rt, 0.U)
io.out.inst_info.fusel := fuType
io.out.inst_info.op := fuOpType
// when(fuType === FuType.bru) {