diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala
index 67f79d5..7ae668b 100644
--- a/chisel/playground/src/cache/DCache.scala
+++ b/chisel/playground/src/cache/DCache.scala
@@ -49,11 +49,10 @@ class DCache(implicit config: CpuConfig) extends Module {
 
   val araddr  = RegInit(0.U(AXI_ADDR_WID.W))
   val arsize  = RegInit(0.U(AXI_SIZE_WID.W))
-  val arlen   = RegInit(0.U(AXI_LEN_WID.W))
   val arvalid = RegInit(false.B)
   io.axi.ar.id    := 1.U
   io.axi.ar.addr  := araddr
-  io.axi.ar.len   := arlen
+  io.axi.ar.len   := 0.U
   io.axi.ar.size  := arsize
   io.axi.ar.burst := BURST_INCR.U
   io.axi.ar.valid := arvalid
diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala
index 969abc5..a911c0f 100644
--- a/chisel/playground/src/pipeline/decoder/Decoder.scala
+++ b/chisel/playground/src/pipeline/decoder/Decoder.scala
@@ -39,9 +39,9 @@ class Decoder extends Module with HasInstrType {
   io.out.inst_info.valid      := false.B
   io.out.inst_info.inst_legal := instrType =/= InstrN
   io.out.inst_info.reg1_ren   := src1Type === SrcType.reg || inst(6, 0) === "b0110111".U // fix LUI
-  io.out.inst_info.reg1_raddr := Mux(src1Type === SrcType.reg, rs, 0.U)
+  io.out.inst_info.reg1_raddr := Mux(io.out.inst_info.reg1_ren, rs, 0.U)
   io.out.inst_info.reg2_ren   := src2Type === SrcType.reg
-  io.out.inst_info.reg2_raddr := Mux(src2Type === SrcType.reg, rt, 0.U)
+  io.out.inst_info.reg2_raddr := Mux(io.out.inst_info.reg2_ren, rt, 0.U)
   io.out.inst_info.fusel      := fuType
   io.out.inst_info.op         := fuOpType
   // when(fuType === FuType.bru) {