Liphen
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f7fb3c4677
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fix(icache): 当地址未对齐时不应访存
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2024-03-09 16:12:56 +08:00 |
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Liphen
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3b330cf8d7
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fix(cache): 修复fault信号的wait阶段复位
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2024-01-20 14:32:18 +08:00 |
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Liphen
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a99cf13f87
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tlb支持巨页
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2024-01-18 16:10:59 +08:00 |
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Liphen
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f182d9b1b1
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fix: ptw的windex问题
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2024-01-18 13:30:40 +08:00 |
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Liphen
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7d795f6d80
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fix(cache): sv39高位需要一致
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2024-01-17 15:30:25 +08:00 |
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Liphen
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b16eff1ba7
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增加lsu的例外处理
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2024-01-15 16:01:22 +08:00 |
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Liphen
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2f3ff6e5dd
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完成除vma指令外的框架
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2024-01-15 13:36:44 +08:00 |
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Liphen
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07490e0f13
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搭了下itlb的框架
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2024-01-13 17:09:01 +08:00 |
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Liphen
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6ca4ffcd86
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refactor: 重构tlb
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2024-01-13 13:13:31 +08:00 |
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Liphen
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eeb076b060
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增加tlb相关常量定义
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2024-01-03 16:17:36 +08:00 |
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Liphen
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78ca79384e
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style: config统一为cpuConfig
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2024-01-03 14:29:19 +08:00 |
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Liphen
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f3d5b5cd1e
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refactor: 将所有的地址宽度调为XLEN
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2024-01-03 10:54:44 +08:00 |
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Liphen
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b21a26f947
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feat(cache): 实现了fence
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2023-12-29 11:14:04 +08:00 |
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Liphen
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7470c6fb5f
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增加fence，修复dcache的一处bug
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2023-12-28 22:21:38 +08:00 |
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Liphen
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82f9573fad
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refactor(cache): 删去无用信号，修改cache大小
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2023-12-28 16:06:54 +08:00 |
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Liphen
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b45e0194fa
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refactor(cache): 进行部分变量替换
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2023-12-28 13:40:25 +08:00 |
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Liphen
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c112df3e35
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style(cache): use next addr信号名修改
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2023-12-26 14:56:02 +08:00 |
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Liphen
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108c529698
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fix(cache): 将save状态改成wait，更符合作用
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2023-12-25 15:45:30 +08:00 |
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Liphen
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ac6aefff8a
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style(tlb): 加上p的前缀表示物理地址
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2023-12-25 14:08:54 +08:00 |
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Liphen
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90bc47c48b
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fix(dcache): 修复显著的问题，目前仍存在bug
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2023-12-25 14:02:01 +08:00 |
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Liphen
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e646ee4a4c
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docs(cache): 增加注释
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2023-12-24 16:21:53 +08:00 |
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Liphen
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03ccee30f6
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style(icache): module使用小驼峰命名法
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2023-12-24 14:14:40 +08:00 |
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Liphen
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82b0912046
|
fix(icache): 修复lru、valid存在的问题
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2023-12-24 14:04:29 +08:00 |
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Liphen
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61f0692e2a
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docs: 增加AXI文档
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2023-12-23 20:44:37 +08:00 |
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Liphen
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f67f96976a
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fix(icache): 配置成任意取指
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2023-12-23 13:44:45 +08:00 |
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Liphen
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442f51d5a4
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fix(icache): 修复之前icache遗留的问题
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2023-12-23 11:47:35 +08:00 |
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Liphen
|
f4e0e1b5be
|
refactor: nset改为nindex
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2023-12-22 18:12:56 +08:00 |
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Liphen
|
faa9fca6b9
|
refactor(axi): 将常量移动到cache-axi中
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2023-12-22 14:56:31 +08:00 |
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Liphen
|
c0bdc5a097
|
refactor: 部分常量换成XLEN
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2023-12-22 14:28:13 +08:00 |
|
Liphen
|
301199c756
|
feat: 添加icache成功生成Verilog
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2023-12-21 15:24:57 +08:00 |
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Liphen
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452b8ad995
|
删除mem_wreg
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2023-12-10 22:23:22 +08:00 |
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Liphen
|
8a3e85b201
|
删除addr_err
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2023-12-01 14:14:14 +08:00 |
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Liphen
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ec946d5def
|
revert(icache): 回退取指read next addr
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2023-11-30 15:45:40 +08:00 |
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Liphen
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160daec1e2
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fix(icache): 修复无cache时的取指问题
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2023-11-29 21:31:54 +08:00 |
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Liphen
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1aeb3180ce
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style(cache): 优化了下acc err写法
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2023-11-29 21:12:58 +08:00 |
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Liphen
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610323dec9
|
fix: 例外判断缺少了int
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2023-11-29 15:37:45 +08:00 |
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Liphen
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7195770448
|
fix(icache): acc err时应该把valid置为1
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2023-11-28 16:46:33 +08:00 |
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Liphen
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aac7d1ccb8
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fix(mem): 修复wstrb错误
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2023-11-27 17:16:46 +08:00 |
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Liphen
|
e3366efc56
|
fix(icache): 修复stall逻辑
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2023-11-27 16:01:17 +08:00 |
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Liphen
|
fbeb9413ab
|
fix(icache): 修复取指bug
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2023-11-26 14:49:22 +08:00 |
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Liphen
|
703b70adf4
|
修改变量名
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2023-11-26 12:15:14 +08:00 |
|
Liphen
|
7daed5b3a5
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修改信号名
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2023-11-26 11:29:59 +08:00 |
|
Liphen
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3000c5b424
|
fix: 可以正常取指令了
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2023-11-24 12:05:47 +08:00 |
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Liphen
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31eadb3bf3
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feat: 成功读取到指令
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2023-11-23 21:51:57 +08:00 |
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Liphen
|
e909de6dfb
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增加instrAddrMisaligned
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2023-11-22 13:42:59 +08:00 |
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Liphen
|
b657c0c7f0
|
ICache改为双取指
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2023-11-20 13:58:08 +08:00 |
|
Liphen
|
ebbdd5b3b7
|
重构了下core
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2023-11-14 12:11:53 +08:00 |
|
Liphen
|
f229789a12
|
feat: 修改并成功生成无cache的axi
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2023-11-13 17:56:41 +08:00 |
|
Liphen
|
e266678e90
|
修改cache代码
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2023-11-12 16:27:30 +08:00 |
|
Liphen
|
8913ae5da0
|
修改了部分前端设计，去除cache、tlb
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2023-11-12 15:50:49 +08:00 |