feat(cache): 实现了fence
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Liphen
parent
0275ea313d
commit
b21a26f947
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@ -103,15 +103,16 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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// * valid dirty * //
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// 每行有一个有效位和一个脏位
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val valid = RegInit(VecInit(Seq.fill(nindex)(VecInit(Seq.fill(nway)(false.B)))))
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val valid = RegInit(VecInit(Seq.fill(nindex)(VecInit(Seq.fill(nway)(false.B))))) // FIXME：nway放前面会导致栈溢出错误
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val dirty = RegInit(VecInit(Seq.fill(nindex)(VecInit(Seq.fill(nway)(false.B)))))
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val lru = RegInit(VecInit(Seq.fill(nindex)(false.B))) // TODO:支持更多路数，目前只支持2路
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val dirty_table = Wire(Vec(nindex, UInt(nway.W))) // 0:第0路脏位为真，1:第1路脏位为真，2:两路都为假
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val dirty_index = Wire(UInt(indexWidth.W))
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val dirty_way = dirty_table(dirty_index) // 用于指示哪个路的脏位为真
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val writeback_index = RegInit(0.U(indexWidth.W))
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val writeback_tag = RegInit(0.U(tagWidth.W))
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// 0:第0路脏位为真，1:第1路脏位为真，2:两路都为假
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val dirty_table = Wire(Vec(nindex, UInt(log2Ceil(nway + 1).W)))
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// 用于指示哪个行的脏位为真
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val dirty_index = Wire(UInt(indexWidth.W))
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// 用于指示哪个路的脏位为真
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val dirty_way = dirty_table(dirty_index)
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for (i <- 0 until nindex) {
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dirty_table(i) := MuxCase(
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@ -125,7 +126,9 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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dirty_index := PriorityEncoder(dirty_table.map(w => w =/= 2.U))
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val fence = RegInit(false.B)
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// 表示进入fence的写回状态
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val fence = RegInit(false.B)
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// 表示准备好了fence的写回数据，因为bank读数据要两拍
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val fence_data_ready = RegInit(false.B)
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// 对于uncached段使用writeFifo进行写回
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@ -143,7 +146,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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}))
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// 用于解决在replace时读写时序不一致的问题
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val bank_woffset = RegInit(0.U((offsetWidth - log2Ceil(XLEN / 8)).W))
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val bank_windex = RegInit(0.U((offsetWidth - log2Ceil(XLEN / 8)).W))
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val bank_replication = RegInit(VecInit(Seq.fill(nbank)(0.U(XLEN.W))))
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// 是否使用exe的地址进行提前访存
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@ -318,7 +321,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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}.otherwise {
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when(!cache_hit) {
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state := s_replace
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bank_woffset := 0.U
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bank_windex := 0.U
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burst.wstrb(replace_way) := 1.U // 先写入第一块bank
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when(replace_dirty) {
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// cache行的脏位为真时需要写回，备份一下cache行，便于处理读写时序问题
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@ -370,15 +373,15 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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when(w.last) {
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wvalid := false.B
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}.otherwise {
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bank_woffset := bank_woffset + 1.U
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w.data := data(bank_woffset + 1.U)(dirty_way)
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when(bank_woffset + 1.U === (cached_len).U) {
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bank_windex := bank_windex + 1.U
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w.data := data(bank_windex + 1.U)(dirty_way)
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when(bank_windex + 1.U === (cached_len).U) {
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w.last := true.B
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}
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}
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}
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when(io.axi.b.valid) {
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// TODO: 增加此处的错误处理
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// TODO: 增加此处的acc_err错误处理
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// acc_err := io.axi.b.bits.resp =/= RESP_OKEY.U
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dirty(dirty_index)(dirty_way) := false.B // 写回完成，清除脏位
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fence_data_ready := false.B
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@ -386,23 +389,21 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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}
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}.elsewhen(dirty.asUInt.orR) {
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when(fence_data_ready) {
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writeback_index := dirty_index // 方便debug
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writeback_tag := Mux(dirty_way === 0.U, tagRam(0).io.rdata, tagRam(1).io.rdata) // 方便debug
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// for axi write
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aw.addr := Cat(
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Mux(dirty_way === 0.U, tagRam(0).io.rdata, tagRam(1).io.rdata),
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dirty_index,
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0.U(offsetWidth.W)
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)
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aw.len := cached_len.U
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aw.size := cached_size.U
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awvalid := true.B
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w.data := data(0)(dirty_way) // 从第零块bank开始写回
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w.strb := ~0.U(AXI_STRB_WID.W)
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w.last := false.B
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wvalid := true.B
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bank_woffset := 0.U
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fence := true.B
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aw.len := cached_len.U
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aw.size := cached_size.U
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awvalid := true.B
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w.data := data(0)(dirty_way) // 从第零块bank开始写回
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w.strb := ~0.U(AXI_STRB_WID.W)
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w.last := false.B
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wvalid := true.B
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bank_windex := 0.U
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fence := true.B
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}.otherwise {
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fence_data_ready := true.B
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}
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@ -422,15 +423,15 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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when(w.last) {
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wvalid := false.B
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}.otherwise {
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bank_woffset := bank_woffset + 1.U
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w.data := bank_replication(bank_woffset + 1.U)
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when(bank_woffset + 1.U === (cached_len).U) {
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bank_windex := bank_windex + 1.U
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w.data := bank_replication(bank_windex + 1.U)
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when(bank_windex + 1.U === (cached_len).U) {
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w.last := true.B
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}
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}
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}
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when(io.axi.b.valid) {
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// TODO: 增加此处的错误处理
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// TODO: 增加此处的acc_err错误处理
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// acc_err := io.axi.b.bits.resp =/= RESP_OKEY.U
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replace_dirty := false.B // 写回完成，清除脏位
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}
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@ -469,15 +470,15 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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tag_wstrb(replace_way) := true.B
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tag_wdata := io.cpu.tlb.ptag
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when(replace_dirty) {
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aw.addr := Cat(tag(replace_way), replace_index, 0.U(offsetWidth.W))
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aw.len := cached_len.U
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aw.size := cached_size.U
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awvalid := true.B
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w.data := data(0)(replace_way)
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w.strb := ~0.U(AXI_STRB_WID.W)
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w.last := false.B
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wvalid := true.B
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bank_woffset := 0.U
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aw.addr := Cat(tag(replace_way), replace_index, 0.U(offsetWidth.W))
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aw.len := cached_len.U
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aw.size := cached_size.U
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awvalid := true.B
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w.data := data(0)(replace_way)
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w.strb := ~0.U(AXI_STRB_WID.W)
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w.last := false.B
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wvalid := true.B
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bank_windex := 0.U
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}
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}
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}
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@ -99,14 +99,6 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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when(tlb_fill) { tlb_fill := false.B }
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io.cpu.tlb.fill := tlb_fill
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// * fence * //
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// fence指令时清空cache，等同于将所有valid位置0
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when(io.cpu.fence_i) {
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// TODO：还要考虑更复杂的情况，比如说打断了读
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valid := 0.U.asTypeOf(valid)
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state := s_fence
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}
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// * lru * //// TODO:检查lru的正确性，增加可拓展性，目前只支持两路的cache
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val lru = RegInit(VecInit(Seq.fill(nindex)(false.B)))
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@ -306,13 +298,20 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
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}
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}
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is(s_fence) {
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// 等待dcache完成写回操作
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when(io.cpu.complete_single_request && !io.cpu.dcache_stall) {
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// 等待dcache完成写回操作，且等待axi总线完成读取操作，因为icache发生状态转移时可能正在读取数据
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when(!io.cpu.dcache_stall && !io.axi.r.valid) {
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state := s_idle
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}
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}
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}
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// * fence * //
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// 不论icache在什么状态，fence指令优先度最高，会强制将icache状态转移为s_fence
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when(io.cpu.fence_i) {
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valid := 0.U.asTypeOf(valid) // fence.i指令需要icache，等同于将所有valid位置0
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state := s_fence
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}
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println("----------------------------------------")
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println("ICache: ")
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println("nindex: " + nindex)
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