!1016 refactor: 不同C库malloc归一

Merge pull request !1016 from Zhaotianyu/20230117libc_malloc
refactor: 不同C库的malloc适配归一
2023-01-18 09:56:58 +00:00 · 2023-01-18 11:22:01 +08:00 · 2023-01-13 08:54:49 +00:00 · 2023-01-13 05:42:29 +00:00 · 2023-01-13 11:34:52 +08:00 · 2023-01-12 15:30:19 +08:00
732 changed files with 27250 additions and 47396 deletions
--- a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md
+++ b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md
@@ -10,6 +10,12 @@
 ### 测试用例（新增、改动、可能影响的功能）


+### 是否涉及对外变更（典型的如：对外API规格变更、新增对外接口等等）
+
+必须选择一项（在MarkDown模式下用[x]替换[ ]即可勾选对应选项）:
+- [ ] 是，涉及对外变更: 需要在commit message中按【[模板要求](https://gitee.com/openharmony/kernel_liteos_m/wikis/Commit%20message%E8%A7%84%E8%8C%83)】描述变更点
+- [ ] 否，不涉及对外变更
+
 ### 是否需要同步至release（如：3.0LTS ... ）分支？

 必须选择一项（在MarkDown模式下用[x]替换[ ]即可勾选对应选项）:
--- a/BUILD.gn
+++ b/BUILD.gn
@@ -31,163 +31,76 @@ import("//build/lite/config/component/lite_component.gni")

 LITEOS_MENUCONFIG_H = rebase_path("$root_out_dir/config.h")

-declare_args() {
-  liteos_name = "OHOS_Image"
-  liteos_kernel_only = false
-}
-
 import("liteos.gni")

-liteos_arch_cflags = []
-if (defined(LOSCFG_ARCH_ARM)) {
-  mcpu = LOSCFG_ARCH_CPU
-  if (defined(LOSCFG_ARCH_ARM_AARCH64) && defined(LOSCFG_ARCH_FPU_DISABLE)) {
-    mcpu += "+nofp"
-  }
-  liteos_arch_cflags += [ "-mcpu=$mcpu" ]
-  if (defined(LOSCFG_ARCH_ARM_AARCH32) && defined(LOSCFG_ARCH_FPU)) {
-    liteos_arch_cflags += [ "-mfpu=$LOSCFG_ARCH_FPU" ]
-  }
-}
+if (defined(LOSCFG_COMPILER_ICCARM)) {
+  import("config_iccarm.gni")
+} else {
+  import("config.gni")

-cc = "$ohos_current_cc_command " + string_join(" ", liteos_arch_cflags)
-if (ohos_build_compiler == "clang") {
-  cc += " --target=$target_triple"
+  cc = "$ohos_current_cc_command " + string_join(" ", liteos_arch_config_cflags)
+  if (ohos_build_compiler == "clang") {
+    cc += " --target=$target_triple"
+  }
 }

 config("arch_config") {
-  cflags = liteos_arch_cflags
-  asmflags = cflags
-  ldflags = cflags
-  if (defined(LOSCFG_ARCH_ARM_AARCH32)) {
-    if (!defined(LOSCFG_COMPILER_CLANG_LLVM)) {
-      cflags += [ "-mthumb-interwork" ]
-    }
-  }
-  if (defined(LOSCFG_THUMB)) {
-    cflags += [ "-mthumb" ]
-    if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
-      cflags += [ "-mimplicit-it=thumb" ]
-    } else {
-      cflags += [ "-Wa,-mimplicit-it=thumb" ]
-    }
-  }
+  cflags = arch_config_cflags
+  asmflags = arch_config_asmflags
+  ldflags = arch_config_ldflags
 }

 config("stdinc_config") {
-  std_include = exec_script("//build/lite/run_shell_cmd.py",
-                            [ "$cc -print-file-name=include" ],
-                            "trim string")
-  cflags = [
-    "-isystem",
-    std_include,
-  ]
-  if (defined(LOSCFG_LIBC_MUSL)) {
-    cflags += [ "-nostdinc" ]
+  cflags = stdinc_config_cflags
+  asmflags = stdinc_config_asmflags
+  if (!defined(LOSCFG_COMPILER_ICCARM)) {
+    std_include = exec_script("//build/lite/run_shell_cmd.py",
+                              [ "$cc -print-file-name=include" ],
+                              "trim string")
+    cflags += [
+      "-isystem",
+      std_include,
+    ]
  }
-  asmflags = cflags
 }

 config("ssp_config") {
-  cflags = []
-  if (defined(LOSCFG_CC_STACKPROTECTOR_ALL)) {
-    cflags += [ "-fstack-protector-all" ]
-  } else if (defined(LOSCFG_CC_STACKPROTECTOR_STRONG)) {
-    cflags += [ "-fstack-protector-strong" ]
-  } else if (defined(LOSCFG_CC_STACKPROTECTOR)) {
-    cflags += [
-      "-fstack-protector",
-      "--param",
-      "ssp-buffer-size=4",
-    ]
-  } else {
-    cflags += [ "-fno-stack-protector" ]
-  }
-  asmflags = cflags
+  cflags = ssp_config_cflags
+  asmflags = ssp_config_asmflags
 }

 config("optimize_config") {
-  cflags = []
-  if (defined(LOSCFG_COMPILE_DEBUG)) {
-    cflags += [
-      "-g",
-      "-gdwarf-2",
-    ]
-    optimization_cflag = "-O0"
-  }
-  if (defined(LOSCFG_COMPILE_OPTIMIZE)) {
-    optimization_cflag = "-O2"
-  }
-  if (defined(LOSCFG_COMPILE_OPTIMIZE_SIZE)) {
-    if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
-      optimization_cflag = "-Oz"
-    } else {
-      optimization_cflag = "-Os"
-    }
-  }
-  if (defined(LOSCFG_COMPILE_LTO)) {
-    if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
-      cflags += [ "-flto=thin" ]
-    } else {
-      #cflags += [ "-flto" ]
-    }
-  }
-  cflags += [ optimization_cflag ]
-  asmflags = cflags
+  cflags = optimize_config_cflags
+  asmflags = optimize_config_asmflags
 }

 config("kconfig_config") {
-  cflags = [
-    "-imacros",
-    "$LITEOS_MENUCONFIG_H",
-  ]
-  asmflags = cflags
-  cflags_cc = cflags
+  cflags = kconfig_config_cflags
+  asmflags = kconfig_config_asmflags
 }

 config("warn_config") {
-  cflags = [
-    "-Wall",
-    "-Werror",
-    "-Wpointer-arith",
-    "-Wstrict-prototypes",
-    "-Winvalid-pch",
-    "-Wno-address-of-packed-member",
-  ]
-  asmflags = cflags
+  cflags = warn_config_cflags
+  asmflags = warn_config_asmflags
 }

 config("dialect_config") {
-  cflags_c = [ "-std=c99" ]
-  cflags_cc = [ "-std=c++11" ]
+  cflags_c = dialect_config_cflags
+  cflags_cc = dialect_config_ccflags
+  asmflags = dialect_config_asmflags
 }

 config("misc_config") {
-  defines = [ "__LITEOS__" ]
-  defines += [ "__LITEOS_M__" ]
+  defines = []
+  if (!defined(LOSCFG_COMPILER_ICCARM)) {
+    defines += [ "__LITEOS__" ]
+    defines += [ "__LITEOS_M__" ]
+  }
  if (!defined(LOSCFG_DEBUG_VERSION)) {
    defines += [ "NDEBUG" ]
  }
-
-  cflags = [
-    "-fno-pic",
-    "-fno-builtin",
-    "-fms-extensions",
-    "-fno-strict-aliasing",
-    "-fno-common",
-    "-fsigned-char",
-    "-ffunction-sections",
-    "-fdata-sections",
-    "-fno-exceptions",
-    "-fno-omit-frame-pointer",
-  ]
-
-  if (!defined(LOSCFG_COMPILER_CLANG_LLVM)) {
-    cflags += [ "-fno-aggressive-loop-optimizations" ]
-  }
-
-  asmflags = cflags
-  asmflags += [ "-DCLZ=CLZ" ]
+  cflags = misc_config_cflags
+  asmflags = misc_config_asmflags
 }

 config("los_config") {
@@ -208,8 +121,11 @@ config("los_config") {
 cmd = "if [ -f $device_path/BUILD.gn ]; then echo true; else echo false; fi"
 HAVE_DEVICE_SDK = exec_script("//build/lite/run_shell_cmd.py", [ cmd ], "value")

-# board and soc decoupling feature, device_path should contains board
-BOARD_SOC_FEATURE = device_path != string_replace(device_path, "/board/", "")
+# If device_path points to vendor, use device_path directly,
+# otherwise board is decoupled from soc, device_path should contain board
+BOARD_SOC_FEATURE =
+    device_path == string_replace(device_path, "/vendor/", "") &&
+    device_path != string_replace(device_path, "/board/", "")

 config("public") {
  configs = [
@@ -257,7 +173,11 @@ not_needed([ "HAVE_DEVICE_SDK" ])

 static_library("libkernel") {
  deps = [ ":modules" ]
-  complete_static_lib = false
+  if (defined(LOSCFG_COMPILER_ICCARM)) {
+    complete_static_lib = true
+  } else {
+    complete_static_lib = false
+  }
 }

 group("kernel") {
@@ -273,11 +193,7 @@ executable("liteos") {
    ":los_config",
  ]

-  ldflags = [
-    "-static",
-    "-Wl,--gc-sections",
-    "-Wl,-Map=$liteos_name.map",
-  ]
+  ldflags = executable_config_ldflags

  output_dir = target_out_dir

@@ -298,11 +214,5 @@ build_ext_component("build_kernel_image") {
  deps = [ ":copy_liteos" ]
  exec_path = rebase_path(root_out_dir)

-  objcopy = "${compile_prefix}objcopy$toolchain_cmd_suffix"
-  objdump = "${compile_prefix}objdump$toolchain_cmd_suffix"
-
-  command = "$objcopy -O binary $liteos_name $liteos_name.bin"
-  command +=
-      " && sh -c '$objdump -t $liteos_name | sort >$liteos_name.sym.sorted'"
-  command += " && sh -c '$objdump -d $liteos_name >$liteos_name.asm'"
+  command = toochain_config_command
 }
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -0,0 +1,465 @@
+#  (2022-03-30)
+
+
+### Bug Fixes
+
+* c-sky等芯片架构的BUILD.gn优化 ([3311d73](https://gitee.com/openharmony/kernel_liteos_m/commits/3311d73406b68d289b6f715a099e90f62c86abd1)), closes [#I4D129](https://gitee.com/openharmony/kernel_liteos_m/issues/I4D129)
+* change the sensitive words ([8e2248c](https://gitee.com/openharmony/kernel_liteos_m/commits/8e2248c062aaca2444cc1001873fe8e8d8cdd3c6)), closes [#I4K7](https://gitee.com/openharmony/kernel_liteos_m/issues/I4K7)
+* cortex-m55栈优化 ([59e9c6e](https://gitee.com/openharmony/kernel_liteos_m/commits/59e9c6ed73caeeed56081a768198eccc7448df6c)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* csky等新增模块的HalTickStart函数定义和实现不一致 ([07ab6a5](https://gitee.com/openharmony/kernel_liteos_m/commits/07ab6a5b77c6955f6093beeab976bdc1b32d1db9)), closes [#I4D1](https://gitee.com/openharmony/kernel_liteos_m/issues/I4D1)
+* FD_SETSIZE compatible newlibc ([82c6d5f](https://gitee.com/openharmony/kernel_liteos_m/commits/82c6d5f17478fb47ea5977a32fb76d783ee3e815))
+* fix compile warning saying dereference void * pointer ([29126a9](https://gitee.com/openharmony/kernel_liteos_m/commits/29126a98fe7a8f75695910bdf8fa1ccc6ff67288))
+* gcc编译testsuite编译问题修复 ([f7d26b8](https://gitee.com/openharmony/kernel_liteos_m/commits/f7d26b8e12fb1ba4bebe6c0fc9ca9e392537419f)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* Kconfig中打开littlefs选项默认关联打开LOSCFG_SUPPORT_LITTLEFS宏 ([b2bcab3](https://gitee.com/openharmony/kernel_liteos_m/commits/b2bcab3a5bd794c86dd4d93b1b5aeca2d097289b)), closes [#I4ENQ1](https://gitee.com/openharmony/kernel_liteos_m/issues/I4ENQ1)
+* kernel接口融合，添加/修改kernel函数 ([cee9714](https://gitee.com/openharmony/kernel_liteos_m/commits/cee9714a90f2660a0b4455f4f5a2fc42870a6aa5))
+* L0 pthread_cond_timedwait接口实现存在的几个问题 ([2219c32](https://gitee.com/openharmony/kernel_liteos_m/commits/2219c32784071b6c37ea57185382e3228ed4b0a7)), closes [#I4N9P8](https://gitee.com/openharmony/kernel_liteos_m/issues/I4N9P8)
+* liteos_kernel_only=true编译内核报错 ([adc2105](https://gitee.com/openharmony/kernel_liteos_m/commits/adc21052b2b9b55de9fc493cf74645f470edf9b5)), closes [#I4O204](https://gitee.com/openharmony/kernel_liteos_m/issues/I4O204)
+* los_exc.S中_ExcInMsp主栈中异常处理函数中异常返回类型错误 ([c51df7a](https://gitee.com/openharmony/kernel_liteos_m/commits/c51df7a94c1f21803db25f46a73a7fb291588eda)), closes [#I4EJI4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4EJI4)
+* los_interrupt.c存在未使用的参数编译出错 ([5af4c2e](https://gitee.com/openharmony/kernel_liteos_m/commits/5af4c2e2139cabe49049283f7a4280460bbf353a)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* LOS_Panic接口中增加需要增加LOS_BackTrace()，方便定位主动异常位置 ([f51d675](https://gitee.com/openharmony/kernel_liteos_m/commits/f51d675fee217e0ad519f2fa79f70b033f313dce)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* los_trace.h接口注释错误修正 ([693468e](https://gitee.com/openharmony/kernel_liteos_m/commits/693468e5274af310721f5962602a915d701a7bf0)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* m4核在任务中异常时backtrace使用的是MSP所在的栈，而不是PSP所在的栈 ([3e8aea2](https://gitee.com/openharmony/kernel_liteos_m/commits/3e8aea224e481322efef9397e4aafc3450a09d28)), closes [#I4D7](https://gitee.com/openharmony/kernel_liteos_m/issues/I4D7)
+* M核posix接口fs模块用例完善 ([ee380fb](https://gitee.com/openharmony/kernel_liteos_m/commits/ee380fb9be45ef033979ec3b8875d980b7f13198)), closes [#I4L7](https://gitee.com/openharmony/kernel_liteos_m/issues/I4L7)
+* optimize default configuration ([b2e3849](https://gitee.com/openharmony/kernel_liteos_m/commits/b2e3849bfbd470981602b0dc02f47bffb38bfe11)), closes [#I4FSC9](https://gitee.com/openharmony/kernel_liteos_m/issues/I4FSC9)
+* OsGetAllTskInfo调用和异常时无任务回调函数地址 ([1c605a3](https://gitee.com/openharmony/kernel_liteos_m/commits/1c605a338ad2317aeb464bdac85df5b9a79c99fd)), closes [#I4MG2](https://gitee.com/openharmony/kernel_liteos_m/issues/I4MG2)
+* pm codex告警清零 ([9666380](https://gitee.com/openharmony/kernel_liteos_m/commits/96663805ecfd3248e33b4deb877c8d55cc4e8eec)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* pm模块解冻线程时存在删除空链表且时间片频繁唤醒系统 ([9f185b5](https://gitee.com/openharmony/kernel_liteos_m/commits/9f185b5b52ed9506a4913f233c9ddfe45452ec05)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* **posix unittest:** posix unittest 融合 ([ad6f249](https://gitee.com/openharmony/kernel_liteos_m/commits/ad6f249d1ea878f06864d79bdbed772b21eeac49))
+* **posix:** posix兼容回退 ([207efc1](https://gitee.com/openharmony/kernel_liteos_m/commits/207efc15b859fe18d8b1dac2a3da9d7a5831aa6e))
+* **posix:** posix接口融合，接口规范兼容性修改 ([e0b1275](https://gitee.com/openharmony/kernel_liteos_m/commits/e0b12758da4a25e42110ba32da25b6d18ebed8ef))
+* **posix接口融合:** posix接口融合，接口规范兼容性修改 ([4b607fd](https://gitee.com/openharmony/kernel_liteos_m/commits/4b607fd0740a5379cd373890482235845d782b62))
+* posix线程和LOS_TaskCreate任务不兼容，补齐接口防护，防止访问野指针 ([60805e1](https://gitee.com/openharmony/kernel_liteos_m/commits/60805e1a7c3736db86695ed86cd03cfaab70a427))
+* pr模板补充说明 ([7b86f69](https://gitee.com/openharmony/kernel_liteos_m/commits/7b86f69cc0ccd5512b69fd3a1181b3440747ddb2))
+* ReadMe中无对动态加载模块待加载的共享库的限制说明。 ([f86b971](https://gitee.com/openharmony/kernel_liteos_m/commits/f86b97180f97903bb2def271b7b11fc1ae1bf9bb)), closes [#I4ICK8](https://gitee.com/openharmony/kernel_liteos_m/issues/I4ICK8)
+* shell 输入不识别命令时内存泄漏 ([0245b1a](https://gitee.com/openharmony/kernel_liteos_m/commits/0245b1a7b24fd36d23f9602d0755b274581a84ce)), closes [#I4UR9](https://gitee.com/openharmony/kernel_liteos_m/issues/I4UR9)
+* **shell:** cat针对大文件无法工作 ([d518bad](https://gitee.com/openharmony/kernel_liteos_m/commits/d518bad0dc7dd9e3fbb45423a7db5cb8c1c922dc)), closes [#I4J4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4J4)
+* shell模块task命令踩内存问题修改 ([6ffd55d](https://gitee.com/openharmony/kernel_liteos_m/commits/6ffd55dcd07ce17b693a97bb678668f763480e4d)), closes [#I4A70](https://gitee.com/openharmony/kernel_liteos_m/issues/I4A70)
+* switch inet_addr to a function ([b30e913](https://gitee.com/openharmony/kernel_liteos_m/commits/b30e9139d5502acab8c36ae9a56d4cd640786c44)), closes [#I4G4I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4G4I4)
+* **testsuites:** cpup和测试套解耦 ([692651f](https://gitee.com/openharmony/kernel_liteos_m/commits/692651fe40f668f19b479186e52fea34d092b458))
+* tick timer时钟频率赋值修改为运行时赋值 ([ae02afc](https://gitee.com/openharmony/kernel_liteos_m/commits/ae02afc8504f64ff6bc09828f55e9602bcbcae56)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* tick中断处理时，无挂起任务时应更新当前运行任务的时间片, 并触发一次调度 ([ea12d40](https://gitee.com/openharmony/kernel_liteos_m/commits/ea12d40caf1301b4a7b6d60a2c599ceff4746c90)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* **time_func_test_01.c:** 修复testTimes测试单板配置LOSCFG_BASE_CORE_TICK_PER_SECOND = 1000的问题 ([5c982f1](https://gitee.com/openharmony/kernel_liteos_m/commits/5c982f1087f95174f2836c72648eab58adf37fd7))
+* 中断向量表对齐大小支持可配置 ([cf9c838](https://gitee.com/openharmony/kernel_liteos_m/commits/cf9c8387e3785d994aacf948b7c1b61324a3dd63)), closes [#I4M20](https://gitee.com/openharmony/kernel_liteos_m/issues/I4M20)
+* 优化trace buffer初始化，删除swtmr 桩中的无效参数 ([afbc9a5](https://gitee.com/openharmony/kernel_liteos_m/commits/afbc9a593b61461072556cb5531d90b30ce2e394)), closes [#I4DPR7](https://gitee.com/openharmony/kernel_liteos_m/issues/I4DPR7)
+* 优化低功耗流程 ([c6600d9](https://gitee.com/openharmony/kernel_liteos_m/commits/c6600d9dddb666f397ba659d47d64f334691af6b)), closes [#I46](https://gitee.com/openharmony/kernel_liteos_m/issues/I46)
+* 修复arch目录调整影响到的target目录下的文件 ([d5725b2](https://gitee.com/openharmony/kernel_liteos_m/commits/d5725b22644da8ab3e719169230303e44c7d8750)), closes [#I4JM7](https://gitee.com/openharmony/kernel_liteos_m/issues/I4JM7)
+* 修复cortex-m系列系统提供的timer在低频下时间不准的问题 ([3e569ba](https://gitee.com/openharmony/kernel_liteos_m/commits/3e569bac587d90dcd21aff7d8ec53216dfbb8f1c)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 修复hook层LOS_HOOK_TYPE_SEM_PEND的runningTask入参可能为空 ([3fd22ac](https://gitee.com/openharmony/kernel_liteos_m/commits/3fd22ac2b0b4c690669a659246aba099fd4311ec)), closes [#I4BU4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4BU4)
+* 修复irqNum = HwiNumGet()编译错误的问题 ([16e87d7](https://gitee.com/openharmony/kernel_liteos_m/commits/16e87d78d89bec7d85c076fc738ed4ad0614b865)), closes [#I4S81](https://gitee.com/openharmony/kernel_liteos_m/issues/I4S81)
+* 修复Kconfig信息错误 ([bb04582](https://gitee.com/openharmony/kernel_liteos_m/commits/bb045829104211522cd12a7273d5853400c1ea26)), closes [#I4MZ1](https://gitee.com/openharmony/kernel_liteos_m/issues/I4MZ1)
+* 修复L0_Emulator 门禁高概率失败的问题 ([7ad2f62](https://gitee.com/openharmony/kernel_liteos_m/commits/7ad2f62a03481a3919fef1f1e46e4c9677b1e65c)), closes [#I4NB0](https://gitee.com/openharmony/kernel_liteos_m/issues/I4NB0)
+* 修复liteos-m在iar环境下的编译问题 ([4c4784e](https://gitee.com/openharmony/kernel_liteos_m/commits/4c4784e33d7944e7850009be192375aaa6e2b125)), closes [#I4Q5Q5](https://gitee.com/openharmony/kernel_liteos_m/issues/I4Q5Q5)
+* 修复los_interrupt.c文件中HalHwiInit函数里未使能未对齐异常问题 ([d32e25f](https://gitee.com/openharmony/kernel_liteos_m/commits/d32e25f3ae8e8e5ec24effa98dc8f0b3ba94d0c1)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 修复newlib缺省PTHREAD_KEYS_MAX 问题 ([65f04bf](https://gitee.com/openharmony/kernel_liteos_m/commits/65f04bf093376a478e9585dadfc1238158cc3641)), closes [#I4OX47](https://gitee.com/openharmony/kernel_liteos_m/issues/I4OX47)
+* 修复OsQueueMailFree提早释放内存的问题 ([ec88d16](https://gitee.com/openharmony/kernel_liteos_m/commits/ec88d1628937b3def6dd613246116f6bfa4141eb))
+* 修复pm编译告警导致内核编译失败 ([18b0524](https://gitee.com/openharmony/kernel_liteos_m/commits/18b052458e1cea113df7a6bb4798a6d5e1eb751e)), closes [#I49](https://gitee.com/openharmony/kernel_liteos_m/issues/I49)
+* 修复pthread 编译告警 ([cc57f81](https://gitee.com/openharmony/kernel_liteos_m/commits/cc57f81ab85a5eb9bb4be9bd7d2863978996bcf3)), closes [#I4U16](https://gitee.com/openharmony/kernel_liteos_m/issues/I4U16)
+* 修复pthread_create相关问题 ([cd949dd](https://gitee.com/openharmony/kernel_liteos_m/commits/cd949ddae0aa4e7291b0b7f6ba83c2034cdf1301)), closes [#I4P78](https://gitee.com/openharmony/kernel_liteos_m/issues/I4P78)
+* 修复pthread_create行为与posix不一致问题 ([2b1e5a7](https://gitee.com/openharmony/kernel_liteos_m/commits/2b1e5a7a130fbca1b86a787b54f474e183541d6d)), closes [#I49W9](https://gitee.com/openharmony/kernel_liteos_m/issues/I49W9)
+* 修复readme中文档链接错误 ([8ee70a0](https://gitee.com/openharmony/kernel_liteos_m/commits/8ee70a0f8f856da29139a36ba6f8589201cdb109)), closes [#I4FD5](https://gitee.com/openharmony/kernel_liteos_m/issues/I4FD5)
+* 修复risc-v异常时，异常信息混乱且backtrace无法输出的问题 ([0fb49d4](https://gitee.com/openharmony/kernel_liteos_m/commits/0fb49d4422245e83c2435468eb7f2690f2e2c6e4)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 修复shcmd.h需要用宏包起来的问题 ([a7a8a62](https://gitee.com/openharmony/kernel_liteos_m/commits/a7a8a62bcb7398b4194b37f62098da9cb1ce717e)), closes [#I45FU2](https://gitee.com/openharmony/kernel_liteos_m/issues/I45FU2)
+* 修复shell 模块存在大量的编译告警及codeCheck。 ([e0d8b53](https://gitee.com/openharmony/kernel_liteos_m/commits/e0d8b5328f53dcef9427a34e8b0462250bb6a40f)), closes [#I48V2](https://gitee.com/openharmony/kernel_liteos_m/issues/I48V2)
+* 修复任务栈对齐问题及补充posix和cmsis测试用例 ([ed863e9](https://gitee.com/openharmony/kernel_liteos_m/commits/ed863e90dd9aceb5d3b6d92b0a94703101b83f80))
+* 修复公版gcc编译内核，调用calloc崩溃 ([8d0ced2](https://gitee.com/openharmony/kernel_liteos_m/commits/8d0ced206951f35d5caab61969344b0ab259e5fb)), closes [#I4OFG6](https://gitee.com/openharmony/kernel_liteos_m/issues/I4OFG6)
+* 修复未使用的参数和类型比较编译报错问题 ([21b46e8](https://gitee.com/openharmony/kernel_liteos_m/commits/21b46e82f31030703d052369701f4d6d736a4a86))
+* 修复调度时间最大值不一致问题 ([9f393bc](https://gitee.com/openharmony/kernel_liteos_m/commits/9f393bcc6df592efb6940e9864ff93e932ae59ad))
+* 修正liteos-m内核README不准确信息 ([0e067b2](https://gitee.com/openharmony/kernel_liteos_m/commits/0e067b239354c28e16b05489274b33051d002508)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 修正部分编码风格问题 ([91903a3](https://gitee.com/openharmony/kernel_liteos_m/commits/91903a37165ef364750916104be4f7dfd1d8f9a6)), closes [#I4K8M7](https://gitee.com/openharmony/kernel_liteos_m/issues/I4K8M7)
+* 内核ERR打印，线程信息，不方便问题定位。 ([232fec2](https://gitee.com/openharmony/kernel_liteos_m/commits/232fec27ac8cd2f46b5a2f5cfbe4677d0e287314)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 内源检视问题修复 ([c24363b](https://gitee.com/openharmony/kernel_liteos_m/commits/c24363bc50364b0be1fba3b993a83c6936fc3d08))
+* 删除C文件中无用的__cplusplus ([7fe3aad](https://gitee.com/openharmony/kernel_liteos_m/commits/7fe3aaddf56b300ffcb2b186ae01ed64bef1c069)), closes [#I4D0](https://gitee.com/openharmony/kernel_liteos_m/issues/I4D0)
+* 删除OsMemboxExcInfoGetSub内存调测方法中多余的赋值语句。 ([94db0fe](https://gitee.com/openharmony/kernel_liteos_m/commits/94db0fe7a30edaa10786101f1ef662987a27734a)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 去掉没有使用的入参consoleid。 ([a627953](https://gitee.com/openharmony/kernel_liteos_m/commits/a62795304da31e13021ea2c675d124afd2594102)), closes [#I43](https://gitee.com/openharmony/kernel_liteos_m/issues/I43)
+* 去掉编译选项-fno-short-enums ([b542aab](https://gitee.com/openharmony/kernel_liteos_m/commits/b542aab09dd92397f8c1305ac656ef14a012b5f8)), closes [#I4JY32](https://gitee.com/openharmony/kernel_liteos_m/issues/I4JY32)
+* 取消cpu进入低功耗前开中断操作 ([bd39e9e](https://gitee.com/openharmony/kernel_liteos_m/commits/bd39e9e6d67310222c363e132141bb7fee1213f1)), closes [#I4KDP8](https://gitee.com/openharmony/kernel_liteos_m/issues/I4KDP8)
+* 告警修复 ([7d2fd01](https://gitee.com/openharmony/kernel_liteos_m/commits/7d2fd01c2d7d6d4c653a307a1419bc094f5332f0))
+* 告警修复 ([2d7bf3b](https://gitee.com/openharmony/kernel_liteos_m/commits/2d7bf3b7d8ea84961e802c366899aca891f38377))
+* 在头文件中补充LOSCFG_MEM_FREE_BY_TASKID函数的声明 ([ad18026](https://gitee.com/openharmony/kernel_liteos_m/commits/ad18026a59fc2853c9580e040f959f9f42082640)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 将curl依赖的函数新增至newlib库 ([bd04d9f](https://gitee.com/openharmony/kernel_liteos_m/commits/bd04d9f29a0b77445a71378f88b01ffdae24554f)), closes [#I4RG71](https://gitee.com/openharmony/kernel_liteos_m/issues/I4RG71)
+* 将未定义小写"true"，"false"改为"TRUE"，"FALSE"。 ([9819eb5](https://gitee.com/openharmony/kernel_liteos_m/commits/9819eb567636adf1774de9fd6039d274bee8f69b)), closes [#I43D20](https://gitee.com/openharmony/kernel_liteos_m/issues/I43D20)
+* 当前仓代码编译告警的问题 ([194ac58](https://gitee.com/openharmony/kernel_liteos_m/commits/194ac5898d1e2ffaa17f6dca405614b73da6f8bb)), closes [#I4N50](https://gitee.com/openharmony/kernel_liteos_m/issues/I4N50)
+* 支持硬浮点编译 ([988fd85](https://gitee.com/openharmony/kernel_liteos_m/commits/988fd85fae454a0d9fe01ef1c921b4f3667d5ac8)), closes [#I48](https://gitee.com/openharmony/kernel_liteos_m/issues/I48)
+* 测试用例任务栈的宏定义重复定义，导致在osTest.h中修改不生效 ([ce6cf68](https://gitee.com/openharmony/kernel_liteos_m/commits/ce6cf6879f4564393765a24c4d65448e0fddc3eb)), closes [#I4BA5](https://gitee.com/openharmony/kernel_liteos_m/issues/I4BA5)
+* 添加L0 测试门禁 ([5c168fc](https://gitee.com/openharmony/kernel_liteos_m/commits/5c168fc3e0d08dd4a8924696e17a498eb444fa70)), closes [#I4C5R4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4C5R4)
+* 添加newlib对ipv6的支持 ([f7400fb](https://gitee.com/openharmony/kernel_liteos_m/commits/f7400fbcb275cbb3b75f1aef2af1459b794432de)), closes [#I4M1](https://gitee.com/openharmony/kernel_liteos_m/issues/I4M1)
+* 添加文件版权头等信息 ([cf4e017](https://gitee.com/openharmony/kernel_liteos_m/commits/cf4e017970f8a3113bc8b6028d75775f747512c6)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 清除因g_tm变量没有使用引入的编译告警 ([9689522](https://gitee.com/openharmony/kernel_liteos_m/commits/9689522a8e08b79244ad339dc24074843b99d33b)), closes [#I4LW3](https://gitee.com/openharmony/kernel_liteos_m/issues/I4LW3)
+* 移除los_arch_interrupt.h文件中冗余声明的函数VOID OsExcInit(VOID) ([136952f](https://gitee.com/openharmony/kernel_liteos_m/commits/136952f193fe97cfd6a88932e71811e12edfa7a5)), closes [#I4D9](https://gitee.com/openharmony/kernel_liteos_m/issues/I4D9)
+* 补充net相关头文件 ([93f616b](https://gitee.com/openharmony/kernel_liteos_m/commits/93f616b64e961013be5c5267e50d58a40b5cc6c9))
+* 解决gmtime和localtime接口由于g_tm全局变量导致的竞态问题 ([1454b76](https://gitee.com/openharmony/kernel_liteos_m/commits/1454b76482d42e78c1904028de55d82261e5ecaa)), closes [#I4LW3](https://gitee.com/openharmony/kernel_liteos_m/issues/I4LW3)
+* 解决los_pm.c:743:19: warning 编译告警 ([0c72c8b](https://gitee.com/openharmony/kernel_liteos_m/commits/0c72c8bf94b053ff90bbf2019006c52adf1eb8df)), closes [#I4D4L8](https://gitee.com/openharmony/kernel_liteos_m/issues/I4D4L8)
+* 解决定时器超时但还在队列中无法删除的问题 ([ecce17e](https://gitee.com/openharmony/kernel_liteos_m/commits/ecce17ea4878c7bdf7d7de9a6848e6bf871563de)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 解除net对cmsis的依赖，net属于内核模块，不应该依赖内核对外接口 ([9982624](https://gitee.com/openharmony/kernel_liteos_m/commits/99826240d979c3aa820ab2aace62e3338978e6d1))
+* 调度中将pm相关的部分用LOSCFG_KERNEL_PM包含 ([d7c0059](https://gitee.com/openharmony/kernel_liteos_m/commits/d7c0059dc4fcca3f85d2cad1012353892ce28021)), closes [#I4L00](https://gitee.com/openharmony/kernel_liteos_m/issues/I4L00)
+* 调用LOS_TaskDetach操作已退出的joinable的任务时，未正确回收该任务 ([49c93b3](https://gitee.com/openharmony/kernel_liteos_m/commits/49c93b37c5e215612bbeb4619e73c809f9eb1cac)), closes [#I4DZL7](https://gitee.com/openharmony/kernel_liteos_m/issues/I4DZL7)
+* 针对pr是否同步至release分支，增加原因说明规则 ([1ee543d](https://gitee.com/openharmony/kernel_liteos_m/commits/1ee543d5d31524d543ffb297b121224dedf8602f))
+* 队列相关的API实现中,参数的校验不完全,导致程序异常 ([eef7c80](https://gitee.com/openharmony/kernel_liteos_m/commits/eef7c80a725d68af254ae55091bd36f978cf4284))
+
+
+### Features
+
+* adapt net ([8594ee4](https://gitee.com/openharmony/kernel_liteos_m/commits/8594ee469ad2d40a363e5d77f94f292ab3cb8c21))
+* add option for ioctl ([5e8ac4b](https://gitee.com/openharmony/kernel_liteos_m/commits/5e8ac4b8883f64bbffa5bb3f063a601112058396)), closes [#I4I3W5](https://gitee.com/openharmony/kernel_liteos_m/issues/I4I3W5)
+* add option SIOCGIFBRDADDR for ioctl ([33ee492](https://gitee.com/openharmony/kernel_liteos_m/commits/33ee49295329e3c394d1cc7b16f77a23ac2255a8)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* added assembly atomic interface ([1513f50](https://gitee.com/openharmony/kernel_liteos_m/commits/1513f50a474d1227a83fb655ad18c19cd792f235))
+* backtrace for arm9 ([03de7f3](https://gitee.com/openharmony/kernel_liteos_m/commits/03de7f37450a8821ea05e60e94a5d1dd359c4f99)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* Board 和 SoC分离，编译适配 ([3f1c04d](https://gitee.com/openharmony/kernel_liteos_m/commits/3f1c04dd57bca0379ce37162d9d824801e7d880f))
+* **build:** add module_group and comment out arch_cflags ([e5636f7](https://gitee.com/openharmony/kernel_liteos_m/commits/e5636f7acaf7e8b7d14dc07930b2a16c86e63c85))
+* **build:** support Kconfig ([7e67343](https://gitee.com/openharmony/kernel_liteos_m/commits/7e673430dc42c55b3a0a6d955ba8fea21d6d58ea))
+* **cmsis:** support max_count for osSemaphoreNew ([d478152](https://gitee.com/openharmony/kernel_liteos_m/commits/d478152762013975551e1af154df42987596c9a6))
+* cortex-m55支持psplimit ([db7d641](https://gitee.com/openharmony/kernel_liteos_m/commits/db7d641c223db8ab25501d79c2a6331f743d830b)), closes [#I4T7R3](https://gitee.com/openharmony/kernel_liteos_m/issues/I4T7R3)
+* littlefs最大打开文件个数修改为可通过menuconfig配置 ([9bc9f3a](https://gitee.com/openharmony/kernel_liteos_m/commits/9bc9f3aa53be7bf392d3da09adcb184dec8e3da2))
+* newlib支持pthread_equal ([ce5357e](https://gitee.com/openharmony/kernel_liteos_m/commits/ce5357eee1daf1c1b3a3aa7bdeaef0cc5a8901bf)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* provide read write for socket by #define ([d044eda](https://gitee.com/openharmony/kernel_liteos_m/commits/d044eda3c3640ae135ef528739d0c9609f40c822)), closes [#I4H8](https://gitee.com/openharmony/kernel_liteos_m/issues/I4H8)
+* synchronizing arch api ([04bf3a6](https://gitee.com/openharmony/kernel_liteos_m/commits/04bf3a682f149482d8ebdbb9ff96d6889edb487a)), closes [#I4N7](https://gitee.com/openharmony/kernel_liteos_m/issues/I4N7)
+* synchronous los_hwicreate interface ([6c68ada](https://gitee.com/openharmony/kernel_liteos_m/commits/6c68adad4db7f6112990764eafe6a3bd5f8759a5))
+* 低内存资源回收low memory killer ([ab886d8](https://gitee.com/openharmony/kernel_liteos_m/commits/ab886d848ab809942c11d0e408b8ff76c41b92b2)), closes [#I4ID0](https://gitee.com/openharmony/kernel_liteos_m/issues/I4ID0)
+* 低功耗支持冻结线程等需求 ([9b5739a](https://gitee.com/openharmony/kernel_liteos_m/commits/9b5739ab11ae7a89d35ba6f54fc62137ddc6d897)), closes [#I49](https://gitee.com/openharmony/kernel_liteos_m/issues/I49)
+* 内核提供Interrupt框架，支持多架构多平台通用化 ([e8538d0](https://gitee.com/openharmony/kernel_liteos_m/commits/e8538d041a93817cea4ae3914afcfdc6182483e7))
+* 内核提供tick timer框架，支持多架构多平台通用化 ([f635450](https://gitee.com/openharmony/kernel_liteos_m/commits/f635450d7cf7f674de3803b5eb9d759b6e4d005b)), closes [#I4N7](https://gitee.com/openharmony/kernel_liteos_m/issues/I4N7)
+* 同步调度部分优化至liteos_m ([fb11ab1](https://gitee.com/openharmony/kernel_liteos_m/commits/fb11ab181e69289f7a2edfd5857595b89f1d5d67))
+* 支持cortex-m55 ([6e17805](https://gitee.com/openharmony/kernel_liteos_m/commits/6e1780546c173365262c7a50b81896f5b3c46389)), closes [#I4Q9](https://gitee.com/openharmony/kernel_liteos_m/issues/I4Q9)
+* 支持Lms ([7b838e8](https://gitee.com/openharmony/kernel_liteos_m/commits/7b838e8a7b8e9f7fb34ca495e5cb46d70d12722b)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 支持posix 和 cmsis join能力 ([ecfdf7f](https://gitee.com/openharmony/kernel_liteos_m/commits/ecfdf7ff9bf1adf06835968dc6f06b7c45e04862)), closes [#I44V26](https://gitee.com/openharmony/kernel_liteos_m/issues/I44V26)
+* 支持posix线程私有数据能力 ([a856303](https://gitee.com/openharmony/kernel_liteos_m/commits/a856303b9cdadcfade33de0d3a335db0332f5761)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 支持pthread_condattr_setclock ([68dad2c](https://gitee.com/openharmony/kernel_liteos_m/commits/68dad2ccc9856dc2c1ac112bc8f30a703c1af5d9)), closes [#I4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4)
+* 支持pthread_mutex属性相关接口 ([d2be4d7](https://gitee.com/openharmony/kernel_liteos_m/commits/d2be4d7a460365844a7732df8a3eb59e6bb64897)), closes [#I4G4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4G4)
+* 支持select.h的FD_SETSIZE宏配置 ([05642f0](https://gitee.com/openharmony/kernel_liteos_m/commits/05642f05ae6b220df977f4402bc31f396bf08603)), closes [#I4RYK4](https://gitee.com/openharmony/kernel_liteos_m/issues/I4RYK4)
+* 支持任务栈可配置 ([96cc92d](https://gitee.com/openharmony/kernel_liteos_m/commits/96cc92d03561e1a9f1030c71916068584b349626))
+* 调度、任务及pm解耦 ([cc8a794](https://gitee.com/openharmony/kernel_liteos_m/commits/cc8a794229f4236a1611183fd482740b3badbcd7)), closes [#I4JTN6](https://gitee.com/openharmony/kernel_liteos_m/issues/I4JTN6)
+* 适配三方库FatFs升级至r0.14a版本 ([92ea355](https://gitee.com/openharmony/kernel_liteos_m/commits/92ea355756ebd92b8809ecb638ffb5355d89c5e9))
+
+
+### BREAKING CHANGES
+
+* pthread_create 支持任务栈设置
+osThreadNew 支持任务栈设置
+TSK_INIT_PARAM_S 结构体添加stackAddr 字段
+
+* 涉及接口修改：
+    LOS_HwiCreate LOS_HwiDelete
+
+改动内容：
+    中断处理函数参数类型由HWI_ARG_T统一改为HwiIrqParam，封装原有arg参数及riscv部分实际使用变量pDevId, 这样一方面统一LiteOS接口，也统一了中断处理函数的arg参数
+    同步LOS_HwiDelete接口入参，新增HWI_IRQ_PARAM_S *irqParam参数，为后续共享中断功能的添加预留
+
+* 新增接口：
+LOS_TaskResRecycle
+LOS_CurrNanosec
+LOS_MDelay
+
+接口修改：
+LOS_QueueCreate：第一个入参添加const修饰并增加一种异常情况处理
+los_memory.c中 OS_ERROR 修改为LOS_NOK，重定义LOS_NOK为（UINT32）-1。
+
+接口位置转移：
+LOS_UDelay 由los_task.h/.c 转移到los_tick.h/.c 
+
+宏修改：
+LOS_ERRNO_MUX_PEND_INTERR 改名为 LOS_ERRNO_MUX_IN_INTERR
+
+* **posix接口融合:**
+
+接口修改：
+calloc
+pthread_mutex_init
+mq_unlink
+pthread_join
+pthread_exit
+pthread_attr_init
+pthread_attr_destroy
+pthread_condattr_destroy
+pthread_cond_timedwait
+pthread_mutexattr_init
+pthread_mutexattr_settype
+pthread_mutex_destroy
+pthread_mutex_timedlock
+pthread_mutex_trylockk
+pthread_mutex_unlock
+sem_getvalue
+sem_timedwait
+pthread_cond_timedwait
+nanosleep
+timer_create
+timer_settime
+timer_gettime
+testStdlibStrtoull005
+testStdlibStrtol011
+testStdlibStrtoul007
+testPthread004
+
+新增接口：
+CheckForCancel
+pthread_setcancelstate
+pthread_setcanceltype
+pthread_once
+pthread_setschedprio
+pthread_attr_setstack
+pthread_attr_getstack
+pthread_condattr_getpshared
+pthread_condattr_setpshared
+pthread_condattr_getclock
+pthread_mutexattr_gettype
+CheckMutexAttr
+OsMuxPreCheck
+sem_trywait
+MuxPendForPosix
+MuxPostForPosix
+增加overrun功能
+
+接口变化：
+mq_getsetattr 改为内部接口MqGetSetAttr
+GetTickTimeFromNow->OsGetTickTimeFromNow
+
+接口位置转移：
+pthread_equal接口由newlib下转移到kal/posix/src/pthread.c中
+
+* **posix:** 接口修改：
+calloc
+pthread_mutex_init
+mq_unlink
+pthread_join
+pthread_exit
+pthread_attr_init
+pthread_attr_destroy
+pthread_condattr_destroy
+pthread_cond_timedwait
+pthread_mutexattr_init
+pthread_mutexattr_settype
+pthread_mutex_destroy
+pthread_mutex_timedlock
+pthread_mutex_trylockk
+pthread_mutex_unlock
+sem_getvalue
+
+新增接口：
+CheckForCancel
+pthread_setcancelstate
+pthread_setcanceltype
+pthread_once
+pthread_setschedprio
+pthread_attr_setstack
+pthread_attr_getstack
+pthread_condattr_getpshared
+pthread_condattr_setpshared
+pthread_condattr_getclock
+pthread_mutexattr_gettype
+CheckMutexAttr
+OsMuxPreCheck
+sem_trywait
+
+接口变化：
+mq_getsetattr 改为内部接口OsMqGetSetAttr
+
+接口位置转移：
+pthread_equal接口由newlib下转移到kal/posix/src/pthread.c中
+
+* 新增接口：
+    LOS_HwiTrigger ArchIntTrigger
+    LOS_HwiEnable ArchIntEnable
+    LOS_HwiDisable ArchIntDisable
+    LOS_HwiClear ArchIntClear
+    LOS_HwiSetPriority ArchIntSetPriority
+
+* Assembly implementation:
+    ArchAtomicRead
+    ArchAtomicSet
+    ArchAtomicAdd
+    ArchAtomicSub
+    ArchAtomicInc
+    ArchAtomicIncRet
+    ArchAtomicDec
+    ArchAtomicDecRet
+
+* 原来版本中每个架构下提供的tick timer相关操作函数为弱函数：
+    WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler);
+    WEAK VOID HalSysTickReload(UINT64 nextResponseTime);
+    WEAK UINT64 HalGetTickCycle(UINT32 *period);
+    WEAK VOID HalTickLock(VOID);
+    WEAK VOID HalTickUnlock(VOID);
+  用户如果需要启用自己的tick timer需要自己实现相关接口(强属性)，在 "内核初始化之前" 通过调用：
+  LOS_TickTimerRegister 接口替换系统默认提供的tick timer相关接口。
+  无论用户提供的tick timer 还是系统默认提供的，均在内核初始化时启动。
+*   int pthread_key_create(pthread_key_t *k, void (*dtor)(void *))
+  int pthread_key_delete(pthread_key_t k)
+  int pthread_setspecific(pthread_key_t k, const void *x)
+  void *pthread_getspecific(pthread_key_t k)
+* 1.修改arch/include下接口，以ArchXX命名函数
+2.提取公共函数声明:ArchAtomicXchg32bits、ArchAtomicDecRet、ArchAtomicCmpXchg32bits
+3.新增部分原子操作c内联实现
+* 增加低内存资源回收注册相关接口LOS_LmkOpsNodeRegister、LOS_LmkOpsNodeUnregister和内存资源释放和任务恢复接口LOS_LmkTasksKill和LOS_LmkTasksRestore.
+* SwtmrHandlerItem结构体新增swtmrID字段，用于标识超时队列中软件定时器id
+* 新增支持API:
+
+LOS_LmsCheckPoolAdd使能检测指定内存池
+LOS_LmsCheckPoolDel不检测指定内存池
+LOS_LmsAddrProtect为指定内存段上锁，不允许访问
+LOS_LmsAddrDisableProtect去能指定内存段的访问保护
+
+
+#  (2021-09-30)
+
+
+### Bug Fixes
+
+*  M核代码告警清零 ([cb5f862](https://gitee.com/openharmony/kernel_liteos_m/commits/cb5f862eafd91675bf53d0320616cc8f707a6e5a)), closes [#I4386](https://gitee.com/openharmony/kernel_liteos_m/issues/I4386)
+*  M核告警消除 ([5a9d53b](https://gitee.com/openharmony/kernel_liteos_m/commits/5a9d53b6444a3bbe084f575ef079f0da36c27c2a)), closes [#I46](https://gitee.com/openharmony/kernel_liteos_m/issues/I46)
+*  M核编译配置修改 ([deff7c9](https://gitee.com/openharmony/kernel_liteos_m/commits/deff7c921f606ed85663f91d21c12163c15aa7f8)), closes [#I46](https://gitee.com/openharmony/kernel_liteos_m/issues/I46)
+*  shell模块task命令踩内存问题修改 ([b5e84d5](https://gitee.com/openharmony/kernel_liteos_m/commits/b5e84d5516b599257151f88b5a830d6fe9e0e188)), closes [#II4](https://gitee.com/openharmony/kernel_liteos_m/issues/II4)
+*  trustzone 中断适配 ([15a2c17](https://gitee.com/openharmony/kernel_liteos_m/commits/15a2c17f791b7d6703863718d92fa35402c41067)), closes [#I42](https://gitee.com/openharmony/kernel_liteos_m/issues/I42)
+* add API LOS_HwiCreate and LOS_HwDelete ([eb668eb](https://gitee.com/openharmony/kernel_liteos_m/commits/eb668eb9e0021961230858f9bfa1599646da9a8f)), closes [#I3R75](https://gitee.com/openharmony/kernel_liteos_m/issues/I3R75)
+* add liteos_m vfs ([5479dd6](https://gitee.com/openharmony/kernel_liteos_m/commits/5479dd66d7ec96d2206a9890586fe5f07d50fbb9)), closes [#I3R493](https://gitee.com/openharmony/kernel_liteos_m/issues/I3R493)
+* backtrace代码段判断函数定义成弱函数，如果有多个代码段，那么可根据实际情况重定义 ([8692ed3](https://gitee.com/openharmony/kernel_liteos_m/commits/8692ed33a3b975bac7aa5b6ce3c40a84e281f6c5)), closes [#I420](https://gitee.com/openharmony/kernel_liteos_m/issues/I420)
+* change cpup retval range ([d00a35b](https://gitee.com/openharmony/kernel_liteos_m/commits/d00a35ba9288047e9eaba06a8ed1d15806bfca40))
+* change description according to review ([a38365e](https://gitee.com/openharmony/kernel_liteos_m/commits/a38365ed097fb398f922a5d1a72305933ae3e7b3))
+* change queuePosion to queuePosition ([e772ccb](https://gitee.com/openharmony/kernel_liteos_m/commits/e772ccb3ccd3b31269066fa59a434a23af98ce51))
+* change to OpenHarmony LiteOS-M ([259fb54](https://gitee.com/openharmony/kernel_liteos_m/commits/259fb54b3c1a208c5672f1f6551ba0424505e4b2))
+* comment error ([a37b73d](https://gitee.com/openharmony/kernel_liteos_m/commits/a37b73d7599a62a728dbf564de9d9927f995ec1b))
+* compile warning fix ([8dea15c](https://gitee.com/openharmony/kernel_liteos_m/commits/8dea15c4fcaff2957c60351781180f964c0a882d)), closes [#I4330](https://gitee.com/openharmony/kernel_liteos_m/issues/I4330)
+* compile warnings ([75f6187](https://gitee.com/openharmony/kernel_liteos_m/commits/75f61870a002e238385bc9a7632d42b0b2488c9a)), closes [#I3Y57](https://gitee.com/openharmony/kernel_liteos_m/issues/I3Y57)
+* correct ECB in comment ([e2aeb1f](https://gitee.com/openharmony/kernel_liteos_m/commits/e2aeb1ff1d4cd54a752c9f6ef976ee8e353da620))
+* correct spelling ([dd5cefb](https://gitee.com/openharmony/kernel_liteos_m/commits/dd5cefb0dace4b7a7276c880e45d5520950e9844))
+* correct spelling ([e7ea50f](https://gitee.com/openharmony/kernel_liteos_m/commits/e7ea50f13142e34a9860e75be051538fe91e234e))
+* correct the counter of exception type ([bff6587](https://gitee.com/openharmony/kernel_liteos_m/commits/bff65877a281ac1cdcbefd325dcd3ad4933edac9))
+* correct typo ([3ceface](https://gitee.com/openharmony/kernel_liteos_m/commits/3ceface13e1c15d107bc3c8460c17b9dd4c95e26))
+* cpup funciton repair ([c842251](https://gitee.com/openharmony/kernel_liteos_m/commits/c842251bab7ea6365f2bee8ae880e6efb60f0c73))
+* delete unused symbols for default config ([7ad3a22](https://gitee.com/openharmony/kernel_liteos_m/commits/7ad3a22b4d62c8b00876ff338c4ce8d1e3f3cbe2)), closes [#I45HN3](https://gitee.com/openharmony/kernel_liteos_m/issues/I45HN3)
+* fix __cplusplus typo ([c3eb3e5](https://gitee.com/openharmony/kernel_liteos_m/commits/c3eb3e59e692371f67a4e21e4b38004195ce5e10))
+* fix backtrace check issue ([b6664e6](https://gitee.com/openharmony/kernel_liteos_m/commits/b6664e66f14d432b02101c883a53cb333dc4c195))
+* fix bad params def in HalTickStart ([4443b74](https://gitee.com/openharmony/kernel_liteos_m/commits/4443b74ea63d2e458af69723a7198bbbaeb856ea)), closes [#I48](https://gitee.com/openharmony/kernel_liteos_m/issues/I48)
+* fix comment typo issue ([0c2a675](https://gitee.com/openharmony/kernel_liteos_m/commits/0c2a675e2d163eaf05aff7df226404888d78ca37))
+* fix destroy typo ([4ba6259](https://gitee.com/openharmony/kernel_liteos_m/commits/4ba6259e94bd677764922b0470fddc2590f6efa5))
+* fix function name ([f7d50d0](https://gitee.com/openharmony/kernel_liteos_m/commits/f7d50d0fbf53cdd352e94a387cf707083f1641bb))
+* fix length typo ([98d6580](https://gitee.com/openharmony/kernel_liteos_m/commits/98d65801de9e37199b5df9c8734ebcb6ff5d853d))
+* fix LOS_MEMBOX_ALIGNED macro name ([fced899](https://gitee.com/openharmony/kernel_liteos_m/commits/fced8992cf4fbc26c9722d528d642a7afe479170))
+* fix LOS_TaskNameGet comment ([c70b28b](https://gitee.com/openharmony/kernel_liteos_m/commits/c70b28bf785da12fd60ecc92a5a63fb54e52c22a))
+* fix macro typo ([1600360](https://gitee.com/openharmony/kernel_liteos_m/commits/16003604a948d081151ca4fcf0cfeea91c9e1960))
+* fix misspell in comments ([4572814](https://gitee.com/openharmony/kernel_liteos_m/commits/457281427ba286e24386d7916c4bc81f112f1c60))
+* fix NULL UNUSED redefined issue ([765bd55](https://gitee.com/openharmony/kernel_liteos_m/commits/765bd551990e906f457ec1145aea4f2bf5856547))
+* fix OS_TASK_STACK_PROTECT_SIZE undeclared error ([2a5a515](https://gitee.com/openharmony/kernel_liteos_m/commits/2a5a515f50a0f344d416218046bf0880facfb97c)), closes [#I4C5](https://gitee.com/openharmony/kernel_liteos_m/issues/I4C5)
+* fix print format compilation warning ([ef12c89](https://gitee.com/openharmony/kernel_liteos_m/commits/ef12c89c7a79791665125a0b7391f9e533a06a0f))
+* fix readme link issue ([9e332c6](https://gitee.com/openharmony/kernel_liteos_m/commits/9e332c69a5813027575786424b78f0ae2f9a4c5a))
+* fix some typo issues ([f6b8cab](https://gitee.com/openharmony/kernel_liteos_m/commits/f6b8cab2539e4d1ee9e47ab8e3eb12f1630f7393))
+* fix typo in comment ([811d3fa](https://gitee.com/openharmony/kernel_liteos_m/commits/811d3fae8a39686a1c66dfd61c897b7fd3fac2ac))
+* fix typos ([191644e](https://gitee.com/openharmony/kernel_liteos_m/commits/191644e4412fccb7142cfcd34316ad8e2d24fcdf))
+* Fixed a spelling error in FS_LOCK_TIMEOUT_SEC. ([42dc308](https://gitee.com/openharmony/kernel_liteos_m/commits/42dc3083693be13c5fa8f2ad8213245465e28adf)), closes [#I3TL66](https://gitee.com/openharmony/kernel_liteos_m/issues/I3TL66)
+* include file log_config.h in los_mpu.c ([1932d71](https://gitee.com/openharmony/kernel_liteos_m/commits/1932d714a589c9e87258d7c8ed647b6110bde543))
+* L0 GN compilation problem ([2f9bfcc](https://gitee.com/openharmony/kernel_liteos_m/commits/2f9bfcc6ee436ee3568d0c8158a8e43c9ef02623)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* l0 shell adapt new master ([fd2227e](https://gitee.com/openharmony/kernel_liteos_m/commits/fd2227e5c858c840f63629c27e559580e1cbdf2f))
+* littlefs inappropriate return value and errno ([452f364](https://gitee.com/openharmony/kernel_liteos_m/commits/452f36403dd4376572d8b52352d0d8129a4617e4)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* littlefs三方源码采用GN编译修改上库 ([bdb614b](https://gitee.com/openharmony/kernel_liteos_m/commits/bdb614bc2b82011d77c7c8ffb95e415d2640d19d))
+* LOS_QueueInfoGet函数统计等待读写任务有误 ([215a1f6](https://gitee.com/openharmony/kernel_liteos_m/commits/215a1f6dc06cf2348c5875f7b05193b26ec17dde)), closes [#I4C6P2](https://gitee.com/openharmony/kernel_liteos_m/issues/I4C6P2)
+* los_swtmr.h不满足自包含要求对los_config.h存在依赖，但未包含los_config.h ([ad8e96a](https://gitee.com/openharmony/kernel_liteos_m/commits/ad8e96a00f2fcaebe57feae4e3f23f99d7f1d066)), closes [#I40](https://gitee.com/openharmony/kernel_liteos_m/issues/I40)
+* **mbedtls:** mbedtls l0 support ([761b860](https://gitee.com/openharmony/kernel_liteos_m/commits/761b86096c3cf5642c95e556c11a45a3d5f413e4)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* misspell ([30578a6](https://gitee.com/openharmony/kernel_liteos_m/commits/30578a6a68a0d3a203b9a00e7bd1a946356d13d2))
+* modify event API description ([9481f1d](https://gitee.com/openharmony/kernel_liteos_m/commits/9481f1d8406960b8b859cc5a84b3831eadaf040c))
+* modify the return type of LOS_IntLock from UINTPTR to UINT32. ([bcc34e2](https://gitee.com/openharmony/kernel_liteos_m/commits/bcc34e22ede5aeccea63aba9f9ce3cb9aa92cbeb))
+* modify type INLNIE ([294a6d2](https://gitee.com/openharmony/kernel_liteos_m/commits/294a6d246b6a1f7cba8ce1bc4eeb9ae11f17a003))
+* Mutex锁释放后，无任务持有的情况下，owner未清空 ([c136cfd](https://gitee.com/openharmony/kernel_liteos_m/commits/c136cfdf973ae0068154606afa3a23858822c347)), closes [#I40OC8](https://gitee.com/openharmony/kernel_liteos_m/issues/I40OC8)
+* M核littlefs当文件open失败时，需要回收fd，否则会有fd泄露 ([b458e12](https://gitee.com/openharmony/kernel_liteos_m/commits/b458e12ed54905db6667f9d5db1410f94a3d6c71)), closes [#I3XU6](https://gitee.com/openharmony/kernel_liteos_m/issues/I3XU6)
+* m核上littlefs新增错误码功能 ([a062378](https://gitee.com/openharmony/kernel_liteos_m/commits/a06237863121816fa6421aed233446a3fa4e2665)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* net compile fix ([299813c](https://gitee.com/openharmony/kernel_liteos_m/commits/299813cdb43ae1e24200f0a6b006e04e4d4fcb05))
+* open shell & fix qemu compile ([911a767](https://gitee.com/openharmony/kernel_liteos_m/commits/911a767992ee540a96ee9f67e0b87195656c3eab))
+* ping cmd compile fail ([ae05de3](https://gitee.com/openharmony/kernel_liteos_m/commits/ae05de3ffda86d312d33b2e38f237dd76daf4949))
+* protect from accssing NULL pointer, access g_handle after fslock ([bc7a914](https://gitee.com/openharmony/kernel_liteos_m/commits/bc7a914bce1b227a4f57265d5ecc3f82d78533e7)), closes [#I3UCX3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3UCX3)
+* remove changelog in README ([37ef8ca](https://gitee.com/openharmony/kernel_liteos_m/commits/37ef8ca7ae73bf78f56dfef36c48bcd790afb6ff)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* remove libsec_kernel ([1144b75](https://gitee.com/openharmony/kernel_liteos_m/commits/1144b75f3ff9ce9e8fa114cf614d3deade8ac7c2))
+* remove project files ([4ad01ce](https://gitee.com/openharmony/kernel_liteos_m/commits/4ad01ced93684e5c7ba144ca267f8fcc2fe03105))
+* remove targets project files ([f39da5a](https://gitee.com/openharmony/kernel_liteos_m/commits/f39da5a6da59a3b1291c6b9ef7c50e6185df5ea1))
+* risc-v 锁中断在调度后失效 ([70f3aa1](https://gitee.com/openharmony/kernel_liteos_m/commits/70f3aa1c112e949d9af8e0245af5879140adefba)), closes [#I42](https://gitee.com/openharmony/kernel_liteos_m/issues/I42)
+* riscv_nuclei 编译失败 ([d3fb23c](https://gitee.com/openharmony/kernel_liteos_m/commits/d3fb23cca06580b6e447a9476a9c16643c4ea8fe)), closes [#I41](https://gitee.com/openharmony/kernel_liteos_m/issues/I41)
+* rollback resources when opendir failed ([82fad6c](https://gitee.com/openharmony/kernel_liteos_m/commits/82fad6c36f183de93d936dd2007b899c2932bcee)), closes [#I3Y577](https://gitee.com/openharmony/kernel_liteos_m/issues/I3Y577)
+* Scheduling module code to join GN compilation. ([8bf166b](https://gitee.com/openharmony/kernel_liteos_m/commits/8bf166b418ce1a6c027dc304d45fc9431923764c)), closes [#I3OA95](https://gitee.com/openharmony/kernel_liteos_m/issues/I3OA95)
+* The hook module fails to compile under the c99 compilation standard. ([a078c30](https://gitee.com/openharmony/kernel_liteos_m/commits/a078c3086fa47e05e3ffdc4e94ca202284a1487b)), closes [#I3S4](https://gitee.com/openharmony/kernel_liteos_m/issues/I3S4)
+* tick 动态化计算优化，减小中断执行时间对系统总体时间的影响，保证软件定时器的响应精度。 ([2118c84](https://gitee.com/openharmony/kernel_liteos_m/commits/2118c84616cce5b5d4569d5a82a4d5de02af1e1c)), closes [#I3YGP1](https://gitee.com/openharmony/kernel_liteos_m/issues/I3YGP1)
+* timer qemu 头文件缺失 ([12fed74](https://gitee.com/openharmony/kernel_liteos_m/commits/12fed747226c377c656b8acb8346154627845b6f))
+* update according to review comments ([4dc0d31](https://gitee.com/openharmony/kernel_liteos_m/commits/4dc0d313d1b4a39ebb62156d0bb6429ebb8b996d))
+* update arch_spec.md ([cf43988](https://gitee.com/openharmony/kernel_liteos_m/commits/cf439885234e0955bab09834b3b876d627c81605))
+* update doc usage ([5c19fd4](https://gitee.com/openharmony/kernel_liteos_m/commits/5c19fd4beca15a8b7faad847a13943a9abfe3c8c))
+* update document description ([954c2fc](https://gitee.com/openharmony/kernel_liteos_m/commits/954c2fcfb531d0da1dcc6354a0c0b14335566ed7))
+* update macro to config item ([be57ece](https://gitee.com/openharmony/kernel_liteos_m/commits/be57ece9ce6200c8868164bc0bb2f26e3062cd37))
+* 以g_sysSchedStartTime是否为0判断时间轴是否生效存在极限场景导致调度时间不生效 ([509cf59](https://gitee.com/openharmony/kernel_liteos_m/commits/509cf59befb40839a376be31958d615f066c66fd)), closes [#I45HP5](https://gitee.com/openharmony/kernel_liteos_m/issues/I45HP5)
+* 修复littlefs的多分区挂载时，对pathname的处理逻辑异常 ([b55cfc1](https://gitee.com/openharmony/kernel_liteos_m/commits/b55cfc1ba7fc470b876c555ac7d3be0aa1d3d363)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* 修复littlefs编译fs.c缺少头文件件依赖配置+若干musl库的缺失问题+多分区规格宏配置问题 ([7259289](https://gitee.com/openharmony/kernel_liteos_m/commits/7259289bd98a743f596060bc607f77ab8f149129)), closes [#I3VT11](https://gitee.com/openharmony/kernel_liteos_m/issues/I3VT11)
+* 修复M核littlefs GN编译的若干错误 ([d77828e](https://gitee.com/openharmony/kernel_liteos_m/commits/d77828e206f3324424c3b1372332828a0afb84c2))
+* 修复M核上musl库缺失strdup,c的问题 ([139f83a](https://gitee.com/openharmony/kernel_liteos_m/commits/139f83af391a4f5e64ab0fccbd783dd651b87e6a)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* 修复QUEUE_INFO_S中waitReadTask无法保存大于32的任务编号 ([704cca9](https://gitee.com/openharmony/kernel_liteos_m/commits/704cca97b17972d1640fd33b1fa0b5917bb92b19)), closes [#I41N78](https://gitee.com/openharmony/kernel_liteos_m/issues/I41N78)
+* 修复task命令格式错误，增加copyright ([ad15bbd](https://gitee.com/openharmony/kernel_liteos_m/commits/ad15bbd6a4d298aabc05b26d7838de6425dbc5c5))
+* 修复timer_settime只设置第一次到期时间时，到期时间不准的缺陷 ([a5f4e37](https://gitee.com/openharmony/kernel_liteos_m/commits/a5f4e37e535bff39a333c469e2f1bf1817216fe8)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* 修复timer_settime只设置第一次到期时间时，到期时间不准的缺陷 ([e4b5d4e](https://gitee.com/openharmony/kernel_liteos_m/commits/e4b5d4ebe9677d49d490fe74e5ac33c4a29435a2)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* 修复不规范的copyright ([2d9bbd2](https://gitee.com/openharmony/kernel_liteos_m/commits/2d9bbd2769e71e7b464bd22fc335999dd8000682)), closes [#I3SPJ1](https://gitee.com/openharmony/kernel_liteos_m/issues/I3SPJ1)
+* 修复中断操作接口头文件位置变更，导致的编译错误 ([013a953](https://gitee.com/openharmony/kernel_liteos_m/commits/013a953926ca7cefd8a2f7c74d23c36c49765b59)), closes [#I4665](https://gitee.com/openharmony/kernel_liteos_m/issues/I4665)
+* 修复文档链接失效问题 ([5d53c84](https://gitee.com/openharmony/kernel_liteos_m/commits/5d53c848124319a95f509b56ba001357c6dd8b05)), closes [#I4529](https://gitee.com/openharmony/kernel_liteos_m/issues/I4529)
+* 内核模块编译增加-Werror编译选项，且清除内核编译告警 ([3798091](https://gitee.com/openharmony/kernel_liteos_m/commits/3798091d87441ea445ec642de57e036dbbc8370e)), closes [#I46E6](https://gitee.com/openharmony/kernel_liteos_m/issues/I46E6)
+* 删除MQ内冗余的重复宏定义 ([6d72916](https://gitee.com/openharmony/kernel_liteos_m/commits/6d7291660ad04682f05850876f81dfd0cba8ea6b)), closes [#I3U5](https://gitee.com/openharmony/kernel_liteos_m/issues/I3U5)
+* 删除延时节点后，存在时间无法有效刷新的场景 ([0a87c04](https://gitee.com/openharmony/kernel_liteos_m/commits/0a87c04d58d11da2082470698de0760d72259533)), closes [#I45I9](https://gitee.com/openharmony/kernel_liteos_m/issues/I45I9)
+* 在内核初始化前期启动tick timer ([b3841ed](https://gitee.com/openharmony/kernel_liteos_m/commits/b3841ed1ddbfb3359c7a0ceca04fc0f645d440c3)), closes [#I410F0](https://gitee.com/openharmony/kernel_liteos_m/issues/I410F0)
+* 增加MPU功能的开关宏，默认关闭 ([9709d29](https://gitee.com/openharmony/kernel_liteos_m/commits/9709d29b87a3888412ffda586e16eba86adccfe7)), closes [#I3WE0](https://gitee.com/openharmony/kernel_liteos_m/issues/I3WE0)
+* 宏LOSCFG_SUPPORT_FATFS在fs.c中存在使用问题，导致无fatfs的情况下，编译出错 ([c1614ce](https://gitee.com/openharmony/kernel_liteos_m/commits/c1614ce2b4d4dfcda9532cbeeff25ad7a6558196)), closes [#I44](https://gitee.com/openharmony/kernel_liteos_m/issues/I44)
+* 延时队列为NULL时，返回的响应时间为64位最大值，导致无法更新tick timer的响应周期 ([bcec32e](https://gitee.com/openharmony/kernel_liteos_m/commits/bcec32e389634097102a203ee7e937ed3193c984)), closes [#I3W1](https://gitee.com/openharmony/kernel_liteos_m/issues/I3W1)
+* 支持smoke 测试用例 ([3ad5942](https://gitee.com/openharmony/kernel_liteos_m/commits/3ad5942301a1094a2c6b6ffee280cf09cfdb2a88)), closes [#I424](https://gitee.com/openharmony/kernel_liteos_m/issues/I424)
+* 新增函数regcomp,regfree和regexec支持 ([86d5544](https://gitee.com/openharmony/kernel_liteos_m/commits/86d5544a3fd5f41f7f2abe3b143e9f1dc9b430f8)), closes [#I3U9](https://gitee.com/openharmony/kernel_liteos_m/issues/I3U9)
+* 清理残留无效的trace代码 ([3c48951](https://gitee.com/openharmony/kernel_liteos_m/commits/3c489518576583ab6bf0d581810ef0a02b6ccd51)), closes [#I3ZMB4](https://gitee.com/openharmony/kernel_liteos_m/issues/I3ZMB4)
+* 解决arm9编译冲突问题 ([c1a6245](https://gitee.com/openharmony/kernel_liteos_m/commits/c1a624536887fef44fed37134638bf40191b9aae)), closes [#I420](https://gitee.com/openharmony/kernel_liteos_m/issues/I420)
+* 调度过程低概率触发OsSchedTaskEnQueue断言，导致系统异常 ([e5e9289](https://gitee.com/openharmony/kernel_liteos_m/commits/e5e9289a08cf1db71c09647b71a864f5a1f8a4a2)), closes [#I3VX9](https://gitee.com/openharmony/kernel_liteos_m/issues/I3VX9)
+* 调整hook类型和位置，方便调试 ([369320d](https://gitee.com/openharmony/kernel_liteos_m/commits/369320de3710486f252c55c522e8c06e19541b77)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+
+
+### Features
+
+* add cmsis ThreadFlags support ([cea551e](https://gitee.com/openharmony/kernel_liteos_m/commits/cea551e99ea0da8eefbaa826de2f68813252fb83))
+* add deps to musl and securec ([bfa25fc](https://gitee.com/openharmony/kernel_liteos_m/commits/bfa25fcaa355c28a6139f683c4453f677e23abd7))
+* add file type support for LfsStat ([ceaed2d](https://gitee.com/openharmony/kernel_liteos_m/commits/ceaed2dc86de2ed242aab4dd02c1f34e064583b3)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* add interface of dhcp_is_bound ([84a180d](https://gitee.com/openharmony/kernel_liteos_m/commits/84a180d585686cda693bf8c6ed6b86f7c5dd5eee)), closes [#I46W08](https://gitee.com/openharmony/kernel_liteos_m/issues/I46W08)
+* add L0 shell function ([97283b7](https://gitee.com/openharmony/kernel_liteos_m/commits/97283b7c5dd44b266e94fcf0f5d21e63ee1ec7e0))
+* add LOS_ListHeadInsert function ([430b186](https://gitee.com/openharmony/kernel_liteos_m/commits/430b186be7ec1554a29a6d509188eb877d796a7e)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* **kernel:** 补充获取最高、最低优先级接口 ([c24c38b](https://gitee.com/openharmony/kernel_liteos_m/commits/c24c38b084c13a2cdc5616f88bb5f63153600c28)), closes [#I42HM7](https://gitee.com/openharmony/kernel_liteos_m/issues/I42HM7)
+* L0 armquem 剥离工具链 ([67d7455](https://gitee.com/openharmony/kernel_liteos_m/commits/67d74559d1bb3820bd51da2e2bf43e41e1224314))
+* L0 支持Trace ([56c93a6](https://gitee.com/openharmony/kernel_liteos_m/commits/56c93a641b3c7a3d1ef9293ee3c95cccb559191f)), closes [#I41Y9](https://gitee.com/openharmony/kernel_liteos_m/issues/I41Y9)
+* L0 支持低功耗框架 ([558ce14](https://gitee.com/openharmony/kernel_liteos_m/commits/558ce14becab05102497afca90a43d89abaf5531)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* L0 测试用例支持risc-v qemu 编译运行 ([2dd6c08](https://gitee.com/openharmony/kernel_liteos_m/commits/2dd6c080daab52eaf61e5eefe7b581190670e8a7)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* **liteos_m:** support backtrace for riscv ([ca1792a](https://gitee.com/openharmony/kernel_liteos_m/commits/ca1792aa4b5a85ca4ea6e41b265858c6b24a6897)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* los_memory.c代码重复率处理 ([475db62](https://gitee.com/openharmony/kernel_liteos_m/commits/475db62db1ac285fc6cab91f09af618870269580)), closes [#I44](https://gitee.com/openharmony/kernel_liteos_m/issues/I44)
+* M33平台支持GCC环境的Trustzone ([d469da2](https://gitee.com/openharmony/kernel_liteos_m/commits/d469da29c6d316640eaa7865f98ad8d6e2eb6d44)), closes [#I3Y85](https://gitee.com/openharmony/kernel_liteos_m/issues/I3Y85)
+* provide getifaddrs for liteos_m ([948501a](https://gitee.com/openharmony/kernel_liteos_m/commits/948501ac73e7887f4585eca156ad760acc2a3b1f)), closes [#I400S5](https://gitee.com/openharmony/kernel_liteos_m/issues/I400S5)
+* risc-v gn 编译框架添加汇编编译选项 ([76dc343](https://gitee.com/openharmony/kernel_liteos_m/commits/76dc343c888ec4e65eba43feb49921111b144640)), closes [#I3YS5](https://gitee.com/openharmony/kernel_liteos_m/issues/I3YS5)
+* Support arm9 ([6d7c9df](https://gitee.com/openharmony/kernel_liteos_m/commits/6d7c9dfe597affb260e8bd74fa606b6d68c2b49a)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* Support arm9 fiq swi mode and using system mode. ([97b5b08](https://gitee.com/openharmony/kernel_liteos_m/commits/97b5b0837be4b8df1381af29a6f650f243322840)), closes [#I3](https://gitee.com/openharmony/kernel_liteos_m/issues/I3)
+* support non-continuous memory regions ([0facb0c](https://gitee.com/openharmony/kernel_liteos_m/commits/0facb0c0179f29a08b037655bbe691c98384dc84)), closes [#I43](https://gitee.com/openharmony/kernel_liteos_m/issues/I43)
+* 完善m核qemu串口驱动，支持shell输入 ([c4dc5ab](https://gitee.com/openharmony/kernel_liteos_m/commits/c4dc5ab0f8b5caae55efdbedf59ab07f5006f6c2)), closes [#I46N7](https://gitee.com/openharmony/kernel_liteos_m/issues/I46N7)
+* 按任务统计已经alloc的内存大小 ([53117f9](https://gitee.com/openharmony/kernel_liteos_m/commits/53117f9f47a8dd3023e83dc0cc0de224eab9719f)), closes [#I44](https://gitee.com/openharmony/kernel_liteos_m/issues/I44)
+* 支持native动态加载组件 ([d753834](https://gitee.com/openharmony/kernel_liteos_m/commits/d75383400efe5d9ca0ae4093e4f2e65fee03024b)), closes [#I418](https://gitee.com/openharmony/kernel_liteos_m/issues/I418)
+* 新增LOSCFG_BASE_CORE_TSK_SWITCH_HOOK 宏定义配置 ([39efd6f](https://gitee.com/openharmony/kernel_liteos_m/commits/39efd6fb30ee7dc9159811f5d37dffcdfe81bae0)), closes [#I40Q9](https://gitee.com/openharmony/kernel_liteos_m/issues/I40Q9)
+* 新增ROM/RAM分析工具 ([ee3403d](https://gitee.com/openharmony/kernel_liteos_m/commits/ee3403deaf24dc612b51354f31f795fb0b9a49b5))
+* 补充fs相关函数用例 ([2a95af5](https://gitee.com/openharmony/kernel_liteos_m/commits/2a95af5bf1b412de27b4518d0abf7c335366d4d7)), closes [#I3UQ4](https://gitee.com/openharmony/kernel_liteos_m/issues/I3UQ4)
+* 解决fclose等函数工具链重定义问题 ([b244ad4](https://gitee.com/openharmony/kernel_liteos_m/commits/b244ad4ad0da8d151b69071fdd6db808c91f85a5)), closes [#I3UG6](https://gitee.com/openharmony/kernel_liteos_m/issues/I3UG6)
+
+
+### BREAKING CHANGES
+
+* 新增4个对外接口，声明在los_dynlink.h文件中，分别为：
+(1) LOS_DynlinkInit: 动态加载模块初始化。
+(2) LOS_SoLoad: 加载指定路径的共享库。
+(3) LOS_FindSym: 根据共享库句柄查找指定符号。
+(4) LOS_SoUnload: 卸载共享库。
+* 1.新增一系列trace的对外API，位于los_trace.h中.
+LOS_TRACE_EASY简易插桩
+LOS_TRACE标准插桩
+LOS_TraceInit配置Trace缓冲区的地址和大小
+LOS_TraceStart开启事件记录
+LOS_TraceStop停止事件记录
+LOS_TraceRecordDump输出Trace缓冲区数据
+LOS_TraceRecordGet获取Trace缓冲区的首地址
+LOS_TraceReset清除Trace缓冲区中的事件
+LOS_TraceEventMaskSet设置事件掩码，仅记录某些模块的事件
+LOS_TraceHwiFilterHookReg注册过滤特定中断号事件的钩子函数
+* 1.原调度中基于tick timer的低功耗扩展和当前的pm模块合并，删除原对外接口LOS_SchedSleepInit,
+　变为pm模块统一提供的LOS_PmRegistered接口.
+2.原来在arch los_timer.h下提供的低功耗模式为枚举LOS_SysSleepEnum，其中OS_SYS_NORMAL_SLEEP
+  和OS_SYS_DEEP_SLEEP不符合对外定义，统一修改为LOS_SYS_NORMAL_SLEEP和LOS_SYS_DEEP_SLEEP,
+  并移至los_pm.h中.
+3.VOID HalEnterSleep(LOS_SysSleepEnum sleep) 变更为UINT32 HalEnterSleep(VOID).
+
+
+
--- a/40
+++ b/40
@@ -52,6 +52,9 @@ config LLVM_TARGET
    depends on COMPILER_CLANG_LLVM
    default "arm-liteos-ohos" if ARCH_ARM_AARCH32

+config COMPILER_ICCARM
+    bool "ICCARM"
+
 endchoice

 config COMPILE_DEBUG
@@ -332,6 +335,14 @@ config KERNEL_PM
      Configuration item for low power frame tailoring.
      If you wish to build LiteOS with support for power management.

+config KERNEL_PM_IDLE
+    bool "Enable Power Management Idle"
+    default n
+    depends on KERNEL_PM
+    help
+      Configuration item for low power frame tailoring.
+      If you wish to build LiteOS with support for power management idle.
+
 config KERNEL_PM_TASK_PTIORITY
    int "Power Management Task Priority"
    default 1
@@ -354,15 +365,10 @@ config KERNEL_PM_DEBUG
    help
      Configuration item for low power frame debug tailoring.

-config DEBUG_HOOK
-    bool
-    default n
-
 config PLATFORM_EXC
-    bool "Enable Hook Feature"
+    bool "Enable Platform Exc Hook"
    default n
    depends on KERNEL_EXTKERNEL
-    select DEBUG_HOOK

 config KERNEL_LMK
    bool "Enable Low Memory Killer"
@@ -515,6 +521,14 @@ config DEBUG_QUEUE
    help
      Answer Y to enable debug queue.

+config MUTEX_CREATE_TRACE
+    bool "Enable Mutex Trace Debugging"
+    default n
+    depends on ARCH_ARM
+    depends on DEBUG_KERNEL
+    help
+      Answer Y to enable debug mutex trace.
+
 config DEBUG_DEADLOCK
    bool "Enable Mutex Deadlock Debugging"
    default n
@@ -529,14 +543,20 @@ config DEBUG_SEMAPHORE
    help
      Answer Y to enable debug semaphore.

-source "components/shell/Kconfig"
 config NET_LWIP_SACK_TFTP
    bool "Enable Tftp"
    default y
    depends on SHELL && NET_LWIP_SACK && DEBUG_VERSION
    help
      Answer Y to enable LiteOS support tftp cmd and tftp tool.
-osource "net/telnet/Kconfig"
+
+config DEBUG_HOOK
+    bool "Enable Hook Framework"
+    default n
+    depends on DEBUG_VERSION
+    help
+      Enable the kernel hook framework to support customized trace information capture.
+
 config SCHED_DEBUG
    bool "Enable sched debug Feature"
    default n
@@ -597,12 +617,14 @@ config VM_OVERLAP_CHECK
    depends on DEBUG_VERSION && MEM_DEBUG
    help
      Answer Y to enable vm overlap check.
-      
+
 config TASK_MEM_USED
    bool "Enable show task mem used or not"
    default n
    depends on DEBUG_VERSION && MEM_DEBUG

+source "components/shell/Kconfig"
+
 endmenu

 ######################## config options os drivers ########################
--- a/README.md
+++ b/README.md
@@ -59,7 +59,6 @@ The directory structure is as follows. For more details, see [arch_spec.md](arch
 ├── kernel               # Minimum kernel function set
 │   ├── include          # APIs exposed externally
 │   └── src              # Source code of the minimum kernel function set
-├── targets              # Board-level projects
 ├── testsuites           # Kernel testsuites
 ├── tools                # Kernel tools
 ├── utils                # Common directory
@@ -107,12 +106,6 @@ The LiteOS-M kernel porting projects for specific development boards are provide

        This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the STM32F429IGTb development board. The code supports build in Ninja, GCC, and IAR modes.

-   Cortex-M7:
-
-    - Nucleo-F767ZI https://gitee.com/harylee/nucleo_f767zi
-
-        This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the Nucleo-F767ZI development board. The code supports build in Ninja, GCC, and IAR modes.
-
 ## Contribution<a name="section1371123476307"></a>

 [How to involve](https://gitee.com/openharmony/docs/blob/HEAD/en/contribute/contribution.md)
--- a/README_zh.md
+++ b/README_zh.md
@@ -11,7 +11,7 @@

 OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系统内核，具有小体积、低功耗、高性能的特点，其代码结构简单，主要包括内核最小功能集、内核抽象层、可选组件以及工程目录等，分为硬件相关层以及硬件无关层，硬件相关层提供统一的HAL（Hardware Abstraction Layer）接口，提升硬件易适配性，不同编译工具链和芯片架构的组合分类，满足AIoT类型丰富的硬件和编译工具链的拓展。其架构图如图1所示：

-**图 1**  OpenHarmony LiteOS-M核内核架构图<a name="fig0865152210223"></a>  
+**图 1**  OpenHarmony LiteOS-M核内核架构图<a name="fig0865152210223"></a>
 ![](figures/OpenHarmony-LiteOS-M核内核架构图.png "OpenHarmony-LiteOS-M核内核架构图")

 ## 目录<a name="section161941989596"></a>
@@ -57,7 +57,6 @@ OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系
 ├── kernel               # 内核最小功能集支持
 │   ├── include          # 对外接口存放目录
 │   └── src              # 内核最小功能集源码
-├── targets              # 板级工程目录
 ├── testsuites           # 内核测试用例
 ├── tools                # 内核工具
 ├── utils                # 通用公共目录
@@ -78,7 +77,7 @@ LiteOS-M内核的编译构建系统是一个基于gn和ninja的组件化构建

 ### 搭建系统基础环境

-在搭建各个开发板环境前，需要完成OpenHarmony系统基础环境搭建。系统基础环境主要是指OpenHarmony的编译环境和开发环境，详细介绍请参考官方站点[开发环境准备](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/quick-start/quickstart-lite-env-setup.md)。开发者需要根据环境搭建文档完成环境搭建。
+在搭建各个开发板环境前，需要完成OpenHarmony系统基础环境搭建。系统基础环境主要是指OpenHarmony的编译环境和开发环境，详细介绍请参考官方站点[开发环境准备](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/quick-start/Readme-CN.md)。开发者需要根据环境搭建文档完成环境搭建。

 ### 获取OpenHarmony源码

@@ -106,12 +105,6 @@ LiteOS-M内核移植的具体开发板的工程由社区开发者提供，可以

        该仓包含OpenHarmony LiteOS-M内核移植支持`野火挑战者STM32F429IGTb`开发板的工程代码，支持Ninja、GCC、IAR等方式进行编译。

-   cortex-m7：
-
-    - Nucleo-F767ZI   https://gitee.com/harylee/nucleo_f767zi
-
-        该仓包含OpenHarmony LiteOS-M内核移植支持`Nucleo-F767ZI`开发板的工程代码，支持Ninja、GCC、IAR等方式进行编译。
-
 ## 贡献<a name="section1371123476307"></a>

 [如何贡献](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/contribute/%E5%8F%82%E4%B8%8E%E8%B4%A1%E7%8C%AE.md)
--- a/arch/BUILD.gn
+++ b/arch/BUILD.gn
@@ -43,7 +43,7 @@ module_group("arch") {
             "$board_cpu" == "ck804ef") {
    modules += [ "csky" ]
  } else if ("$board_cpu" == "") {
-    if ("$board_arch" == "rv32imac" || "$board_arch" == "rv32imafdc") {
+    if ("$board_arch" != string_replace("$board_arch", "rv32i", "")) {
      modules += [ "risc-v" ]
    } else if ("$board" == "esp32") {
      modules += [ "xtensa" ]
--- a/arch/arm/BUILD.gn
+++ b/arch/arm/BUILD.gn
@@ -1,5 +1,5 @@
 # Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
-# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without modification,
 # are permitted provided that the following conditions are met:
@@ -34,6 +34,10 @@ config("arm_config") {
 }

 module_group("arm") {
-  modules = [ "$board_cpu/gcc" ]
+  if (defined(LOSCFG_COMPILER_ICCARM)) {
+    modules = [ "$board_cpu/iar" ]
+  } else {
+    modules = [ "$board_cpu/gcc" ]
+  }
  configs = [ ":arm_config" ]
 }
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -31,43 +31,61 @@ config ARCH_ARM_VER
 #
 # VFP Hardware
 #
-config ARCH_FPU_VFP_V3
-    bool
-    help
-      An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
-      VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support code.
+choice
+    prompt "Choose FPU type"
+    depends on !ARCH_FPU_DISABLE

-config ARCH_FPU_VFP_V4
-    bool
-    help
-      An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
-      VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support code.
-      VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to the features of VFPv3.
+    choice
+        prompt "Choose FPU version"
+        default ARCH_FPU_VFP_V4
+        depends on !ARCH_FPU_DISABLE
+        help
+            Choose FPU version.
+        
+    config ARCH_FPU_VFP_V3
+        bool "VFP_V3"
+        help
+        An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
+        VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support code.

-config ARCH_FPU_VFP_D16
-    bool
-    depends on ARCH_ARM_AARCH32
-    help
-      VPU implemented with 16 doubleword registers (16 x 64-bit).
+    config ARCH_FPU_VFP_V4
+        bool "VFP_V4"
+        help
+        An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
+        VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support code.
+        VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to the features of VFPv3.
+    endchoice

-config ARCH_FPU_VFP_D32
-    bool
-    depends on ARCH_ARM_AARCH32
-    help
-      VPU implemented with 32 doubleword registers (32 x 64-bit).
+    choice
+        prompt "Choose num of FPU doubleword registers"
+        default ARCH_FPU_VFP_D32
+        depends on !ARCH_FPU_DISABLE
+        help
+            Choose num of FPU doubleword registers.

-config ARCH_FPU_VFP_NEON
-    bool
-    help
-      Advanced SIMD extension (NEON) support.
+    config ARCH_FPU_VFP_D16
+        bool "FPU_VFP_D16"
+        depends on ARCH_ARM_AARCH32
+        help
+        VPU implemented with 16 doubleword registers (16 x 64-bit).

+    config ARCH_FPU_VFP_D32
+        bool "FPU_VFP_D32"
+        depends on ARCH_ARM_AARCH32
+        help
+        VPU implemented with 32 doubleword registers (32 x 64-bit).
+    endchoice
+endchoice
 config ARCH_FPU
    string
-    default "vfpv3"       if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D32
-    default "vfpv3-d16"   if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D16
-    default "neon-vfpv4"  if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32 && ARCH_FPU_VFP_NEON
-    default "vfpv4"       if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32
-    default "vfpv4-d16"   if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D16
+    default "vfpv3"       if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D32 && !COMPILER_ICCARM
+    default "vfpv3-d16"   if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D16 && !COMPILER_ICCARM
+    default "vfpv4"       if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32 && !COMPILER_ICCARM
+    default "vfpv4-d16"   if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D16 && !COMPILER_ICCARM
+    default "VFPv3"       if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D32 && COMPILER_ICCARM
+    default "VFPv3_D16"   if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D16 && COMPILER_ICCARM
+    default "VFPv4"       if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32 && COMPILER_ICCARM
+    default "VFPv4_D16"   if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D16 && COMPILER_ICCARM

 #
 # Supported Processor Cores
@@ -86,22 +104,16 @@ config ARCH_CORTEX_M7
    bool
    select ARCH_ARM_V7M
    select ARCH_ARM_AARCH32
-    select ARCH_FPU_VFP_V4
-    select ARCH_FPU_VFP_D32

 config ARCH_CORTEX_M33
    bool
    select ARCH_ARM_V8M
    select ARCH_ARM_AARCH32
-    select ARCH_FPU_VFP_V4
-    select ARCH_FPU_VFP_D32

 config ARCH_CORTEX_M55
    bool
    select ARCH_ARM_V8M
    select ARCH_ARM_AARCH32
-    select ARCH_FPU_VFP_V4
-    select ARCH_FPU_VFP_D32

 config ARCH_ARM9
    bool
@@ -110,9 +122,14 @@ config ARCH_ARM9

 config ARCH_CPU
    string
-    default "cortex-m3" if ARCH_CORTEX_M3
-    default "cortex-m4" if ARCH_CORTEX_M4
-    default "cortex-m7" if ARCH_CORTEX_M7
-    default "cortex-m33" if ARCH_CORTEX_M33
-    default "cortex-m55" if ARCH_CORTEX_M55
+    default "cortex-m3" if ARCH_CORTEX_M3 && !COMPILER_ICCARM
+    default "cortex-m4" if ARCH_CORTEX_M4 && !COMPILER_ICCARM
+    default "cortex-m7" if ARCH_CORTEX_M7 && !COMPILER_ICCARM
+    default "cortex-m33" if ARCH_CORTEX_M33 && !COMPILER_ICCARM
+    default "cortex-m55" if ARCH_CORTEX_M55 && !COMPILER_ICCARM
+    default "Cortex-M3" if ARCH_CORTEX_M3 && COMPILER_ICCARM
+    default "Cortex-M4" if ARCH_CORTEX_M4 && COMPILER_ICCARM
+    default "Cortex-M7" if ARCH_CORTEX_M7 && COMPILER_ICCARM
+    default "Cortex-M33" if ARCH_CORTEX_M33 && COMPILER_ICCARM
+    default "Cortex-M55" if ARCH_CORTEX_M55 && COMPILER_ICCARM
    default "arm9" if ARCH_ARM9
--- a/arch/arm/arm9/gcc/los_arch_atomic.h
+++ b/arch/arm/arm9/gcc/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/arm9/gcc/los_context.c
+++ b/arch/arm/arm9/gcc/los_context.c
@@ -59,7 +59,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m3/keil/los_arch_atomic.h
+++ b/arch/arm/cortex-m3/keil/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m3/keil/los_context.c
+++ b/arch/arm/cortex-m3/keil/los_context.c
@@ -60,7 +60,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m33/gcc/NTZ/los_arch_atomic.h
+++ b/arch/arm/cortex-m33/gcc/NTZ/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m33/gcc/NTZ/los_context.c
+++ b/arch/arm/cortex-m33/gcc/NTZ/los_context.c
@@ -59,7 +59,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_atomic.h
+++ b/arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m33/gcc/TZ/non_secure/los_context.c
+++ b/arch/arm/cortex-m33/gcc/TZ/non_secure/los_context.c
@@ -59,7 +59,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m33/gcc/TZ/non_secure/los_timer.c
+++ b/arch/arm/cortex-m33/gcc/TZ/non_secure/los_timer.c
@@ -91,7 +91,7 @@ STATIC UINT64 SysTickReload(UINT64 nextResponseTime)

 STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
-    UINT32 hwCycle = 0；
+    UINT32 hwCycle = 0;
    UINT32 intSave = LOS_IntLock();
    UINT32 val = SysTick->VAL;
    *period = SysTick->LOAD;
--- a/arch/arm/cortex-m33/gcc/TZ/non_secure/los_trustzone.c
+++ b/arch/arm/cortex-m33/gcc/TZ/non_secure/los_trustzone.c
@@ -51,6 +51,7 @@ VOID HalSecureSVCHandler(UINT32 svcID, UINTPTR arg)
            HalSecureContextLoad(g_secureContext);
            break;
        case OS_SVC_FREE_SECURE_CONTEXT:
+            LOS_ASSERT(g_secureContext != NULL);
            HalSecureContextFree(g_secureContext);
            break;
        default:
--- a/arch/arm/cortex-m33/iar/BUILD.gn
+++ b/arch/arm/cortex-m33/iar/BUILD.gn
@@ -26,13 +26,12 @@
 # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-if LIBC_ICCARM
+import("//kernel/liteos_m/liteos.gni")

-config LIBC_ICCARM_FS
-    bool "Enable POSIX file system API support"
-    default y
-    depends on FS_VFS
-    help
-        This enables POSIX style file system related APIs.
-
-endif # LIBC_ICCARM
+module_group("iar") {
+  if (defined(LOSCFG_SECURE_TRUSTZONE)) {
+    modules = [ "TZ" ]
+  } else {
+    modules = [ "NTZ" ]
+  }
+}
--- a/arch/arm/cortex-m33/iar/NTZ/BUILD.gn
+++ b/arch/arm/cortex-m33/iar/NTZ/BUILD.gn
@@ -0,0 +1,45 @@
+# Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_name = "arch"
+kernel_module(module_name) {
+  sources = [
+    "los_context.c",
+    "los_dispatch.S",
+    "los_exc.S",
+    "los_interrupt.c",
+    "los_timer.c",
+  ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
+}
+
+config("public") {
+  include_dirs = [ "." ]
+}
--- a/arch/arm/cortex-m33/iar/NTZ/los_arch_atomic.h
+++ b/arch/arm/cortex-m33/iar/NTZ/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m33/iar/NTZ/los_context.c
+++ b/arch/arm/cortex-m33/iar/NTZ/los_context.c
@@ -59,7 +59,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_atomic.h
+++ b/arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m33/iar/TZ/non_secure/los_context.c
+++ b/arch/arm/cortex-m33/iar/TZ/non_secure/los_context.c
@@ -59,7 +59,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m33/iar/TZ/non_secure/los_trustzone.c
+++ b/arch/arm/cortex-m33/iar/TZ/non_secure/los_trustzone.c
@@ -51,6 +51,7 @@ VOID HalSecureSVCHandler(UINT32 svcID, UINTPTR arg)
            HalSecureContextLoad(g_secureContext);
            break;
        case OS_SVC_FREE_SECURE_CONTEXT:
+            LOS_ASSERT(g_secureContext != NULL);
            HalSecureContextFree(g_secureContext);
            break;
        default:
--- a/arch/arm/cortex-m33/iar/TZ/secure/los_secure_context.h
+++ b/arch/arm/cortex-m33/iar/TZ/secure/los_secure_context.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -63,5 +63,3 @@ extern VOID HalSecureContextSaveAsm(OsSecureContext *secureContext);
 #endif /* __cplusplus */

 #endif
-
-
--- a/arch/arm/cortex-m4/gcc/los_arch_atomic.h
+++ b/arch/arm/cortex-m4/gcc/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m4/gcc/los_context.c
+++ b/arch/arm/cortex-m4/gcc/los_context.c
@@ -58,7 +58,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m4/iar/BUILD.gn
+++ b/arch/arm/cortex-m4/iar/BUILD.gn
@@ -0,0 +1,47 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_name = "arch"
+kernel_module(module_name) {
+  sources = [
+    "los_context.c",
+    "los_dispatch.S",
+    "los_exc.S",
+    "los_interrupt.c",
+    "los_mpu.c",
+    "los_timer.c",
+  ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
+}
+
+config("public") {
+  include_dirs = [ "." ]
+}
--- a/arch/arm/cortex-m4/iar/los_arch_atomic.h
+++ b/arch/arm/cortex-m4/iar/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m4/iar/los_context.c
+++ b/arch/arm/cortex-m4/iar/los_context.c
@@ -61,7 +61,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m55/gcc/NTZ/los_arch_atomic.h
+++ b/arch/arm/cortex-m55/gcc/NTZ/los_arch_atomic.h
@@ -32,6 +32,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m55/gcc/NTZ/los_context.c
+++ b/arch/arm/cortex-m55/gcc/NTZ/los_context.c
@@ -58,7 +58,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m55/gcc/TZ/BUILD.gn
+++ b/arch/arm/cortex-m55/gcc/TZ/BUILD.gn
@@ -0,0 +1,52 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_name = "arch"
+kernel_module(module_name) {
+  sources = [
+    "non_secure/los_context.c",
+    "non_secure/los_dispatch.S",
+    "non_secure/los_exc.S",
+    "non_secure/los_interrupt.c",
+    "non_secure/los_timer.c",
+    "non_secure/los_trustzone.c",
+  ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
+
+  include_dirs = [
+    "non_secure",
+    "secure",
+  ]
+}
+
+config("public") {
+  include_dirs = [ "non_secure" ]
+}
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_arch_atomic.h
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_arch_atomic.h
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    __asm__ __volatile__("ldrex %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%1]\n"
+                             "strex %0, %2, [%1]\n"
+                             : "=&r"(status)
+                             : "r"(v), "r"(setVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "add %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "sub %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%3]\n"
+                             "strex %1, %4, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("ldrex %0, %2\n"
+                             "mov %1, #0\n"
+                             "cmp %0, %3\n"
+                             "bne 1f\n"
+                             "strex %1, %4, %2\n"
+                             "1:"
+                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
+                             : "r"(oldVal), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_arch_context.h
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_arch_context.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct TagTskContext {
+    UINT32 secureContext;
+    UINT32 stackLimit;
+    UINT32 excReturn;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} TaskContext;
+
+/**
+ * @ingroup  los_config
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_arch_interrupt.h
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_arch_interrupt.h
@@ -0,0 +1,683 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_INTERRUPT_H
+#define _LOS_ARCH_INTERRUPT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST                   0
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST                    7
+#endif
+
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of M-Core system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT                     16
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of M-Core interrupt vector.
+ */
+#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * AIRCR register priority group parameter .
+ */
+#define OS_NVIC_AIRCR_PRIGROUP                7
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Boot interrupt vector table.
+ */
+extern UINT32 _BootVectors[];
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * SysTick control and status register.
+ */
+#define OS_SYSTICK_CONTROL_REG                0xE000E010
+
+/* *
+ * @ingroup los_hw
+ * SysTick current value register.
+ */
+#define OS_SYSTICK_CURRENT_REG                0xE000E018
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt Priority-Level Registers.
+ */
+#define OS_NVIC_PRI_BASE                      0xE000E400
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt enable register for 0-31.
+ */
+#define OS_NVIC_SETENA_BASE                   0xE000E100
+
+/* *
+ * @ingroup los_arch_interrupt
+ * interrupt pending register.
+ */
+#define OS_NVIC_SETPEND_BASE                  0xE000E200
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt active register.
+ */
+#define OS_NVIC_INT_ACT_BASE                  0xE000E300
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt disable register for 0-31.
+ */
+#define OS_NVIC_CLRENA_BASE                   0xE000E180
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt control and status register.
+ */
+#define OS_NVIC_INT_CTRL                      0xE000ED04
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Vector table offset register.
+ */
+#define OS_NVIC_VTOR                          0xE000ED08
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Application interrupt and reset control register
+ */
+#define OS_NVIC_AIRCR                         0xE000ED0C
+
+/* *
+ * @ingroup los_arch_interrupt
+ * System exception priority register.
+ */
+#define OS_NVIC_EXCPRI_BASE                   0xE000ED18
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 1 :reset.
+ */
+#define OS_EXC_RESET                          1
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 2 :Non-Maskable Interrupt.
+ */
+#define OS_EXC_NMI                            2
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 3 :(hard)fault.
+ */
+#define OS_EXC_HARD_FAULT                     3
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 4 :MemManage fault.
+ */
+#define OS_EXC_MPU_FAULT                      4
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 5 :Bus fault.
+ */
+#define OS_EXC_BUS_FAULT                      5
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 6 :Usage fault.
+ */
+#define OS_EXC_USAGE_FAULT                    6
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 11 :SVCall.
+ */
+#define OS_EXC_SVC_CALL                       11
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 12 :Debug monitor.
+ */
+#define OS_EXC_DBG_MONITOR                    12
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 14 :PendSV.
+ */
+#define OS_EXC_PEND_SV                        14
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 15 :SysTick.
+ */
+#define OS_EXC_SYS_TICK                       15
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_arch_interrupt
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_arch_interrupt
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Reset the vector table.
+ *
+ * @par Description:
+ * This API is used to reset the vector table.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID Reset_Handler(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Pended System Call.
+ *
+ * @par Description:
+ * PendSV can be pended and is useful for an OS to pend an exception
+ * so that an action can be performed after other important tasks are completed.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalPendSV(VOID);
+
+
+#define OS_EXC_IN_INIT                      0
+#define OS_EXC_IN_TASK                      1
+#define OS_EXC_IN_HWI                       2
+
+#define OS_EXC_MAX_BUF_LEN                  25
+#define OS_EXC_MAX_NEST_DEPTH               1
+
+#define OS_NVIC_SHCSR                       0xE000ED24
+#define OS_NVIC_CCR                         0xE000ED14
+
+#define OS_NVIC_INT_ENABLE_SIZE             0x20
+#define OS_NVIC_INT_PRI_SIZE                0xF0
+#define OS_NVIC_EXCPRI_SIZE                 0xC
+#define OS_NVIC_INT_CTRL_SIZE               4
+#define OS_NVIC_SHCSR_SIZE                  4
+
+#define OS_NVIC_INT_PEND_SIZE               OS_NVIC_INT_ACT_SIZE
+#define OS_NVIC_INT_ACT_SIZE                OS_NVIC_INT_ENABLE_SIZE
+
+#define OS_EXC_FLAG_NO_FLOAT                0x10000000
+#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
+#define OS_EXC_FLAG_IN_HWI                  0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
+
+#define OS_EXC_EVENT                        0x00000001
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
+ */
+typedef struct TagExcContext {
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    /* auto save */
+    UINT32 uwSP;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED) && (__FPU_USED== 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+
+VOID HalExcNMI(VOID);
+VOID HalExcHardFault(VOID);
+VOID HalExcMemFault(VOID);
+VOID HalExcBusFault(VOID);
+VOID HalExcUsageFault(VOID);
+VOID HalSVCHandler(VOID);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was being pushed.
+ */
+#define OS_EXC_BF_STKERR           1
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was out of the stack.
+ */
+#define OS_EXC_BF_UNSTKERR         2
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register imprecise data access violation.
+ */
+#define OS_EXC_BF_IMPRECISERR      3
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register exact data access violation.
+ */
+#define OS_EXC_BF_PRECISERR        4
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register access violation while pointing.
+ */
+#define OS_EXC_BF_IBUSERR          5
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was being pushed.
+ */
+#define OS_EXC_MF_MSTKERR          6
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
+ */
+#define OS_EXC_MF_MUNSTKERR        7
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register data access violation.
+ */
+#define OS_EXC_MF_DACCVIOL         8
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register access violation.
+ */
+#define OS_EXC_MF_IACCVIOL         9
+
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
+ */
+#define OS_EXC_UF_DIVBYZERO        10
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error, error caused by unaligned access.
+ */
+#define OS_EXC_UF_UNALIGNED        11
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
+ */
+#define OS_EXC_UF_NOCP             12
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
+ */
+#define OS_EXC_UF_INVPC            13
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
+ */
+#define OS_EXC_UF_INVSTATE         14
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
+ */
+#define OS_EXC_UF_UNDEFINSTR       15
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: NMI
+ */
+
+#define OS_EXC_CAUSE_NMI           16
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: hard fault
+ */
+#define OS_EXC_CAUSE_HARDFAULT     17
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: The task handler exits.
+ */
+#define OS_EXC_CAUSE_TASK_EXIT     18
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A fatal error.
+ */
+#define OS_EXC_CAUSE_FATAL_ERR     19
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Hard Fault caused by a debug event.
+ */
+#define OS_EXC_CAUSE_DEBUGEVT      20
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
+ */
+#define OS_EXC_CAUSE_VECTBL        21
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M33 platform.
+ *
+ */
+typedef struct TagExcInfo {
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    UINT16 phase;
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
+    UINT16 type;
+    /**< If the exact address access error indicates the wrong access address when the exception occurred */
+    UINT32 faultAddr;
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    UINT32 thrdPid;
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
+    UINT16 nestCnt;
+    /**< reserve */
+    UINT16 reserved;
+    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+    EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_curNestCount;
+extern UINT32 g_intCount;
+extern UINT8 g_uwExcTbl[32];
+extern ExcInfo g_excInfo;
+
+#define MAX_INT_INFO_SIZE       (8 + 0x164)
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_INTERRUPT_H */
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_arch_timer.h
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_arch_timer.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2021-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -28,27 +29,23 @@
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

-#include "los_tick.h"
-#include <time.h>
-#include <sys/time.h>
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H

-#define SECS_PER_MIN 60
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"

-int _gettimeofday(struct timeval *__tp, void *__tzp)
-{
-    struct timespec ts;
-    struct timezone *tz = (struct timezone *)__tzp;
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */

-    if (__tp != NULL) {
-        if (-1 == clock_gettime(CLOCK_REALTIME, &ts)) {
-            return -1;
-        }
-        __tp->tv_sec = ts.tv_sec;
-        __tp->tv_usec = ts.tv_nsec / OS_SYS_NS_PER_US;
-    }
-    if (tz != NULL) {
-        tz->tz_minuteswest = timezone / SECS_PER_MIN;
-        tz->tz_dsttime = 0;
-    }
-    return 0;
-}
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_context.c
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_context.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
+
+/* ****************************************************************************
+ Function    : ArchInit
+ Description : arch init function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+    HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function    : ArchSysExit
+ Description : Task exit function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+    (VOID)LOS_IntLock();
+    while (1) {
+    }
+}
+
+/* ****************************************************************************
+ Function    : ArchTskStackInit
+ Description : Task stack initialization function
+ Input       : taskID     --- TaskID
+               stackSize  --- Total size of the stack
+               topStack   --- Top of task's stack
+ Output      : None
+ Return      : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
+
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    context->S16 = 0xAA000010;
+    context->S17 = 0xAA000011;
+    context->S18 = 0xAA000012;
+    context->S19 = 0xAA000013;
+    context->S20 = 0xAA000014;
+    context->S21 = 0xAA000015;
+    context->S22 = 0xAA000016;
+    context->S23 = 0xAA000017;
+    context->S24 = 0xAA000018;
+    context->S25 = 0xAA000019;
+    context->S26 = 0xAA00001A;
+    context->S27 = 0xAA00001B;
+    context->S28 = 0xAA00001C;
+    context->S29 = 0xAA00001D;
+    context->S30 = 0xAA00001E;
+    context->S31 = 0xAA00001F;
+    context->S0 = 0xAA000000;
+    context->S1 = 0xAA000001;
+    context->S2 = 0xAA000002;
+    context->S3 = 0xAA000003;
+    context->S4 = 0xAA000004;
+    context->S5 = 0xAA000005;
+    context->S6 = 0xAA000006;
+    context->S7 = 0xAA000007;
+    context->S8 = 0xAA000008;
+    context->S9 = 0xAA000009;
+    context->S10 = 0xAA00000A;
+    context->S11 = 0xAA00000B;
+    context->S12 = 0xAA00000C;
+    context->S13 = 0xAA00000D;
+    context->S14 = 0xAA00000E;
+    context->S15 = 0xAA00000F;
+    context->FPSCR = 0x00000000;
+    context->NO_NAME = 0xAA000011;
+#endif
+
+    context->secureContext = 0UL;
+    context->stackLimit = (UINT32)topStack;
+    context->excReturn = 0xFFFFFFBC;
+
+    context->uwR4 = 0x04040404L;
+    context->uwR5 = 0x05050505L;
+    context->uwR6 = 0x06060606L;
+    context->uwR7 = 0x07070707L;
+    context->uwR8 = 0x08080808L;
+    context->uwR9 = 0x09090909L;
+    context->uwR10 = 0x10101010L;
+    context->uwR11 = 0x11111111L;
+    context->uwPriMask = 0;
+    context->uwR0 = taskID;
+    context->uwR1 = 0x01010101L;
+    context->uwR2 = 0x02020202L;
+    context->uwR3 = 0x03030303L;
+    context->uwR12 = 0x12121212L;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
+    context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
+    context->uwxPSR = 0x01000000L;
+
+    return (VOID *)context;
+}
+
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->stackLimit = (UINT32)stackTop;
+    context->excReturn = 0xFFFFFFBC;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+    return LOS_OK; /* never return */
+}
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_dispatch.S
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_dispatch.S
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .syntax unified
+ .arch armv8.1-m.main
+ .fpu vfpv3-d16-fp16
+ .thumb
+
+.equ    OS_FPU_CPACR,                0xE000ED88
+.equ    OS_FPU_CPACR_ENABLE,         0x00F00000
+.equ    OS_NVIC_INT_CTRL,            0xE000ED04
+.equ    OS_NVIC_SYSPRI2,             0xE000ED20
+.equ    OS_NVIC_PENDSV_PRI,          0xF0F00000
+.equ    OS_NVIC_PENDSVSET,           0x10000000
+.equ    OS_TASK_STATUS_RUNNING,      0x0010
+
+    .section .text
+    .thumb
+
+.macro SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+.endm
+
+    .type HalStartFirstTask, %function
+    .global HalStartFirstTask
+HalStartFirstTask:
+    MOV     R0, #2
+    MSR     CONTROL, R0
+
+    LDR     R1, =g_losTask
+    LDR     R0, [R1, #4]
+
+    LDR     R12, [R0]                  /* Get the stack pointer of the current task. */
+    LDMFD   R12!, {R1-R3}              /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 = excReturn.*/
+    LDR     R4, =g_secureContext
+    STR     R1, [R4]                   /* Set the secureContext to g_secureContext handler. */
+    MSR     PSPLIM, R2                 /* Set the stackLmit for the PSPLIM about current task. */
+    ISB
+
+    LDR.W   R1, =OS_FPU_CPACR
+    LDR     R1, [R1]
+    AND     R1, R1, #OS_FPU_CPACR_ENABLE
+    CMP     R1, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU1
+    ADD     R12, R12, #64
+    VPUSH   {S0}
+    VPOP    {S0}
+
+__DisabledFPU1:
+    ADD     R12, R12, #36
+    MSR     PSP, R12
+    CPSIE   I
+    BX      R3
+
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
+    .fnstart
+    .cantunwind
+
+    MRS R0, PRIMASK
+    CPSID I
+    BX LR
+    .fnend
+
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
+    .fnstart
+    .cantunwind
+
+    MRS R0, PRIMASK
+    CPSIE I
+    BX LR
+    .fnend
+
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
+    .fnstart
+    .cantunwind
+
+    MSR PRIMASK, R0
+    BX LR
+    .fnend
+
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
+    .fnstart
+    .cantunwind
+
+    ldr     r0, =OS_NVIC_INT_CTRL
+    ldr     r1, =OS_NVIC_PENDSVSET
+    str     r1, [r0]
+    dsb
+    isb
+    bx      lr
+   .fnend
+
+    .type HalPendSV, %function
+    .global HalPendSV
+HalPendSV:
+    .fnstart
+    .cantunwind
+
+    mrs     r12, PRIMASK
+    cpsid   I
+
+HalTaskSwitch:
+    SIGNAL_CONTEXT_RESTORE
+
+    push    {r12, lr}
+    blx     OsSchedTaskSwitch
+    pop     {r12, lr}
+    cmp     r0, #0
+    mov     r0, lr
+    bne     TaskContextSwitch
+    msr     PRIMASK, r12
+    bx      lr
+
+TaskContextSwitch:
+    mov     lr, r0
+    mrs     r0, psp
+
+    LDR     R2, =g_secureContext
+    LDR     R1, [R2]
+    CBZ     R1, __SaveNSContext               /* If the g_secureContext is NULL, so no secure context to save. */
+
+    PUSH    {R0-R1, R12, R14}                 /* Store registers, include LR, PRIMASK. */
+    BL      HalSecureContextSave              /* Store the secure context to g_secureContext->curStackPointer. */
+    POP     {R0-R3}
+    MOV     LR, R3
+    MOV     R12, R2                           /* R2 = PRIMASK. */
+
+__SaveNSContext:
+    STMFD   R0!, {R4-R12}
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU2
+    VSTMDB  R0!, {D8-D15}
+
+__DisabledFPU2:
+    LDR     R5, =g_losTask
+    LDR     R6, [R5]                          /* Get the stackPointer handler of the current task. */
+    SUBS    R0, R0, #12
+    STR     R0, [R6]                          /* Save the new top of stack in TCB. */
+    MRS     R2, PSPLIM
+    MOV     R3, LR
+    STMIA   R0!, {R1, R2-R3}                  /* Store g_secureContext, PSPLIM and LR on the stack of current task. */
+
+    LDR     R0, [R5, #4]
+    STR     R0, [R5]
+    LDR     R1, [R0]
+
+SignalContextRestore:
+    LDMIA   R1!, {R0, R2-R3}                  /* Restore secureContext, PSPLIM and LR from the current task stack. */
+    MSR     PSPLIM, R2
+    MOV     LR, R3
+    LDR     R2, =g_secureContext
+    STR     R0, [R2]                          /* Set the secureContext of the new task to g_secureContext. */
+    CBZ     R0, __RestoreNSContext            /* If there is no secure context for the new task, so restore from the non-secure context. */
+    PUSH    {R1, R3}
+    BL      HalSecureContextLoad              /* Restore the secure context. */
+    POP     {R1, R3}
+    MOV     LR, R3
+
+__RestoreNSContext:
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU3
+    VLDMIA  R1!, {D8-D15}
+
+__DisabledFPU3:
+    LDMFD   R1!, {R4-R12}
+    MSR     PSP,  R1
+
+    MSR     PRIMASK, R12
+    BX      LR
+    .fnend
+
+    .type HalSVCStartSchedule, %function
+    .global HalSVCStartSchedule
+HalSVCStartSchedule:
+    .fnstart
+    .cantunwind
+    LDR     R4, =OS_NVIC_SYSPRI2
+    LDR     R5, =OS_NVIC_PENDSV_PRI
+    STR     R5, [R4]
+    CPSIE   I
+    DSB
+    ISB
+    SVC     2
+    .fnend
+
+    .type HalSVCSecureContextAlloc, %function
+    .global HalSVCSecureContextAlloc
+HalSVCSecureContextAlloc:
+    .fnstart
+    .cantunwind
+    SVC     0
+    BX      LR
+    .fnend
+
+    .type HalSVCSecureContextFree, %function
+    .global HalSVCSecureContextFree
+HalSVCSecureContextFree:
+    .fnstart
+    .cantunwind
+    SVC     1
+    BX      LR
+    .fnend
+
+    .type HalSVCHandler, %function
+    .global HalSVCHandler
+HalSVCHandler:
+    .fnstart
+    .cantunwind
+    TST     LR, #0x04
+    ITE     EQ
+    MRSEQ   R1, MSP
+    MRSNE   R1, PSP
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]                     /* Get the SVC number. */
+
+    PUSH    {LR}
+    MOV     R2, R1                            /* Get the stack for R2. */
+    LDMFD   R2!, {R1}                         /* Get the input arg for HalSecureSVCHandler. */
+    STMFD   R2!, {R1}
+    BL      HalSecureSVCHandler
+    POP     {LR}
+    BX      LR
+    .fnend
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_exc.S
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_exc.S
@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .syntax unified
+ .arch armv8.1-m.main
+ .fpu vfpv3-d16-fp16
+ .thumb
+.section .text
+
+
+    .global  HalExcNMI
+    .global  HalExcHardFault
+    .global  HalExcMemFault
+    .global  HalExcBusFault
+    .global  HalExcUsageFault
+
+    .extern HalExcHandleEntry
+    .extern g_uwExcTbl
+    .extern g_taskScheduled
+
+.equ OS_FLG_BGD_ACTIVE,   0x0002
+
+.equ OS_EXC_CAUSE_NMI,   16
+.equ OS_EXC_CAUSE_HARDFAULT,   17
+
+.equ HF_DEBUGEVT,   20
+.equ HF_VECTBL,   21
+
+.equ FLAG_ADDR_VALID,   0x10000
+.equ FLAG_HWI_ACTIVE,   0x20000
+.equ FLAG_NO_FLOAT,   0x10000000
+
+.equ OS_NVIC_FSR                 ,   0xE000ED28      //include BusFault/MemFault/UsageFault State Register
+.equ OS_NVIC_HFSR                ,   0xE000ED2C      //HardFault State Register
+.equ OS_NVIC_BFAR                ,   0xE000ED38
+.equ OS_NVIC_MMAR                ,   0xE000ED34
+.equ OS_NVIC_ACT_BASE            ,   0xE000E300
+.equ OS_NVIC_SHCSRS              ,   0xE000ED24
+.equ OS_NVIC_SHCSR_MASK          ,   0xC00
+
+    .type HalExcNMI, %function
+    .global HalExcNMI
+HalExcNMI:
+    .fnstart
+    .cantunwind
+    MOV  R0, #OS_EXC_CAUSE_NMI
+    MOV  R1, #0
+    B  osExcDispatch
+    .fnend
+
+    .type HalExcHardFault, %function
+    .global HalExcHardFault
+HalExcHardFault:
+    .fnstart
+    .cantunwind
+    MOV  R0, #OS_EXC_CAUSE_HARDFAULT
+    LDR  R2, =OS_NVIC_HFSR
+    LDR  R2, [R2]
+
+    MOV  R1, #HF_DEBUGEVT
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x80000000
+    BNE  osExcDispatch     // DEBUGEVT
+
+    AND  R0, R0 , #0x000000FF
+    MOV  R1, #HF_VECTBL
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x00000002
+    BNE  osExcDispatch     // VECTBL
+
+    //if not DEBUGEVT and VECTBL then is FORCED
+    AND  R0, R0, #0x000000FF
+
+    LDR  R2, =OS_NVIC_FSR
+    LDR  R2, [R2]
+
+    TST  R2, #0x8000     // BFARVALID
+    BNE  _HFBusFault     // BusFault
+
+    TST  R2, #0x80       // MMARVALID
+    BNE  _HFMemFault     // MemFault
+
+    MOV  R12,#0
+    B    osHFExcCommonBMU
+    .fnend
+
+    .type _HFBusFault, %function
+
+_HFBusFault:
+    .fnstart
+    .cantunwind
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    B    osHFExcCommonBMU
+    .fnend
+
+    .type _HFMemFault, %function
+
+_HFMemFault:
+    .fnstart
+    .cantunwind
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    .fnend
+
+    .type osHFExcCommonBMU, %function
+    .global osHFExcCommonBMU
+osHFExcCommonBMU:
+    .fnstart
+    .cantunwind
+    CLZ  R2, R2
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R2
+    LDRB R2, [R3]
+    ORR  R0, R0, R2, LSL #0x8
+    ORR  R0, R0 ,R12
+    B    osExcDispatch
+    .fnend
+
+    .type HalExcBusFault, %function
+    .global HalExcBusFault
+HalExcBusFault:
+    .fnstart
+    .cantunwind
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x8000  // BFARVALID
+    BEQ  _ExcBusNoADDR
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1F00
+
+    B    osExcCommonBMU
+    .fnend
+
+    .type _ExcBusNoADDR, %function
+    .global _ExcBusNoADDR
+_ExcBusNoADDR:
+    .fnstart
+    .cantunwind
+    MOV  R12,#0
+    B    osExcCommonBMU
+    .fnend
+
+    .type HalExcMemFault, %function
+    .global HalExcMemFault
+HalExcMemFault:
+    .fnstart
+    .cantunwind
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x80 // MMARVALID
+    BEQ  _ExcMemNoADDR
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1B
+
+    B    osExcCommonBMU
+    .fnend
+
+    .type _ExcMemNoADDR, %function
+    .global _ExcMemNoADDR
+_ExcMemNoADDR:
+    .fnstart
+    .cantunwind
+    MOV  R12,#0
+    B    osExcCommonBMU
+    .fnend
+
+    .type HalExcUsageFault, %function
+    .global HalExcUsageFault
+HalExcUsageFault:
+    .fnstart
+    .cantunwind
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    MOVW  R1, #0x030F
+    LSL  R1, R1, #16
+    AND  R0, R0, R1
+    MOV  R12, #0
+
+    .fnend
+
+    .type osExcCommonBMU, %function
+    .global osExcCommonBMU
+osExcCommonBMU:
+    .fnstart
+    .cantunwind
+    CLZ  R0, R0
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R0
+    LDRB R0, [R3]
+    ORR  R0, R0, R12
+    .fnend
+// R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid),  R1 -- EXCADDR
+
+    .type osExcDispatch, %function
+    .global osExcDispatch
+osExcDispatch:
+    .fnstart
+    .cantunwind
+    LDR   R2, =OS_NVIC_ACT_BASE
+    MOV   R12, #8                       // R12 is hwi check loop counter
+    .fnend
+
+    .type _hwiActiveCheck, %function
+    .global _hwiActiveCheck
+_hwiActiveCheck:
+    .fnstart
+    .cantunwind
+    LDR   R3, [R2]                      // R3 store active hwi register when exc
+    CMP   R3, #0
+    BEQ   _hwiActiveCheckNext
+
+    // exc occurred in IRQ
+    ORR   R0, R0, #FLAG_HWI_ACTIVE
+    RBIT  R2, R3
+    CLZ   R2, R2
+    AND   R12, R12, #1
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
+    .fnend
+
+    .type _ExcInMSP, %function
+    .global _ExcInMSP
+_ExcInMSP:
+    .fnstart
+    .cantunwind
+    CMP   LR, #0xFFFFFFE9
+    BNE   _NoFloatInMsp
+    ADD   R3, R13, #104
+    PUSH  {R3}
+    MRS   R12, PRIMASK                  // store message-->exc: disable int?
+    PUSH {R4-R12}                       // store message-->exc: {R4-R12}
+    VPUSH {D8-D15}
+    B     _handleEntry
+  .fnend
+
+    .type _NoFloatInMsp, %function
+    .global _NoFloatInMsp
+_NoFloatInMsp:
+    .fnstart
+    .cantunwind
+    ADD   R3, R13, #32
+    PUSH  {R3} // save IRQ SP            // store message-->exc: MSP(R13)
+
+    MRS   R12, PRIMASK                  // store message-->exc: disable int?
+    PUSH {R4-R12}                       // store message-->exc: {R4-R12}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+    B     _handleEntry
+  .fnend
+
+    .type _hwiActiveCheckNext, %function
+    .global _hwiActiveCheckNext
+_hwiActiveCheckNext:
+    .fnstart
+    .cantunwind
+    ADD   R2, R2, #4                        // next NVIC ACT ADDR
+    SUBS  R12, R12, #1
+    BNE   _hwiActiveCheck
+
+    /*NMI interrupt excption*/
+    LDR   R2, =OS_NVIC_SHCSRS
+    LDRH  R2,[R2]
+    LDR   R3,=OS_NVIC_SHCSR_MASK
+    AND   R2, R2,R3
+    CMP   R2,#0
+    BNE   _ExcInMSP
+    // exc occurred in Task or Init or exc
+    // reserved for register info from task stack
+
+    LDR  R2, =g_taskScheduled
+    LDR  R2, [R2]
+    TST  R2, #1                         // OS_FLG_BGD_ACTIVE
+    BEQ  _ExcInMSP                      // if exc occurred in Init then branch
+
+
+    CMP   LR, #0xFFFFFFED               //auto push floating registers
+    BNE   _NoFloatInPsp
+
+    // exc occurred in Task
+    MOV   R2,  R13
+    SUB   R13, #96                      // add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #104
+    PUSH  {R12}                         // save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+    VPUSH {D8-D15}
+
+    // copy auto saved task register
+
+    LDMFD R3!, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
+    VLDMIA  R3!, {D8-D15}
+    VSTMDB  R2!, {D8-D15}
+    STMFD R2!, {R4-R11}
+    B     _handleEntry
+  .fnend
+
+    .type _NoFloatInPsp, %function
+    .global _NoFloatInPsp
+_NoFloatInPsp:
+    .fnstart
+    .cantunwind
+    MOV   R2,  R13                      // no auto push floating registers
+    SUB   R13, #32                      // add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #32
+    PUSH  {R12}                         // save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+
+    LDMFD R3, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
+    STMFD R2!, {R4-R11}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+  .fnend
+
+    .type _handleEntry, %function
+    .global _handleEntry
+_handleEntry:
+    .fnstart
+    .cantunwind
+    MOV R3, R13                         // R13:the 4th param
+    CPSID I
+    CPSID F
+    B  HalExcHandleEntry
+
+    NOP
+  .fnend
+
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_interrupt.c
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_interrupt.c
@@ -0,0 +1,649 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "los_interrupt.h"
+#include <stdarg.h>
+#include "securec.h"
+#include "los_context.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
+#include "los_cpup.h"
+#endif
+
+#define DEF_HANDLER_START_INDEX 2
+UINT32 g_intCount = 0;
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_DEBUG_TOOLS == 1)
+STATIC UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM] = {0};
+STATIC CHAR *g_hwiFormName[OS_HWI_MAX_NUM] = {0};
+
+UINT32 OsGetHwiFormCnt(UINT32 index)
+{
+    return g_hwiFormCnt[index];
+}
+
+CHAR *OsGetHwiFormName(UINT32 index)
+{
+    return g_hwiFormName[index];
+}
+
+BOOL OsGetHwiCreated(UINT32 index)
+{
+    if (g_hwiForm[index] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return TRUE;
+    }
+
+    return FALSE;
+}
+#endif
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+    HWI_PROC_FUNC pfnHandler;
+    VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+    }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+    }
+}
+#endif
+
+/* ****************************************************************************
+ Function    : HwiNumGet
+ Description : Get an interrupt number
+ Input       : None
+ Output      : None
+ Return      : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+    return __get_IPSR();
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+    return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function    : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+/*lint -e529*/
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+    while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+    UINT32 hwiIndex;
+    UINT32 intSave;
+
+#if (LOSCFG_KERNEL_RUNSTOP == 1)
+    SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
+#endif
+
+    intSave = LOS_IntLock();
+    g_intCount++;
+    LOS_IntRestore(intSave);
+
+    hwiIndex = HwiNumGet();
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
+    OsCpupIrqStart(hwiIndex);
+#endif
+
+    HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+        g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+    }
+#else
+    if (g_hwiHandlerForm[hwiIndex] != 0) {
+        g_hwiHandlerForm[hwiIndex]();
+    }
+#endif
+
+#if (LOSCFG_DEBUG_TOOLS == 1)
+    ++g_hwiFormCnt[hwiIndex];
+#endif
+
+    HalAftInterruptHandler(hwiIndex);
+
+#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
+    OsCpupIrqEnd(hwiIndex);
+#endif
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+    intSave = LOS_IntLock();
+    g_intCount--;
+    LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiCreate
+ Description : create hardware interrupt
+ Input       : hwiNum   --- hwi num to create
+               hwiPrio  --- priority of the hwi
+               hwiMode  --- unused
+               hwiHandler --- hwi handler
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T hwiMode,
+                                           HWI_PROC_FUNC hwiHandler,
+                                           HwiIrqParam *irqParam)
+{
+    (VOID)hwiMode;
+    UINT32 intSave;
+
+    if (hwiHandler == NULL) {
+        return OS_ERRNO_HWI_PROC_FUNC_NULL;
+    }
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return OS_ERRNO_HWI_ALREADY_CREATED;
+    }
+
+    if (hwiPrio > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (irqParam != NULL) {
+        OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+    } else {
+        OsSetVector(hwiNum, hwiHandler, NULL);
+    }
+#else
+    (VOID)irqParam;
+    OsSetVector(hwiNum, hwiHandler);
+#endif
+
+#if (LOSCFG_DEBUG_TOOLS == 1)
+    if ((irqParam != NULL) && (irqParam->pName != NULL)) {
+        g_hwiFormName[hwiNum + OS_SYS_VECTOR_CNT] = (CHAR *)irqParam->pName;
+    }
+    g_hwiFormCnt[hwiNum + OS_SYS_VECTOR_CNT] = 0;
+#endif
+
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input       : hwiNum   --- hwi num to delete
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+    (VOID)irqParam;
+    UINT32 intSave;
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    intSave = LOS_IntLock();
+
+    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+#define FAULT_STATUS_REG_BIT            32
+#define USGFAULT                        (1 << 18)
+#define BUSFAULT                        (1 << 17)
+#define MEMFAULT                        (1 << 16)
+#define DIV0FAULT                       (1 << 4)
+#define UNALIGNFAULT                    (1 << 3)
+#define HARDFAULT_IRQN                  (-13)
+
+ExcInfo g_excInfo = {0};
+
+UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
+    0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
+    0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
+    0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
+    0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
+};
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcNvicDump(VOID)
+{
+#define OS_NR_NVIC_EXC_DUMP_TYPES   7
+    UINT32 *base = NULL;
+    UINT32 len, i, j;
+    UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
+        OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
+    };
+    UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
+        OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
+        OS_NVIC_INT_CTRL_SIZE
+    };
+    CHAR strRgEnable[] = "enable";
+    CHAR strRgPending[] = "pending";
+    CHAR strRgActive[] = "active";
+    CHAR strRgPriority[] = "priority";
+    CHAR strRgException[] = "exception";
+    CHAR strRgShcsr[] = "shcsr";
+    CHAR strRgIntCtrl[] = "control";
+    CHAR *strRgs[] = {
+        strRgEnable, strRgPending, strRgActive, strRgPriority,
+        strRgException, strRgShcsr, strRgIntCtrl
+    };
+
+    PRINTK("\r\nOS exception NVIC dump:\n");
+    for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
+        base = (UINT32 *)rgNvicBases[i];
+        len = rgNvicLens[i];
+        PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
+        len = (len >> 2); /* 2: Gets the next register offset */
+        for (j = 0; j < len; j++) {
+            PRINTK("0x%x ", *(base + j));
+            if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
+                PRINTK("\n");
+            }
+        }
+        PRINTK("\n");
+    }
+}
+
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+    CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+    PRINTK("Type      = %d\n", excInfo->type);
+    PRINTK("ThrdPid   = %d\n", excInfo->thrdPid);
+    PRINTK("Phase     = %s\n", phaseStr[excInfo->phase]);
+    PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Current task info:\n");
+    if (excInfo->phase == OS_EXC_IN_TASK) {
+        LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+        PRINTK("Task name = %s\n", taskCB->taskName);
+        PRINTK("Task ID   = %d\n", taskCB->taskID);
+        PRINTK("Task SP   = %p\n", taskCB->stackPointer);
+        PRINTK("Task ST   = 0x%x\n", taskCB->topOfStack);
+        PRINTK("Task SS   = 0x%x\n", taskCB->stackSize);
+    } else if (excInfo->phase == OS_EXC_IN_HWI) {
+        PRINTK("Exception occur in interrupt phase!\n");
+    } else {
+        PRINTK("Exception occur in system init phase!\n");
+    }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Exception reg dump:\n");
+    PRINTK("PC        = 0x%x\n", excInfo->context->uwPC);
+    PRINTK("LR        = 0x%x\n", excInfo->context->uwLR);
+    PRINTK("SP        = 0x%x\n", excInfo->context->uwSP);
+    PRINTK("R0        = 0x%x\n", excInfo->context->uwR0);
+    PRINTK("R1        = 0x%x\n", excInfo->context->uwR1);
+    PRINTK("R2        = 0x%x\n", excInfo->context->uwR2);
+    PRINTK("R3        = 0x%x\n", excInfo->context->uwR3);
+    PRINTK("R4        = 0x%x\n", excInfo->context->uwR4);
+    PRINTK("R5        = 0x%x\n", excInfo->context->uwR5);
+    PRINTK("R6        = 0x%x\n", excInfo->context->uwR6);
+    PRINTK("R7        = 0x%x\n", excInfo->context->uwR7);
+    PRINTK("R8        = 0x%x\n", excInfo->context->uwR8);
+    PRINTK("R9        = 0x%x\n", excInfo->context->uwR9);
+    PRINTK("R10       = 0x%x\n", excInfo->context->uwR10);
+    PRINTK("R11       = 0x%x\n", excInfo->context->uwR11);
+    PRINTK("R12       = 0x%x\n", excInfo->context->uwR12);
+    PRINTK("PriMask   = 0x%x\n", excInfo->context->uwPriMask);
+    PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+    UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+    UINT32 index;
+
+    OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
+
+    PRINTK("----- backtrace start -----\n");
+    for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+        if (LR[index] == 0) {
+            break;
+        }
+        PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
+    }
+    PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+    PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+    MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+    UINT32 errCnt;
+    UINT32 i;
+
+    (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+    errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+    if (errCnt < OS_SYS_MEM_NUM) {
+        errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+    }
+
+    if (errCnt == 0) {
+        PRINTK("all memory pool check passed!\n");
+        return;
+    }
+
+    for (i = 0; i < errCnt; i++) {
+        PRINTK("pool num    = %d\n", i);
+        PRINTK("pool type   = %d\n", memExcInfo[i].type);
+        PRINTK("pool addr   = 0x%x\n", memExcInfo[i].startAddr);
+        PRINTK("pool size   = 0x%x\n", memExcInfo[i].size);
+        PRINTK("pool free   = 0x%x\n", memExcInfo[i].free);
+        PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
+        PRINTK("pool error node addr  = 0x%x\n", memExcInfo[i].errorAddr);
+        PRINTK("pool error node len   = 0x%x\n", memExcInfo[i].errorLen);
+        PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
+    }
+#endif
+    UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+    if (ret == LOS_OK) {
+        PRINTK("system heap memcheck over, all passed!\n");
+    }
+
+    PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+    PRINTK("*************Exception Information**************\n");
+    OsExcTypeInfo(excInfo);
+    OsExcCurTaskInfo(excInfo);
+    OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+    OsExcBackTraceInfo(excInfo);
+#endif
+    OsGetAllTskInfo();
+    OsExcNvicDump();
+    OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+    UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
+    g_intCount++;
+    g_excInfo.nestCnt++;
+
+    g_excInfo.type = excType & OS_NULL_SHORT;
+
+    if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
+        g_excInfo.faultAddr = faultAddr;
+    } else {
+        g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+    }
+    if (g_losTask.runTask != NULL) {
+        if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
+            g_excInfo.phase = OS_EXC_IN_HWI;
+            g_excInfo.thrdPid = pid;
+        } else {
+            g_excInfo.phase = OS_EXC_IN_TASK;
+            g_excInfo.thrdPid = g_losTask.runTask->taskID;
+        }
+    } else {
+        g_excInfo.phase = OS_EXC_IN_INIT;
+        g_excInfo.thrdPid = OS_NULL_INT;
+    }
+    if (excType & OS_EXC_FLAG_NO_FLOAT) {
+        g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
+    } else {
+        g_excInfo.context = excBufAddr;
+    }
+
+    OsDoExcHook(EXC_INTERRUPT);
+    OsExcInfoDisplay(&g_excInfo);
+    ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function    : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    UINT32 index;
+    g_hwiForm[0] = 0; /* [0] Top of Stack */
+    g_hwiForm[1] = 0; /* [1] reset */
+    for (index = DEF_HANDLER_START_INDEX; index < OS_VECTOR_CNT; index++) {
+        g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+    }
+    /* Exception handler register */
+    g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT]   = (HWI_PROC_FUNC)HalExcNMI;
+    g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT]        = (HWI_PROC_FUNC)HalExcHardFault;
+    g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault;
+    g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT]         = (HWI_PROC_FUNC)HalExcBusFault;
+    g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT]       = (HWI_PROC_FUNC)HalExcUsageFault;
+    g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT]           = (HWI_PROC_FUNC)HalSVCHandler;
+    g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT]           = (HWI_PROC_FUNC)HalPendSV;
+    g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT]          = (HWI_PROC_FUNC)OsTickHandler;
+
+    /* Interrupt vector table location */
+    SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
+#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
+    NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
+#endif
+
+    /* Enable USGFAULT, BUSFAULT, MEMFAULT */
+    *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+
+    /* Enable DIV 0 and unaligned exception */
+#ifdef LOSCFG_ARCH_UNALIGNED_EXC
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
+#else
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
+#endif
+
+    return;
+}
+
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_timer.c
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_timer.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "los_tick.h"
+#include "los_arch_interrupt.h"
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+    UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
+
+    tick->freq = OS_SYS_CLOCK;
+
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
+#else
+    OsSetVector(tick->irqNum, handler);
+#endif
+#endif
+
+    ret = SysTick_Config(g_cyclesPerTick);
+    if (ret == 1) {
+        return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
+    }
+
+    return LOS_OK;
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+    if (nextResponseTime > g_archTickTimer.periodMax) {
+        nextResponseTime = g_archTickTimer.periodMax;
+    }
+
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
+    SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+    UINT32 hwCycle = 0;
+    UINT32 intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
+    *period = SysTick->LOAD;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
+    LOS_IntRestore(intSave);
+    return (UINT64)hwCycle;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return LOS_OK;
+}
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_trustzone.c
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_trustzone.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_trustzone.h"
+#include "los_secure_macros.h"
+#include "los_secure_context.h"
+#include "los_debug.h"
+#include "los_arch_context.h"
+#include "los_interrupt.h"
+
+OsSecureContext *g_secureContext = NULL;
+
+VOID HalSecureSVCHandler(UINT32 svcID, UINTPTR arg)
+{
+    switch (svcID) {
+        case OS_SVC_START_SCHEDULE:
+            HalSecureContextInit();
+            HalStartFirstTask();
+            break;
+        case OS_SVC_ALLOCATE_SECURE_CONTEXT:
+            g_secureContext = HalSecureContextAlloc(arg);
+            LOS_ASSERT(g_secureContext != NULL);
+            HalSecureContextLoad(g_secureContext);
+            break;
+        case OS_SVC_FREE_SECURE_CONTEXT:
+            LOS_ASSERT(g_secureContext != NULL);
+            HalSecureContextFree(g_secureContext);
+            break;
+        default:
+            PRINT_ERR("Incorrect svc id = %u\n", svcID);
+            break;
+    }
+}
+
+VOID HalStartToRun(VOID)
+{
+    HalSVCStartSchedule();
+}
+
+VOID LOS_SecureContextAlloc(UINT32 secureStackSize)
+{
+    if (secureStackSize == 0) {
+        return;
+    }
+
+    LOS_ASSERT((__get_IPSR() == 0) && (__get_PRIMASK() == 0));
+    secureStackSize = LOS_Align(secureStackSize, sizeof(UINTPTR));
+    HalSVCSecureContextAlloc(secureStackSize);
+}
+
+VOID LOS_SecureContextFree(VOID)
+{
+    HalSVCSecureContextFree();
+}
+
--- a/arch/arm/cortex-m55/gcc/TZ/non_secure/los_trustzone.h
+++ b/arch/arm/cortex-m55/gcc/TZ/non_secure/los_trustzone.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_TRUSTZONE_H
+#define _LOS_TRUSTZONE_H
+
+#include "los_config.h"
+#include "los_task.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+extern VOID LOS_SecureContextAlloc(UINT32 secureStackSize);
+extern VOID LOS_SecureContextFree(VOID);
+
+extern VOID HalStartFirstTask(VOID);
+extern VOID HalSVCStartSchedule(VOID);
+extern VOID HalSVCSecureContextAlloc(UINT32 secureStackSize);
+extern VOID HalSVCSecureContextFree(VOID);
+extern VOID HalSVCHandler(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
+
--- a/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_context.c
+++ b/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_context.c
@@ -1,113 +1,98 @@
-/*
- * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "securec.h"
-#include "los_config.h"
-#include "los_memory.h"
-#include <malloc.h>
-
-void *zalloc(size_t size)
-{
-    void *ptr = NULL;
-
-    if (size == 0) {
-        return NULL;
-    }
-
-    ptr = LOS_MemAlloc(OS_SYS_MEM_ADDR, size);
-    if (ptr != NULL) {
-        (void)memset_s(ptr, size, 0, size);
-    }
-    return ptr;
-}
-
-void __wrap__free_r(struct _reent *reent, void *aptr)
-{
-    if (aptr == NULL) {
-        return;
-    }
-
-    LOS_MemFree(OS_SYS_MEM_ADDR, aptr);
-}
-
-size_t __wrap__malloc_usable_size_r(struct _reent *reent, void *aptr)
-{
-    return 0;
-}
-
-void *__wrap__malloc_r(struct _reent *reent, size_t nbytes)
-{
-    if (nbytes == 0) {
-        return NULL;
-    }
-
-    return LOS_MemAlloc(OS_SYS_MEM_ADDR, nbytes);
-}
-
-void *__wrap__memalign_r(struct _reent *reent, size_t align, size_t nbytes)
-{
-    if (nbytes == 0) {
-        return NULL;
-    }
-
-    return LOS_MemAllocAlign(OS_SYS_MEM_ADDR, nbytes, align);
-}
-
-void *__wrap__realloc_r(struct _reent *reent, void *aptr, size_t nbytes)
-{
-    if (aptr == NULL) {
-        return malloc(nbytes);
-    }
-
-    if (nbytes == 0) {
-        free(aptr);
-        return NULL;
-    }
-
-    return LOS_MemRealloc(OS_SYS_MEM_ADDR, aptr, nbytes);
-}
-
-void *__wrap__calloc_r(struct _reent *reent, size_t nitems, size_t size)
-{
-    size_t real_size;
-    void *ptr = NULL;
-
-    if (nitems == 0 || size == 0) {
-        return NULL;
-    }
-
-    real_size = (size_t)(nitems * size);
-    ptr = LOS_MemAlloc(OS_SYS_MEM_ADDR, real_size);
-    if (ptr != NULL) {
-        (void)memset_s(ptr, real_size, 0, real_size);
-    }
-    return ptr;
-}
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_secure_context.h"
+#include "los_secure_macros.h"
+#include "los_secure_heap.h"
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextInit(VOID)
+{
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return;
+    }
+
+    HalSecureContextInitAsm();
+}
+
+OS_CMSE_NS_ENTRY OsSecureContext *HalSecureContextAlloc(UINT32 size)
+{
+    OsSecureContext *secureContext = NULL;
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return NULL;
+    }
+
+    secureContext = HalSecureMalloc(sizeof(OsSecureContext));
+    if (secureContext == NULL) {
+        return NULL;
+    }
+
+    secureContext->stackLimit = HalSecureMalloc(size);
+    if (secureContext->stackLimit == NULL) {
+        HalSecureFree(secureContext);
+        return NULL;
+    }
+
+    secureContext->stackStart = secureContext->stackLimit + size;
+    secureContext->curStackPointer = secureContext->stackStart;
+
+    return secureContext;
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextFree(OsSecureContext *secureContext)
+{
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return;
+    }
+
+    HalSecureFree(secureContext->stackLimit);
+    secureContext->stackLimit = NULL;
+    HalSecureFree(secureContext);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextLoad(OsSecureContext *secureContext)
+{
+    HalSecureContextLoadAsm(secureContext);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextSave(OsSecureContext *secureContext)
+{
+    HalSecureContextSaveAsm(secureContext);
+}
+
--- a/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_context.h
+++ b/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_context.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_SECURE_CONTEXT_H
+#define _LOS_SECURE_CONTEXT_H
+
+#include "los_config.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct {
+    UINT8 *curStackPointer;
+    UINT8 *stackLimit;
+    UINT8 *stackStart;
+} OsSecureContext;
+
+extern VOID HalSecureContextInit(VOID);
+extern OsSecureContext *HalSecureContextAlloc(UINT32 size);
+extern VOID HalSecureContextFree(OsSecureContext *secureContext);
+extern VOID HalSecureContextLoad(OsSecureContext *secureContext);
+extern VOID HalSecureContextSave(OsSecureContext *secureContext);
+
+extern VOID HalSecureContextInitAsm(VOID);
+extern VOID HalSecureContextLoadAsm(OsSecureContext *secureContext);
+extern VOID HalSecureContextSaveAsm(OsSecureContext *secureContext);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
--- a/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_context_asm.S
+++ b/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_context_asm.S
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .syntax unified
+ .arch armv8.1-m.main
+ .fpu vfpv3-d16-fp16
+ .thumb
+
+.equ OS_SECURE_SCB_AIRCR,    0xE000ED0C
+
+    .section .text
+    .thumb
+
+    .type HalSecureContextInitAsm, %function
+    .global HalSecureContextInitAsm
+HalSecureContextInitAsm:
+    .fnstart
+    .cantunwind
+    LDR     R0, =OS_SECURE_SCB_AIRCR
+    LDR     R1, [R0]
+
+    MOV     R2, #0xFFFF
+    LSL     R2, R2, #16
+    BIC     R1, R1, R2
+    MOV     R2, #0x05FA
+    LSL     R2, R2, #16
+    ORR     R1, R1, R2
+
+    BIC     R1, R1, #0x4000
+    MOV     R2, #0x4000
+    ORR     R1, R1, R2
+    STR     R1, [R0]
+
+    MOV     R0, #0
+    MSR     PSPLIM, R0
+    MSR     PSP, R0
+    MOV     R0, #2
+    MSR     CONTROL, R0 
+    BX      LR
+    .fnend
+
+    .type HalSecureContextLoadAsm, %function
+    .global HalSecureContextLoadAsm
+HalSecureContextLoadAsm:
+    .fnstart
+    .cantunwind
+    MRS     R1, IPSR
+    CBZ     R1, __ThreadMode
+
+    LDMIA   R0!, {R1, R2}               /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext->stackLimit. */
+    MSR     PSPLIM, R2                  /* Restore PSPLIM. */
+    MSR     PSP, R1                     /* Restore PSP. */
+    BX      LR
+    .fnend
+    
+    .type HalSecureContextSaveAsm, %function
+    .global HalSecureContextSaveAsm
+HalSecureContextSaveAsm:
+    .fnstart
+    .cantunwind
+    MRS     R0, IPSR
+    CBZ     R0, __ThreadMode
+
+    MRS     R0, PSP
+    STR     R0, [R1]                    /* g_secureContext->curStackPointer = R0. */
+    MOV     R0, #0
+    MSR     PSPLIM, R0                  /* No PSPLIM for the current task. */
+    MSR     PSP, R0                     /* No secure stack for the current task. */
+    .fnend
+
+__ThreadMode:
+    BX      LR
--- a/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_heap.c
+++ b/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_heap.c
@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_secure_heap.h"
+#include "los_secure_macros.h"
+#include "los_config.h"
+#include "los_list.h"
+
+STATIC UINT8 __attribute__((aligned(0x4)))g_secureHeap[LOSCFG_SECURE_HEAP_SIZE] = {0};
+STATIC LOS_DL_LIST g_secureHeapFreeList = {NULL, NULL};
+
+struct OsSecureHeapNode {
+    LOS_DL_LIST freeNode;
+    struct OsSecureHeapNode *preNode;
+    UINT32 size : 24;
+    UINT32 used : 8;
+};
+
+#define OS_SECURE_HEAP_NODE_HEAD_SIZE   sizeof(struct OsSecureHeapNode)
+#define OS_SECURE_HEAP_ALIGN_SIZE       sizeof(UINTPTR)
+
+#define OS_SECURE_HEAP_NODE_USED        1
+#define OS_SECURE_HEAP_NODE_FREE        0
+
+#define OS_SECURE_HEAP_FIRST_NODE     ((struct OsSecureHeapNode *)g_secureHeap)
+#define OS_SECURE_HEAP_NEXT_NODE(node) \
+    ((struct OsSecureHeapNode *)((UINT8 *)(node) + (node)->size))
+#define OS_SECURE_HEAP_END_NODE \
+    ((struct OsSecureHeapNode *)((UINT8 *)g_secureHeap + LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE))
+
+STATIC INLINE VOID OsSecureHeapListInit(LOS_DL_LIST *head)
+{
+    head->pstPrev = head;
+    head->pstNext = head;
+}
+
+STATIC INLINE VOID OsSecureHeapListDelete(LOS_DL_LIST *node)
+{
+    node->pstNext->pstPrev = node->pstPrev;
+    node->pstPrev->pstNext = node->pstNext;
+    node->pstNext = NULL;
+    node->pstPrev = NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapListAdd(LOS_DL_LIST *listNode, LOS_DL_LIST *node)
+{
+    node->pstNext = listNode->pstNext;
+    node->pstPrev = listNode;
+    listNode->pstNext->pstPrev = node;
+    listNode->pstNext = node;
+}
+
+STATIC struct OsSecureHeapNode *OsSecureHeapFindSuitableFreeBlock(UINT32 allocSize)
+{
+    LOS_DL_LIST *listNodeHead = &g_secureHeapFreeList;
+    struct OsSecureHeapNode *tmpNode = NULL;
+
+    LOS_DL_LIST_FOR_EACH_ENTRY(tmpNode, listNodeHead, struct OsSecureHeapNode, freeNode) {
+        if (tmpNode->size >= allocSize) {
+            return tmpNode;
+        }
+    }
+
+    return NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapClearNode(struct OsSecureHeapNode *node)
+{
+    node->preNode = NULL;
+    node->size = 0;
+    node->used = 0;
+    node->freeNode.pstPrev = NULL;
+    node->freeNode.pstNext = NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapMergeNode(struct OsSecureHeapNode *node)
+{
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    node->preNode->size += node->size;
+    nextNode = (struct OsSecureHeapNode *)((UINTPTR)node + node->size);
+    nextNode->preNode = node->preNode;
+    OsSecureHeapClearNode(node);
+}
+
+STATIC INLINE VOID OsSecureHeapSplitNode(struct OsSecureHeapNode *allocNode, UINT32 allocSize)
+{
+    struct OsSecureHeapNode *newFreeNode = NULL;
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    newFreeNode = (struct OsSecureHeapNode *)((UINT8 *)allocNode + allocSize);
+    newFreeNode->preNode = allocNode;
+    newFreeNode->size = allocNode->size - allocSize;
+    newFreeNode->used = OS_SECURE_HEAP_NODE_FREE;
+    allocNode->size = allocSize;
+    nextNode = OS_SECURE_HEAP_NEXT_NODE(newFreeNode);
+    nextNode->preNode = newFreeNode;
+    if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+        OsSecureHeapListDelete(&nextNode->freeNode);
+        OsSecureHeapMergeNode(nextNode);
+    }
+
+    OsSecureHeapListAdd(&g_secureHeapFreeList, &newFreeNode->freeNode);
+}
+
+STATIC INLINE VOID OsSecureHeapFreeNode(struct OsSecureHeapNode *node)
+{
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    if ((node->preNode != NULL) && (node->preNode->used == OS_SECURE_HEAP_NODE_FREE)) {
+        struct OsSecureHeapNode *preNode = node->preNode;
+        OsSecureHeapMergeNode(node);
+        nextNode = OS_SECURE_HEAP_NEXT_NODE(preNode);
+        if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+            OsSecureHeapListDelete(&nextNode->freeNode);
+            OsSecureHeapMergeNode(nextNode);
+        }
+
+        OsSecureHeapListDelete(&preNode->freeNode);
+        preNode->used = OS_SECURE_HEAP_NODE_FREE;
+        OsSecureHeapListAdd(&g_secureHeapFreeList, &preNode->freeNode);
+    } else {
+        nextNode = OS_SECURE_HEAP_NEXT_NODE(node);
+        if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+            OsSecureHeapListDelete(&nextNode->freeNode);
+            OsSecureHeapMergeNode(nextNode);
+        }
+
+        node->used = OS_SECURE_HEAP_NODE_FREE;
+        OsSecureHeapListAdd(&g_secureHeapFreeList, &node->freeNode);
+    }
+}
+
+STATIC INLINE VOID *OsSecureHeapAllocNode(UINT32 size)
+{
+    struct OsSecureHeapNode *allocNode = NULL;
+    UINT32 allocSize;
+
+    allocSize = LOS_Align(size + OS_SECURE_HEAP_NODE_HEAD_SIZE, OS_SECURE_HEAP_ALIGN_SIZE);
+    allocNode = OsSecureHeapFindSuitableFreeBlock(allocSize);
+    if (allocNode == NULL) {
+        return NULL;
+    }
+    if ((allocSize + OS_SECURE_HEAP_NODE_HEAD_SIZE + OS_SECURE_HEAP_ALIGN_SIZE) <= allocNode->size) {
+        OsSecureHeapSplitNode(allocNode, allocSize);
+    }
+    OsSecureHeapListDelete(&allocNode->freeNode);
+    allocNode->used = OS_SECURE_HEAP_NODE_USED;
+
+    return (allocNode + 1);
+}
+
+STATIC INLINE VOID OsSecureHeapInit(VOID)
+{
+    struct OsSecureHeapNode *newNode = NULL;
+    struct OsSecureHeapNode *endNode = NULL;
+
+    newNode = OS_SECURE_HEAP_FIRST_NODE;
+    newNode->size = LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE;
+    newNode->preNode = OS_SECURE_HEAP_END_NODE;
+    newNode->used = OS_SECURE_HEAP_NODE_FREE;
+
+    OsSecureHeapListInit(&g_secureHeapFreeList);
+    OsSecureHeapListAdd(&g_secureHeapFreeList, &newNode->freeNode);
+
+    endNode = OS_SECURE_HEAP_END_NODE;
+    endNode->preNode = newNode;
+    endNode->size = OS_SECURE_HEAP_NODE_HEAD_SIZE;
+    endNode->used = OS_SECURE_HEAP_NODE_USED;
+}
+
+OS_CMSE_NS_ENTRY VOID *HalSecureMalloc(UINT32 size)
+{
+    if (size == 0) {
+        return NULL;
+    }
+
+    if ((g_secureHeapFreeList.pstPrev == NULL) &&
+        (g_secureHeapFreeList.pstNext == NULL)) {
+        OsSecureHeapInit();
+    }
+
+    return OsSecureHeapAllocNode(size);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureFree(VOID *ptr)
+{
+    struct OsSecureHeapNode *node = NULL;
+
+    if (ptr == NULL) {
+        return;
+    }
+
+    node = (struct OsSecureHeapNode *)((UINTPTR)ptr - OS_SECURE_HEAP_NODE_HEAD_SIZE);
+    if (node->used != OS_SECURE_HEAP_NODE_USED) {
+        return;
+    }
+
+    OsSecureHeapFreeNode(node);
+}
+
--- a/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_heap.h
+++ b/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_heap.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_SECURE_HEAP_H
+#define _LOS_SECURE_HEAP_H
+
+#include "los_config.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+VOID *HalSecureMalloc(UINT32 size);
+VOID HalSecureFree(VOID *ptr);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
+
--- a/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_macros.h
+++ b/arch/arm/cortex-m55/gcc/TZ/secure/los_secure_macros.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_SECURE_MACROS_H
+#define _LOS_SECURE_MACROS_H
+
+#include "los_config.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#define OS_CMSE_NS_ENTRY      __attribute__((cmse_nonsecure_entry))
+#define OS_CMSE_NS_CALL       __attribute__((cmse_nonsecure_call))
+#define OS_IPSR_READ(ipsr)    __asm volatile("MRS %0, IPSR" : "=r" (ipsr))
+
+#define OS_SVC_ALLOCATE_SECURE_CONTEXT  0
+#define OS_SVC_FREE_SECURE_CONTEXT      1
+#define OS_SVC_START_SCHEDULE           2
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
+
--- a/arch/arm/cortex-m55/iar/BUILD.gn
+++ b/arch/arm/cortex-m55/iar/BUILD.gn
@@ -27,13 +27,12 @@
 # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-if LIBC_MUSL
+import("//kernel/liteos_m/liteos.gni")

-config LIBC_MUSL_FS
-    bool "Enable POSIX file system API support"
-    default y
-    depends on FS_VFS
-    help
-        This enables POSIX style file system related APIs.
-
-endif # LIBC_MUSL
+module_group("iar") {
+  if (defined(LOSCFG_SECURE_TRUSTZONE)) {
+    modules = [ "TZ" ]
+  } else {
+    modules = [ "NTZ" ]
+  }
+}
--- a/arch/arm/cortex-m55/iar/NTZ/BUILD.gn
+++ b/arch/arm/cortex-m55/iar/NTZ/BUILD.gn
@@ -27,13 +27,20 @@
 # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-if LIBC_NEWLIB
+import("//kernel/liteos_m/liteos.gni")

-config LIBC_NEWLIB_FS
-    bool "Enable POSIX file system API support"
-    default y
-    depends on FS_VFS
-    help
-        This enables POSIX style file system related APIs.
+module_name = "arch"
+kernel_module(module_name) {
+  sources = [
+    "los_context.c",
+    "los_dispatch.S",
+    "los_exc.S",
+    "los_interrupt.c",
+    "los_timer.c",
+  ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
+}

-endif # LIBC_NEWLIB
+config("public") {
+  include_dirs = [ "." ]
+}
--- a/arch/arm/cortex-m55/iar/NTZ/los_arch_atomic.h
+++ b/arch/arm/cortex-m55/iar/NTZ/los_arch_atomic.h
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    asm volatile("ldrex %0, [%1]\n"
+                 : "=&r"(val)
+                 : "r"(v)
+                 : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %0, [%1]\n"
+                     "strex %0, %2, [%1]\n"
+                     : "=&r"(status)
+                     : "r"(v), "r"(setVal)
+                     : "cc");
+    } while (status != 0);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "add %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(addVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "sub %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(subVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        asm volatile("ldrex %0, [%2]\n"
+                     "strex %1, %3, [%2]"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        asm volatile("ldrex %0, [%2]\n"
+                     "mov %1, #0\n"
+                     "cmp %0, %3\n"
+                     "bne 1f\n"
+                     "strex %1, %4, [%2]\n"
+                     "1:"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(oldVal), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */
--- a/targets/riscv_nuclei_demo_soc_gcc/Src/task_sample.c
+++ b/targets/riscv_nuclei_demo_soc_gcc/Src/task_sample.c
@@ -1,7 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- * Copyright (c) 2021 Nuclei Limited. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -28,16 +27,13 @@
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Description: Provide a task example.
 */

-#include "task_sample.h"
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
 #include "los_config.h"
-#include "los_debug.h"
-#include "los_interrupt.h"
-#include "los_task.h"
-#include "los_tick.h"
+#include "los_compiler.h"

 #ifdef __cplusplus
 #if __cplusplus
@@ -45,62 +41,91 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */

-UINT8 __attribute__ ((aligned (8))) g_memStart[OS_SYS_MEM_SIZE];
+typedef struct TagTskContext {
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} TaskContext;

-VOID TaskSampleEntry2(VOID)
-{
-    while (1) {
-        printf("TaskSampleEntry2 running...\n");
-        LOS_TaskDelay(10000); /* 10 Seconds */
-    }
-}
-
-VOID TaskSampleEntry1(VOID)
-{
-    while (1) {
-        printf("TaskSampleEntry1 running...\n");
-        LOS_TaskDelay(2000); /* 2 Seconds */
-    }
-}
-
-VOID TaskSample(VOID)
-{
-    UINT32 uwRet;
-    UINT32 taskID1;
-    UINT32 taskID2;
-    TSK_INIT_PARAM_S stTask = {0};
-
-    stTask.pfnTaskEntry = (TSK_ENTRY_FUNC)TaskSampleEntry1;
-    stTask.uwStackSize = 0x1000;
-    stTask.pcName = "TaskSampleEntry1";
-    stTask.usTaskPrio = 6; /* Os task priority is 6 */
-    uwRet = LOS_TaskCreate(&taskID1, &stTask);
-    if (uwRet != LOS_OK) {
-        printf("Task1 create failed\n");
-    }
-
-    stTask.pfnTaskEntry = (TSK_ENTRY_FUNC)TaskSampleEntry2;
-    stTask.uwStackSize = 0x1000;
-    stTask.pcName = "TaskSampleEntry2";
-    stTask.usTaskPrio = 7; /* Os task priority is 7 */
-    uwRet = LOS_TaskCreate(&taskID2, &stTask);
-    if (uwRet != LOS_OK) {
-        printf("Task2 create failed\n");
-    }
-}
-
-VOID RunTaskSample(VOID)
-{
-    UINT32 ret;
-    ret = LOS_KernelInit();
-    if (ret == LOS_OK) {
-        TaskSample();
-        LOS_Start();
-    }
-}
+/**
+ * @ingroup  los_config
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);

 #ifdef __cplusplus
 #if __cplusplus
 }
 #endif /* __cplusplus */
 #endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */
+
--- a/arch/arm/cortex-m55/iar/NTZ/los_arch_interrupt.h
+++ b/arch/arm/cortex-m55/iar/NTZ/los_arch_interrupt.h
@@ -0,0 +1,684 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_EXC_H
+#define _LOS_EXC_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_hwi
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_hwi
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST                   0
+#endif
+
+/* *
+ * @ingroup los_hwi
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST                    7
+#endif
+
+
+/* *
+ * @ingroup  los_hwi
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_hwi
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_hwi
+ * Count of M-Core system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT                     16
+
+/* *
+ * @ingroup los_hwi
+ * Count of M-Core interrupt vector.
+ */
+#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_hwi
+ * AIRCR register priority group parameter .
+ */
+#define OS_NVIC_AIRCR_PRIGROUP                7
+
+/* *
+ * @ingroup los_hwi
+ * Boot interrupt vector table.
+ */
+extern UINT32 _BootVectors[];
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+/* *
+ * @ingroup los_hwi
+ * SysTick control and status register.
+ */
+#define OS_SYSTICK_CONTROL_REG                0xE000E010
+
+/* *
+ * @ingroup los_hw
+ * SysTick current value register.
+ */
+#define OS_SYSTICK_CURRENT_REG                0xE000E018
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt Priority-Level Registers.
+ */
+#define OS_NVIC_PRI_BASE                      0xE000E400
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt enable register for 0-31.
+ */
+#define OS_NVIC_SETENA_BASE                   0xE000E100
+
+/* *
+ * @ingroup los_hwi
+ * interrupt pending register.
+ */
+#define OS_NVIC_SETPEND_BASE                  0xE000E200
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt active register.
+ */
+#define OS_NVIC_INT_ACT_BASE                  0xE000E300
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt disable register for 0-31.
+ */
+#define OS_NVIC_CLRENA_BASE                   0xE000E180
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt control and status register.
+ */
+#define OS_NVIC_INT_CTRL                      0xE000ED04
+
+/* *
+ * @ingroup los_hwi
+ * Vector table offset register.
+ */
+#define OS_NVIC_VTOR                          0xE000ED08
+
+/* *
+ * @ingroup los_hwi
+ * Application interrupt and reset control register
+ */
+#define OS_NVIC_AIRCR                         0xE000ED0C
+
+/* *
+ * @ingroup los_hwi
+ * System exception priority register.
+ */
+#define OS_NVIC_EXCPRI_BASE                   0xE000ED18
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 1 :reset.
+ */
+#define OS_EXC_RESET                          1
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 2 :Non-Maskable Interrupt.
+ */
+#define OS_EXC_NMI                            2
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 3 :(hard)fault.
+ */
+#define OS_EXC_HARD_FAULT                     3
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 4 :MemManage fault.
+ */
+#define OS_EXC_MPU_FAULT                      4
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 5 :Bus fault.
+ */
+#define OS_EXC_BUS_FAULT                      5
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 6 :Usage fault.
+ */
+#define OS_EXC_USAGE_FAULT                    6
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 11 :SVCall.
+ */
+#define OS_EXC_SVC_CALL                       11
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 12 :Debug monitor.
+ */
+#define OS_EXC_DBG_MONITOR                    12
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 14 :PendSV.
+ */
+#define OS_EXC_PEND_SV                        14
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 15 :SysTick.
+ */
+#define OS_EXC_SYS_TICK                       15
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li
+></ul>
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Reset the vector table.
+ *
+ * @par Description:
+ * This API is used to reset the vector table.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID Reset_Handler(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Pended System Call.
+ *
+ * @par Description:
+ * PendSV can be pended and is useful for an OS to pend an exception
+ * so that an action can be performed after other important tasks are completed.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalPendSV(VOID);
+
+
+#define OS_EXC_IN_INIT                      0
+#define OS_EXC_IN_TASK                      1
+#define OS_EXC_IN_HWI                       2
+
+#define OS_EXC_MAX_BUF_LEN                  25
+#define OS_EXC_MAX_NEST_DEPTH               1
+
+#define OS_NVIC_SHCSR                       0xE000ED24
+#define OS_NVIC_CCR                         0xE000ED14
+
+#define OS_NVIC_INT_ENABLE_SIZE             0x20
+#define OS_NVIC_INT_PRI_SIZE                0xF0
+#define OS_NVIC_EXCPRI_SIZE                 0xC
+#define OS_NVIC_INT_CTRL_SIZE               4
+#define OS_NVIC_SHCSR_SIZE                  4
+
+#define OS_NVIC_INT_PEND_SIZE               OS_NVIC_INT_ACT_SIZE
+#define OS_NVIC_INT_ACT_SIZE                OS_NVIC_INT_ENABLE_SIZE
+
+#define OS_EXC_FLAG_NO_FLOAT                0x10000000
+#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
+#define OS_EXC_FLAG_IN_HWI                  0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
+
+#define OS_EXC_EVENT                        0x00000001
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
+ */
+typedef struct TagExcContext {
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    /* auto save */
+    UINT32 uwSP;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED) && (__FPU_USED== 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+}EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+
+VOID HalExcNMI(VOID);
+VOID HalExcHardFault(VOID);
+VOID HalExcMemFault(VOID);
+VOID HalExcBusFault(VOID);
+VOID HalExcUsageFault(VOID);
+VOID HalSVCHandler(VOID);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was being pushed.
+ */
+#define OS_EXC_BF_STKERR           1
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was out of the stack.
+ */
+#define OS_EXC_BF_UNSTKERR         2
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register imprecise data access violation.
+ */
+#define OS_EXC_BF_IMPRECISERR      3
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register exact data access violation.
+ */
+#define OS_EXC_BF_PRECISERR        4
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register access violation while pointing.
+ */
+#define OS_EXC_BF_IBUSERR          5
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was being pushed.
+ */
+#define OS_EXC_MF_MSTKERR          6
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
+ */
+#define OS_EXC_MF_MUNSTKERR        7
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register data access violation.
+ */
+#define OS_EXC_MF_DACCVIOL         8
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register access violation.
+ */
+#define OS_EXC_MF_IACCVIOL         9
+
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
+ */
+#define OS_EXC_UF_DIVBYZERO        10
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error, error caused by unaligned access.
+ */
+#define OS_EXC_UF_UNALIGNED        11
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
+ */
+#define OS_EXC_UF_NOCP             12
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
+ */
+#define OS_EXC_UF_INVPC            13
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
+ */
+#define OS_EXC_UF_INVSTATE         14
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
+ */
+#define OS_EXC_UF_UNDEFINSTR       15
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: NMI
+ */
+
+#define OS_EXC_CAUSE_NMI           16
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: hard fault
+ */
+#define OS_EXC_CAUSE_HARDFAULT     17
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: The task handler exits.
+ */
+#define OS_EXC_CAUSE_TASK_EXIT     18
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A fatal error.
+ */
+#define OS_EXC_CAUSE_FATAL_ERR     19
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Hard Fault caused by a debug event.
+ */
+#define OS_EXC_CAUSE_DEBUGEVT      20
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
+ */
+#define OS_EXC_CAUSE_VECTBL        21
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
+ *
+ */
+typedef struct TagExcInfo {
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    UINT16 phase;
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
+    UINT16 type;
+    /**< If the exact address access error indicates the wrong access address when the exception occurred */
+    UINT32 faultAddr;
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    UINT32 thrdPid;
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
+    UINT16 nestCnt;
+    /**< reserve */
+    UINT16 reserved;
+    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+    EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_curNestCount;
+extern UINT32 g_intCount;
+extern UINT8 g_uwExcTbl[32];
+extern ExcInfo g_excInfo;
+
+#define MAX_INT_INFO_SIZE       (8 + 0x164)
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_EXC_H */
--- a/targets/riscv_nuclei_demo_soc_gcc/Src/task_sample.h
+++ b/targets/riscv_nuclei_demo_soc_gcc/Src/task_sample.h
@@ -1,7 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- * Copyright (c) 2021 Nuclei Limited. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -27,15 +26,15 @@
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
- *
- * Description: Provide a task example.
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

-#ifndef _TASKSAMPLE_H
-#define _TASKSAMPLE_H
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H

+#include "los_config.h"
 #include "los_compiler.h"
+#include "los_timer.h"

 #ifdef __cplusplus
 #if __cplusplus
@@ -43,12 +42,11 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */

-VOID RunTaskSample(VOID);
-
 #ifdef __cplusplus
 #if __cplusplus
 }
 #endif /* __cplusplus */
 #endif /* __cplusplus */

-#endif /* _TASKSAMPLE_H */
+#endif /* _LOS_ARCH_TIMER_H */
+
--- a/arch/arm/cortex-m55/iar/NTZ/los_context.c
+++ b/arch/arm/cortex-m55/iar/NTZ/los_context.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
+
+/* ****************************************************************************
+ Function    : ArchInit
+ Description : arch init function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+    HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function    : ArchSysExit
+ Description : Task exit function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+    (VOID)LOS_IntLock();
+    while (1) {
+    }
+}
+
+/* ****************************************************************************
+ Function    : ArchTskStackInit
+ Description : Task stack initialization function
+ Input       : taskID     --- TaskID
+               stackSize  --- Total size of the stack
+               topStack    --- Top of task's stack
+ Output      : None
+ Return      : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
+
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    context->S16 = 0xAA000010;
+    context->S17 = 0xAA000011;
+    context->S18 = 0xAA000012;
+    context->S19 = 0xAA000013;
+    context->S20 = 0xAA000014;
+    context->S21 = 0xAA000015;
+    context->S22 = 0xAA000016;
+    context->S23 = 0xAA000017;
+    context->S24 = 0xAA000018;
+    context->S25 = 0xAA000019;
+    context->S26 = 0xAA00001A;
+    context->S27 = 0xAA00001B;
+    context->S28 = 0xAA00001C;
+    context->S29 = 0xAA00001D;
+    context->S30 = 0xAA00001E;
+    context->S31 = 0xAA00001F;
+    context->S0 = 0xAA000000;
+    context->S1 = 0xAA000001;
+    context->S2 = 0xAA000002;
+    context->S3 = 0xAA000003;
+    context->S4 = 0xAA000004;
+    context->S5 = 0xAA000005;
+    context->S6 = 0xAA000006;
+    context->S7 = 0xAA000007;
+    context->S8 = 0xAA000008;
+    context->S9 = 0xAA000009;
+    context->S10 = 0xAA00000A;
+    context->S11 = 0xAA00000B;
+    context->S12 = 0xAA00000C;
+    context->S13 = 0xAA00000D;
+    context->S14 = 0xAA00000E;
+    context->S15 = 0xAA00000F;
+    context->FPSCR = 0x00000000;
+    context->NO_NAME = 0xAA000011;
+#endif
+
+    context->uwR4 = 0x04040404L;
+    context->uwR5 = 0x05050505L;
+    context->uwR6 = 0x06060606L;
+    context->uwR7 = 0x07070707L;
+    context->uwR8 = 0x08080808L;
+    context->uwR9 = 0x09090909L;
+    context->uwR10 = 0x10101010L;
+    context->uwR11 = 0x11111111L;
+    context->uwPriMask = 0;
+    context->uwR0 = taskID;
+    context->uwR1 = 0x01010101L;
+    context->uwR2 = 0x02020202L;
+    context->uwR3 = 0x03030303L;
+    context->uwR12 = 0x12121212L;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
+    context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
+    context->uwxPSR = 0x01000000L;
+
+    return (VOID *)context;
+}
+
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    UNUSED(stackTop);
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+    return LOS_OK; /* never return */
+}
--- a/arch/arm/cortex-m55/iar/NTZ/los_dispatch.S
+++ b/arch/arm/cortex-m55/iar/NTZ/los_dispatch.S
@@ -0,0 +1,175 @@
+;
+; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this list of
+;    conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice, this list
+;    of conditions and the following disclaimer in the documentation and/or other materials
+;    provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without specific prior written
+;    permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+    PRESERVE8
+
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
+    EXPORT  HalStartToRun
+    EXPORT  ArchTaskSchedule
+    EXPORT  HalPendSV
+    IMPORT  OsSchedTaskSwitch
+    IMPORT  OsSignalTaskContextRestore
+    IMPORT  g_losTask
+
+OS_FPU_CPACR                EQU     0xE000ED88
+OS_FPU_CPACR_ENABLE         EQU     0x00F00000
+OS_NVIC_INT_CTRL            EQU     0xE000ED04
+OS_NVIC_SYSPRI2             EQU     0xE000ED20
+OS_NVIC_PENDSV_PRI          EQU     0xF0F00000
+OS_NVIC_PENDSVSET           EQU     0x10000000
+OS_TASK_STATUS_RUNNING      EQU     0x0010
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+
+    MACRO SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+    ENDM
+
+HalStartToRun
+    LDR     R4, =OS_NVIC_SYSPRI2
+    LDR     R5, =OS_NVIC_PENDSV_PRI
+    STR     R5, [R4]
+
+    MOV     R0, #2
+    MSR     CONTROL, R0
+
+    LDR     R1, =g_losTask
+    LDR     R0, [R1, #4]
+    LDR     R12, [R0]
+
+    LDR.W   R1, =OS_FPU_CPACR
+    LDR     R1, [R1]
+    AND     R1, R1, #OS_FPU_CPACR_ENABLE
+    CMP     R1, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU
+    ADD     R12, R12, #100
+
+    LDMFD   R12!, {R0-R7}
+    ADD     R12, R12, #72
+    MSR     PSP, R12
+    VPUSH   S0;
+    VPOP    S0;
+    MOV     LR, R5
+    CPSIE   I
+    BX      R6
+
+__DisabledFPU
+    ADD     R12, R12, #36
+
+    LDMFD   R12!, {R0-R7}
+    MSR     PSP, R12
+    MOV     LR, R5
+    CPSIE   I
+    BX      R6
+
+
+ArchIntLock
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+ArchIntUnLock
+    MRS     R0, PRIMASK
+    CPSIE   I
+    BX      LR
+
+ArchIntRestore
+    MSR     PRIMASK, R0
+    BX      LR
+
+ArchTaskSchedule
+    LDR     R0, =OS_NVIC_INT_CTRL
+    LDR     R1, =OS_NVIC_PENDSVSET
+    STR     R1, [R0]
+    DSB
+    ISB
+    BX      LR
+
+HalPendSV
+    MRS     R12, PRIMASK
+    CPSID   I
+
+HalTaskSwitch
+    PUSH    {R12, LR}
+    BLX     OsSchedTaskSwitch
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R0, LR
+    BNE     TaskContextSwitch
+    MSR     PRIMASK, R12
+    BX      LR
+
+TaskContextSwitch
+    MOV     LR, R0
+    MRS     R0, PSP
+
+    STMFD   R0!, {R4-R12}
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU1
+    VSTMDB  R0!, {D8-D15}
+
+__DisabledFPU1
+    LDR     R5, =g_losTask
+    LDR     R6, [R5]
+    STR     R0, [R6]
+
+    LDR     R0, [R5, #4]
+    STR     R0, [R5]
+    LDR     R1, [R0]
+
+SignalContextRestore
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU2
+    VLDMIA  R1!, {D8-D15}
+
+__DisabledFPU2
+    LDMFD   R1!, {R4-R12}
+    MSR     PSP,  R1
+
+    MSR     PRIMASK, R12
+    BX      LR
+
+    END
--- a/arch/arm/cortex-m55/iar/NTZ/los_exc.S
+++ b/arch/arm/cortex-m55/iar/NTZ/los_exc.S
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    PRESERVE8
+    SECTION    .text:CODE(2)
+    THUMB
+
+    EXPORT  HalExcNMI
+    EXPORT  HalExcHardFault
+    EXPORT  HalExcMemFault
+    EXPORT  HalExcBusFault
+    EXPORT  HalExcUsageFault
+    EXPORT  HalSVCHandler
+
+    IMPORT HalExcHandleEntry
+    IMPORT g_uwExcTbl
+    IMPORT g_taskScheduled
+
+OS_FLG_BGD_ACTIVE   EQU   0x0002
+
+OS_EXC_CAUSE_NMI            EQU   16
+OS_EXC_CAUSE_HARDFAULT      EQU   17
+
+HF_DEBUGEVT     EQU   20
+HF_VECTBL       EQU   21
+
+FLAG_ADDR_VALID             EQU   0x10000
+FLAG_HWI_ACTIVE             EQU   0x20000
+FLAG_NO_FLOAT               EQU   0x10000000
+
+OS_NVIC_FSR                 EQU   0xE000ED28      ;include BusFault/MemFault/UsageFault State Register
+OS_NVIC_HFSR                EQU   0xE000ED2C      ;HardFault State Register
+OS_NVIC_BFAR                EQU   0xE000ED38
+OS_NVIC_MMAR                EQU   0xE000ED34
+OS_NVIC_ACT_BASE            EQU   0xE000E300
+OS_NVIC_SHCSRS              EQU   0xE000ED24
+OS_NVIC_SHCSR_MASK          EQU   0xC00
+
+HalExcNMI
+    MOV  R0, #OS_EXC_CAUSE_NMI
+    MOV  R1, #0
+    B  osExcDispatch
+
+HalExcHardFault
+    MOV  R0, #OS_EXC_CAUSE_HARDFAULT
+    LDR  R2, =OS_NVIC_HFSR
+    LDR  R2, [R2]
+
+    MOV  R1, #HF_DEBUGEVT
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x80000000
+    BNE  osExcDispatch     ; DEBUGEVT
+
+    AND  R0, R0 , #0x000000FF
+    MOV  R1, #HF_VECTBL
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x00000002
+    BNE  osExcDispatch     ; VECTBL
+
+    ;if not DEBUGEVT and VECTBL then is FORCED
+    AND  R0, R0, #0x000000FF
+
+    LDR  R2, =OS_NVIC_FSR
+    LDR  R2, [R2]
+
+    TST  R2, #0x8000     ; BFARVALID
+    BNE  _HFBusFault     ; BusFault
+
+    TST  R2, #0x80       ; MMARVALID
+    BNE  _HFMemFault     ; MemFault
+
+    MOV  R12,#0
+    B    osHFExcCommonBMU
+
+_HFBusFault
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    B    osHFExcCommonBMU
+
+_HFMemFault
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+
+osHFExcCommonBMU
+    CLZ  R2, R2
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R2
+    LDRB R2, [R3]
+    ORR  R0, R0, R2, LSL #0x8
+    ORR  R0, R0 ,R12
+    B    osExcDispatch
+
+HalSVCHandler
+    TST   LR, #0x4
+    ITE   EQ
+    MRSEQ R0, MSP
+    MRSNE R0, PSP
+    LDR   R1, [R0,#24]
+    LDRB  R0, [R1,#-2]
+    MOV   R1, #0
+    B     osExcDispatch
+
+HalExcBusFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x8000 ; BFARVALID
+    BEQ  _ExcBusNoADDR
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1F00
+
+    B    osExcCommonBMU
+
+_ExcBusNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcMemFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x80 ; MMARVALID
+    BEQ  _ExcMemNoADDR
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1B
+
+    B    osExcCommonBMU
+
+_ExcMemNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcUsageFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    MOV  R1, #0x030F
+    LSL  R1, R1, #16
+    AND  R0, R0, R1
+    MOV  R12, #0
+
+osExcCommonBMU
+    CLZ  R0, R0
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R0
+    LDRB R0, [R3]
+    ORR  R0, R0, R12
+
+; R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid),  R1 -- EXCADDR
+osExcDispatch
+    LDR   R2, =OS_NVIC_ACT_BASE
+    MOV   R12, #8                       ; R12 is hwi check loop counter
+
+_hwiActiveCheck
+    LDR   R3, [R2]                      ; R3 store active hwi register when exc
+    CMP   R3, #0
+    BEQ   _hwiActiveCheckNext
+
+    ; exc occurred in IRQ
+    ORR   R0, R0, #FLAG_HWI_ACTIVE
+    RBIT  R2, R3
+    CLZ   R2, R2
+    AND   R12, R12, #1
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as uwPid
+
+_ExcInMSP
+    CMP   LR, #0xFFFFFFE9
+    BNE   _NoFloatInMsp
+    ADD   R3, R13, #104
+    PUSH  {R3}
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    VPUSH {D8-D15}
+    B     _handleEntry
+
+_NoFloatInMsp
+    ADD   R3, R13, #32
+    PUSH  {R3} ; save IRQ SP            ; store message-->exc: MSP(R13)
+
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+    B     _handleEntry
+
+_hwiActiveCheckNext
+    ADD   R2, R2, #4                        ; next NVIC ACT ADDR
+    SUBS  R12, R12, #1
+    BNE   _hwiActiveCheck
+
+    ;/*NMI interrupt excption*/
+    LDR   R2, =OS_NVIC_SHCSRS
+    LDRH  R2,[R2]
+    LDR   R3,=OS_NVIC_SHCSR_MASK
+    AND   R2, R2,R3
+    CMP   R2,#0
+    BNE   _ExcInMSP
+    ; exc occurred in Task or Init or exc
+    ; reserved for register info from task stack
+
+    LDR  R2, =g_taskScheduled
+    LDR  R2, [R2]
+    TST  R2, #1         ; OS_FLG_BGD_ACTIVE
+    BEQ  _ExcInMSP                      ; if exc occurred in Init then branch
+
+
+    CMP   LR, #0xFFFFFFED               ;auto push floating registers
+    BNE   _NoFloatInPsp
+
+    ; exc occurred in Task
+    MOV   R2,  R13
+    SUB   R13, #96                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #104
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+    VPUSH {D8-D15}
+
+    ; copy auto saved task register
+
+    LDMFD R3!, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    VLDMIA  R3!, {D8-D15}
+    VSTMDB  R2!, {D8-D15}
+    STMFD R2!, {R4-R11}
+    B     _handleEntry
+
+_NoFloatInPsp
+    MOV   R2,  R13                           ;no auto push floating registers
+    SUB   R13, #32                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #32
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+
+    LDMFD R3, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    STMFD R2!, {R4-R11}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+
+_handleEntry
+    MOV R3, R13                         ; R13:the 4th param
+    CPSID I
+    CPSID F
+    B  HalExcHandleEntry
+
+    NOP
+    END
--- a/arch/arm/cortex-m55/iar/NTZ/los_interrupt.c
+++ b/arch/arm/cortex-m55/iar/NTZ/los_interrupt.c
@@ -0,0 +1,654 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_interrupt.h"
+#include "securec.h"
+#include <stdarg.h>
+#include "los_arch_interrupt.h"
+#include "los_context.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
+#include "los_cpup.h"
+#endif
+
+/*lint -save -e40 -e522 -e533*/
+UINT32 g_intCount = 0;
+
+/*lint -restore*/
+#pragma location = ".data.vector"
+#pragma data_alignment = LOSCFG_ARCH_HWI_VECTOR_ALIGN
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_DEBUG_TOOLS == 1)
+STATIC UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM] = {0};
+STATIC CHAR *g_hwiFormName[OS_HWI_MAX_NUM] = {0};
+
+UINT32 OsGetHwiFormCnt(UINT32 index)
+{
+    return g_hwiFormCnt[index];
+}
+
+CHAR *OsGetHwiFormName(UINT32 index)
+{
+    return g_hwiFormName[index];
+}
+
+BOOL OsGetHwiCreated(UINT32 index)
+{
+    if (g_hwiForm[index] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return TRUE;
+    }
+
+    return FALSE;
+}
+#endif
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+    HWI_PROC_FUNC pfnHandler;
+    VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+    }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+    }
+}
+#endif
+
+WEAK VOID SysTick_Handler(VOID)
+{
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HwiNumGet
+ Description : Get an interrupt number
+ Input       : None
+ Output      : None
+ Return      : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+    return __get_IPSR();
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+    return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function    : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+/*lint -e529*/
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+    while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+    UINT32 hwiIndex;
+    UINT32 intSave;
+
+#if (LOSCFG_KERNEL_RUNSTOP == 1)
+    SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
+#endif
+
+    intSave = LOS_IntLock();
+
+    g_intCount++;
+
+    LOS_IntRestore(intSave);
+
+    hwiIndex = HwiNumGet();
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
+    OsCpupIrqStart(hwiIndex);
+#endif
+
+    HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+        g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+    }
+#else
+    if (g_hwiHandlerForm[hwiIndex] != 0) {
+        g_hwiHandlerForm[hwiIndex]();
+    }
+#endif
+
+#if (LOSCFG_DEBUG_TOOLS == 1)
+    ++g_hwiFormCnt[hwiIndex];
+#endif
+
+    HalAftInterruptHandler(hwiIndex);
+
+#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
+    OsCpupIrqEnd(hwiIndex);
+#endif
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+    intSave = LOS_IntLock();
+    g_intCount--;
+    LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiCreate
+ Description : create hardware interrupt
+ Input       : hwiNum   --- hwi num to create
+               hwiPrio  --- priority of the hwi
+               hwiMode  --- unused
+               hwiHandler --- hwi handler
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T hwiMode,
+                                           HWI_PROC_FUNC hwiHandler,
+                                           HwiIrqParam *irqParam)
+{
+    (VOID)hwiMode;
+    UINTPTR intSave;
+
+    if (hwiHandler == NULL) {
+        return OS_ERRNO_HWI_PROC_FUNC_NULL;
+    }
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return OS_ERRNO_HWI_ALREADY_CREATED;
+    }
+
+    if (hwiPrio > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (irqParam != NULL) {
+        OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+    } else {
+        OsSetVector(hwiNum, hwiHandler, NULL);
+    }
+#else
+    (VOID)irqParam;
+    OsSetVector(hwiNum, hwiHandler);
+#endif
+
+#if (LOSCFG_DEBUG_TOOLS == 1)
+    if ((irqParam != NULL) && (irqParam->pName != NULL)) {
+        g_hwiFormName[hwiNum + OS_SYS_VECTOR_CNT] = (CHAR *)irqParam->pName;
+    }
+    g_hwiFormCnt[hwiNum + OS_SYS_VECTOR_CNT] = 0;
+#endif
+
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input       : hwiNum   --- hwi num to delete
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+    (VOID)irqParam;
+    UINT32 intSave;
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    intSave = LOS_IntLock();
+
+    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+#define FAULT_STATUS_REG_BIT            32
+#define USGFAULT                        (1 << 18)
+#define BUSFAULT                        (1 << 17)
+#define MEMFAULT                        (1 << 16)
+#define DIV0FAULT                       (1 << 4)
+#define HARDFAULT_IRQN                  (-13)
+
+ExcInfo g_excInfo = {0};
+
+UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
+    0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
+    0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
+    0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
+    0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
+};
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcNvicDump(VOID)
+{
+#define OS_NR_NVIC_EXC_DUMP_TYPES   7
+    UINT32 *base = NULL;
+    UINT32 len, i, j;
+    UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
+        OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
+    };
+    UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
+        OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
+        OS_NVIC_INT_CTRL_SIZE
+    };
+    CHAR strRgEnable[] = "enable";
+    CHAR strRgPending[] = "pending";
+    CHAR strRgActive[] = "active";
+    CHAR strRgPriority[] = "priority";
+    CHAR strRgException[] = "exception";
+    CHAR strRgShcsr[] = "shcsr";
+    CHAR strRgIntCtrl[] = "control";
+    CHAR *strRgs[] = {
+        strRgEnable, strRgPending, strRgActive, strRgPriority,
+        strRgException, strRgShcsr, strRgIntCtrl
+    };
+
+    PRINTK("\r\nOS exception NVIC dump:\n");
+    for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
+        base = (UINT32 *)rgNvicBases[i];
+        len = rgNvicLens[i];
+        PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
+        len = (len >> 2); /* 2: Gets the next register offset */
+        for (j = 0; j < len; j++) {
+            PRINTK("0x%x ", *(base + j));
+            if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
+                PRINTK("\n");
+            }
+        }
+        PRINTK("\n");
+    }
+}
+
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+    CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+    PRINTK("Type      = %d\n", excInfo->type);
+    PRINTK("ThrdPid   = %d\n", excInfo->thrdPid);
+    PRINTK("Phase     = %s\n", phaseStr[excInfo->phase]);
+    PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Current task info:\n");
+    if (excInfo->phase == OS_EXC_IN_TASK) {
+        LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+        PRINTK("Task name = %s\n", taskCB->taskName);
+        PRINTK("Task ID   = %d\n", taskCB->taskID);
+        PRINTK("Task SP   = %p\n", taskCB->stackPointer);
+        PRINTK("Task ST   = 0x%x\n", taskCB->topOfStack);
+        PRINTK("Task SS   = 0x%x\n", taskCB->stackSize);
+    } else if (excInfo->phase == OS_EXC_IN_HWI) {
+        PRINTK("Exception occur in interrupt phase!\n");
+    } else {
+        PRINTK("Exception occur in system init phase!\n");
+    }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Exception reg dump:\n");
+    PRINTK("PC        = 0x%x\n", excInfo->context->uwPC);
+    PRINTK("LR        = 0x%x\n", excInfo->context->uwLR);
+    PRINTK("SP        = 0x%x\n", excInfo->context->uwSP);
+    PRINTK("R0        = 0x%x\n", excInfo->context->uwR0);
+    PRINTK("R1        = 0x%x\n", excInfo->context->uwR1);
+    PRINTK("R2        = 0x%x\n", excInfo->context->uwR2);
+    PRINTK("R3        = 0x%x\n", excInfo->context->uwR3);
+    PRINTK("R4        = 0x%x\n", excInfo->context->uwR4);
+    PRINTK("R5        = 0x%x\n", excInfo->context->uwR5);
+    PRINTK("R6        = 0x%x\n", excInfo->context->uwR6);
+    PRINTK("R7        = 0x%x\n", excInfo->context->uwR7);
+    PRINTK("R8        = 0x%x\n", excInfo->context->uwR8);
+    PRINTK("R9        = 0x%x\n", excInfo->context->uwR9);
+    PRINTK("R10       = 0x%x\n", excInfo->context->uwR10);
+    PRINTK("R11       = 0x%x\n", excInfo->context->uwR11);
+    PRINTK("R12       = 0x%x\n", excInfo->context->uwR12);
+    PRINTK("PriMask   = 0x%x\n", excInfo->context->uwPriMask);
+    PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+    UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+    UINT32 index;
+
+    OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
+
+    PRINTK("----- backtrace start -----\n");
+    for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+        if (LR[index] == 0) {
+            break;
+        }
+        PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
+    }
+    PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+    PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+    MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+    UINT32 errCnt;
+    UINT32 i;
+
+    (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+    errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+    if (errCnt < OS_SYS_MEM_NUM) {
+        errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+    }
+
+    if (errCnt == 0) {
+        PRINTK("all memory pool check passed!\n");
+        return;
+    }
+
+    for (i = 0; i < errCnt; i++) {
+        PRINTK("pool num    = %d\n", i);
+        PRINTK("pool type   = %d\n", memExcInfo[i].type);
+        PRINTK("pool addr   = 0x%x\n", memExcInfo[i].startAddr);
+        PRINTK("pool size   = 0x%x\n", memExcInfo[i].size);
+        PRINTK("pool free   = 0x%x\n", memExcInfo[i].free);
+        PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
+        PRINTK("pool error node addr  = 0x%x\n", memExcInfo[i].errorAddr);
+        PRINTK("pool error node len   = 0x%x\n", memExcInfo[i].errorLen);
+        PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
+    }
+#endif
+    UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+    if (ret == LOS_OK) {
+        PRINTK("system heap memcheck over, all passed!\n");
+    }
+
+    PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+    PRINTK("*************Exception Information**************\n");
+    OsExcTypeInfo(excInfo);
+    OsExcCurTaskInfo(excInfo);
+    OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+    OsExcBackTraceInfo(excInfo);
+#endif
+    OsGetAllTskInfo();
+    OsExcNvicDump();
+    OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+    UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
+    g_intCount++;
+    g_excInfo.nestCnt++;
+
+    g_excInfo.type = excType & OS_NULL_SHORT;
+
+    if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
+        g_excInfo.faultAddr = faultAddr;
+    } else {
+        g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+    }
+    if (g_losTask.runTask != NULL) {
+        if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
+            g_excInfo.phase = OS_EXC_IN_HWI;
+            g_excInfo.thrdPid = pid;
+        } else {
+            g_excInfo.phase = OS_EXC_IN_TASK;
+            g_excInfo.thrdPid = g_losTask.runTask->taskID;
+        }
+    } else {
+        g_excInfo.phase = OS_EXC_IN_INIT;
+        g_excInfo.thrdPid = OS_NULL_INT;
+    }
+    if (excType & OS_EXC_FLAG_NO_FLOAT) {
+        g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
+    } else {
+        g_excInfo.context = excBufAddr;
+    }
+
+    OsDoExcHook(EXC_INTERRUPT);
+    OsExcInfoDisplay(&g_excInfo);
+    ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function    : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    UINT32 index;
+    g_hwiForm[0] = 0;             /* [0] Top of Stack */
+    g_hwiForm[1] = (HWI_PROC_FUNC)Reset_Handler; /* [1] reset */
+    for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
+        g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+    }
+    /* Exception handler register */
+    g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT]   = (HWI_PROC_FUNC)HalExcNMI;
+    g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT]        = (HWI_PROC_FUNC)HalExcHardFault;
+    g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault;
+    g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT]         = (HWI_PROC_FUNC)HalExcBusFault;
+    g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT]       = (HWI_PROC_FUNC)HalExcUsageFault;
+    g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT]           = (HWI_PROC_FUNC)HalSVCHandler;
+    g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT]           = (HWI_PROC_FUNC)HalPendSV;
+    g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT]          = (HWI_PROC_FUNC)SysTick_Handler;
+
+    /* Interrupt vector table location */
+    SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
+#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
+    NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
+#endif
+
+    /* Enable USGFAULT, BUSFAULT, MEMFAULT */
+    *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+    /* Enable DIV 0 and unaligned exception */
+    *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
+
+    return;
+}
+
--- a/arch/arm/cortex-m55/iar/NTZ/los_timer.c
+++ b/arch/arm/cortex-m55/iar/NTZ/los_timer.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "los_tick.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+    UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
+
+    tick->freq = OS_SYS_CLOCK;
+
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
+#else
+    OsSetVector(tick->irqNum, handler);
+#endif
+#endif
+
+    ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
+    if (ret == 1) {
+        return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
+    }
+
+    return LOS_OK;
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+    if (nextResponseTime > g_archTickTimer.periodMax) {
+        nextResponseTime = g_archTickTimer.periodMax;
+    }
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
+    SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+    UINT32 hwCycle = 0;
+    UINTPTR intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
+    *period = SysTick->LOAD;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
+    LOS_IntRestore(intSave);
+    return (UINT64)hwCycle;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+    __DSB();
+    __WFI();
+    __ISB();
+    return LOS_OK;
+}
--- a/arch/arm/cortex-m55/iar/TZ/BUILD.gn
+++ b/arch/arm/cortex-m55/iar/TZ/BUILD.gn
@@ -0,0 +1,46 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_name = "arch"
+kernel_module(module_name) {
+  sources = [
+    "los_context.c",
+    "los_dispatch.S",
+    "los_exc.S",
+    "los_interrupt.c",
+    "los_timer.c",
+  ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
+}
+
+config("public") {
+  include_dirs = [ "." ]
+}
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_arch_atomic.h
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_arch_atomic.h
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    asm volatile("ldrex %0, [%1]\n"
+                 : "=&r"(val)
+                 : "r"(v)
+                 : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %0, [%1]\n"
+                     "strex %0, %2, [%1]\n"
+                     : "=&r"(status)
+                     : "r"(v), "r"(setVal)
+                     : "cc");
+    } while (status != 0);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "add %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(addVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "sub %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(subVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        asm volatile("ldrex %0, [%2]\n"
+                     "strex %1, %3, [%2]"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        asm volatile("ldrex %0, [%2]\n"
+                     "mov %1, #0\n"
+                     "cmp %0, %3\n"
+                     "bne 1f\n"
+                     "strex %1, %4, [%2]\n"
+                     "1:"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(oldVal), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_arch_context.h
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_arch_context.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct TagTskContext {
+    UINT32 secureContext;
+    UINT32 stackLmit;
+    UINT32 excReturn;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} TaskContext;
+
+/**
+ * @ingroup  los_config
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */
+
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_arch_interrupt.h
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_arch_interrupt.h
@@ -0,0 +1,684 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_EXC_H
+#define _LOS_EXC_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_hwi
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_hwi
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST                   0
+#endif
+
+/* *
+ * @ingroup los_hwi
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST                    7
+#endif
+
+
+/* *
+ * @ingroup  los_hwi
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_hwi
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_hwi
+ * Count of M-Core system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT                     16
+
+/* *
+ * @ingroup los_hwi
+ * Count of M-Core interrupt vector.
+ */
+#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_hwi
+ * AIRCR register priority group parameter .
+ */
+#define OS_NVIC_AIRCR_PRIGROUP                7
+
+/* *
+ * @ingroup los_hwi
+ * Boot interrupt vector table.
+ */
+extern UINT32 _BootVectors[];
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+/* *
+ * @ingroup los_hwi
+ * SysTick control and status register.
+ */
+#define OS_SYSTICK_CONTROL_REG                0xE000E010
+
+/* *
+ * @ingroup los_hw
+ * SysTick current value register.
+ */
+#define OS_SYSTICK_CURRENT_REG                0xE000E018
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt Priority-Level Registers.
+ */
+#define OS_NVIC_PRI_BASE                      0xE000E400
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt enable register for 0-31.
+ */
+#define OS_NVIC_SETENA_BASE                   0xE000E100
+
+/* *
+ * @ingroup los_hwi
+ * interrupt pending register.
+ */
+#define OS_NVIC_SETPEND_BASE                  0xE000E200
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt active register.
+ */
+#define OS_NVIC_INT_ACT_BASE                  0xE000E300
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt disable register for 0-31.
+ */
+#define OS_NVIC_CLRENA_BASE                   0xE000E180
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt control and status register.
+ */
+#define OS_NVIC_INT_CTRL                      0xE000ED04
+
+/* *
+ * @ingroup los_hwi
+ * Vector table offset register.
+ */
+#define OS_NVIC_VTOR                          0xE000ED08
+
+/* *
+ * @ingroup los_hwi
+ * Application interrupt and reset control register
+ */
+#define OS_NVIC_AIRCR                         0xE000ED0C
+
+/* *
+ * @ingroup los_hwi
+ * System exception priority register.
+ */
+#define OS_NVIC_EXCPRI_BASE                   0xE000ED18
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 1 :reset.
+ */
+#define OS_EXC_RESET                          1
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 2 :Non-Maskable Interrupt.
+ */
+#define OS_EXC_NMI                            2
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 3 :(hard)fault.
+ */
+#define OS_EXC_HARD_FAULT                     3
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 4 :MemManage fault.
+ */
+#define OS_EXC_MPU_FAULT                      4
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 5 :Bus fault.
+ */
+#define OS_EXC_BUS_FAULT                      5
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 6 :Usage fault.
+ */
+#define OS_EXC_USAGE_FAULT                    6
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 11 :SVCall.
+ */
+#define OS_EXC_SVC_CALL                       11
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 12 :Debug monitor.
+ */
+#define OS_EXC_DBG_MONITOR                    12
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 14 :PendSV.
+ */
+#define OS_EXC_PEND_SV                        14
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 15 :SysTick.
+ */
+#define OS_EXC_SYS_TICK                       15
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li
+></ul>
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Reset the vector table.
+ *
+ * @par Description:
+ * This API is used to reset the vector table.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID Reset_Handler(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Pended System Call.
+ *
+ * @par Description:
+ * PendSV can be pended and is useful for an OS to pend an exception
+ * so that an action can be performed after other important tasks are completed.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalPendSV(VOID);
+
+
+#define OS_EXC_IN_INIT                      0
+#define OS_EXC_IN_TASK                      1
+#define OS_EXC_IN_HWI                       2
+
+#define OS_EXC_MAX_BUF_LEN                  25
+#define OS_EXC_MAX_NEST_DEPTH               1
+
+#define OS_NVIC_SHCSR                       0xE000ED24
+#define OS_NVIC_CCR                         0xE000ED14
+
+#define OS_NVIC_INT_ENABLE_SIZE             0x20
+#define OS_NVIC_INT_PRI_SIZE                0xF0
+#define OS_NVIC_EXCPRI_SIZE                 0xC
+#define OS_NVIC_INT_CTRL_SIZE               4
+#define OS_NVIC_SHCSR_SIZE                  4
+
+#define OS_NVIC_INT_PEND_SIZE               OS_NVIC_INT_ACT_SIZE
+#define OS_NVIC_INT_ACT_SIZE                OS_NVIC_INT_ENABLE_SIZE
+
+#define OS_EXC_FLAG_NO_FLOAT                0x10000000
+#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
+#define OS_EXC_FLAG_IN_HWI                  0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
+
+#define OS_EXC_EVENT                        0x00000001
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
+ */
+typedef struct TagExcContext {
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    /* auto save */
+    UINT32 uwSP;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED) && (__FPU_USED== 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+}EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+
+VOID HalExcNMI(VOID);
+VOID HalExcHardFault(VOID);
+VOID HalExcMemFault(VOID);
+VOID HalExcBusFault(VOID);
+VOID HalExcUsageFault(VOID);
+VOID HalSVCHandler(VOID);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was being pushed.
+ */
+#define OS_EXC_BF_STKERR           1
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was out of the stack.
+ */
+#define OS_EXC_BF_UNSTKERR         2
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register imprecise data access violation.
+ */
+#define OS_EXC_BF_IMPRECISERR      3
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register exact data access violation.
+ */
+#define OS_EXC_BF_PRECISERR        4
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register access violation while pointing.
+ */
+#define OS_EXC_BF_IBUSERR          5
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was being pushed.
+ */
+#define OS_EXC_MF_MSTKERR          6
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
+ */
+#define OS_EXC_MF_MUNSTKERR        7
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register data access violation.
+ */
+#define OS_EXC_MF_DACCVIOL         8
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register access violation.
+ */
+#define OS_EXC_MF_IACCVIOL         9
+
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
+ */
+#define OS_EXC_UF_DIVBYZERO        10
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error, error caused by unaligned access.
+ */
+#define OS_EXC_UF_UNALIGNED        11
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
+ */
+#define OS_EXC_UF_NOCP             12
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
+ */
+#define OS_EXC_UF_INVPC            13
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
+ */
+#define OS_EXC_UF_INVSTATE         14
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
+ */
+#define OS_EXC_UF_UNDEFINSTR       15
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: NMI
+ */
+
+#define OS_EXC_CAUSE_NMI           16
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: hard fault
+ */
+#define OS_EXC_CAUSE_HARDFAULT     17
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: The task handler exits.
+ */
+#define OS_EXC_CAUSE_TASK_EXIT     18
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A fatal error.
+ */
+#define OS_EXC_CAUSE_FATAL_ERR     19
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Hard Fault caused by a debug event.
+ */
+#define OS_EXC_CAUSE_DEBUGEVT      20
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
+ */
+#define OS_EXC_CAUSE_VECTBL        21
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
+ *
+ */
+typedef struct TagExcInfo {
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    UINT16 phase;
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
+    UINT16 type;
+    /**< If the exact address access error indicates the wrong access address when the exception occurred */
+    UINT32 faultAddr;
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    UINT32 thrdPid;
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
+    UINT16 nestCnt;
+    /**< reserve */
+    UINT16 reserved;
+    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+    EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_curNestCount;
+extern UINT32 g_intCount;
+extern UINT8 g_uwExcTbl[32];
+extern ExcInfo g_excInfo;
+
+#define MAX_INT_INFO_SIZE       (8 + 0x164)
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_EXC_H */
--- a/targets/riscv_nuclei_gd32vf103_soc_gcc/Src/task_sample.h
+++ b/targets/riscv_nuclei_gd32vf103_soc_gcc/Src/task_sample.h
@@ -1,7 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- * Copyright (c) 2021 Nuclei Limited. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -27,15 +26,15 @@
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
- *
- * Description: Provide a task example.
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

-#ifndef _TASKSAMPLE_H
-#define _TASKSAMPLE_H
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H

+#include "los_config.h"
 #include "los_compiler.h"
+#include "los_timer.h"

 #ifdef __cplusplus
 #if __cplusplus
@@ -43,12 +42,11 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */

-VOID RunTaskSample(VOID);
-
 #ifdef __cplusplus
 #if __cplusplus
 }
 #endif /* __cplusplus */
 #endif /* __cplusplus */

-#endif /* _TASKSAMPLE_H */
+#endif /* _LOS_ARCH_TIMER_H */
+
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_context.c
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_context.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
+
+/* ****************************************************************************
+ Function    : ArchInit
+ Description : arch init function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+    HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function    : ArchSysExit
+ Description : Task exit function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+    (VOID)LOS_IntLock();
+    while (1) {
+    }
+}
+
+/* ****************************************************************************
+ Function    : ArchTskStackInit
+ Description : Task stack initialization function
+ Input       : taskID     --- TaskID
+               stackSize  --- Total size of the stack
+               topStack    --- Top of task's stack
+ Output      : None
+ Return      : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
+
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    context->S16 = 0xAA000010;
+    context->S17 = 0xAA000011;
+    context->S18 = 0xAA000012;
+    context->S19 = 0xAA000013;
+    context->S20 = 0xAA000014;
+    context->S21 = 0xAA000015;
+    context->S22 = 0xAA000016;
+    context->S23 = 0xAA000017;
+    context->S24 = 0xAA000018;
+    context->S25 = 0xAA000019;
+    context->S26 = 0xAA00001A;
+    context->S27 = 0xAA00001B;
+    context->S28 = 0xAA00001C;
+    context->S29 = 0xAA00001D;
+    context->S30 = 0xAA00001E;
+    context->S31 = 0xAA00001F;
+    context->S0 = 0xAA000000;
+    context->S1 = 0xAA000001;
+    context->S2 = 0xAA000002;
+    context->S3 = 0xAA000003;
+    context->S4 = 0xAA000004;
+    context->S5 = 0xAA000005;
+    context->S6 = 0xAA000006;
+    context->S7 = 0xAA000007;
+    context->S8 = 0xAA000008;
+    context->S9 = 0xAA000009;
+    context->S10 = 0xAA00000A;
+    context->S11 = 0xAA00000B;
+    context->S12 = 0xAA00000C;
+    context->S13 = 0xAA00000D;
+    context->S14 = 0xAA00000E;
+    context->S15 = 0xAA00000F;
+    context->FPSCR = 0x00000000;
+    context->NO_NAME = 0xAA000011;
+#endif
+
+    context->secureContext = 0UL;
+    context->stackLmit = (UINT32)topStack;
+    context->excReturn = 0xFFFFFFBC;
+
+    context->uwR4 = 0x04040404L;
+    context->uwR5 = 0x05050505L;
+    context->uwR6 = 0x06060606L;
+    context->uwR7 = 0x07070707L;
+    context->uwR8 = 0x08080808L;
+    context->uwR9 = 0x09090909L;
+    context->uwR10 = 0x10101010L;
+    context->uwR11 = 0x11111111L;
+    context->uwPriMask = 0;
+    context->uwR0 = taskID;
+    context->uwR1 = 0x01010101L;
+    context->uwR2 = 0x02020202L;
+    context->uwR3 = 0x03030303L;
+    context->uwR12 = 0x12121212L;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
+    context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
+    context->uwxPSR = 0x01000000L;
+
+    return (VOID *)context;
+}
+
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->stackLimit = (UINT32)stackTop;
+    context->excReturn = 0xFFFFFFBC;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+    return LOS_OK; /* never return */
+}
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_dispatch.S
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_dispatch.S
@@ -0,0 +1,237 @@
+;
+; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this list of
+;    conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice, this list
+;    of conditions and the following disclaimer in the documentation and/or other materials
+;    provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without specific prior written
+;    permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+    PRESERVE8
+
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
+    EXPORT  ArchTaskSchedule
+    EXPORT  HalPendSV
+    EXPORT  HalSVCHandler
+    EXPORT  HalStartFirstTask
+    EXPORT  HalSVCStartSchedule
+    EXPORT  HalSVCSecureContextAlloc
+    EXPORT  HalSVCSecureContextFree
+    IMPORT  OsSignalTaskContextRestore
+    IMPORT  OsSchedTaskSwitch
+    IMPORT  g_losTask
+
+    EXTERN  HalSecureSVCHandler
+    EXTERN  HalSecureContextSave
+    EXTERN  HalSecureContextLoad
+    EXTERN  g_secureContext
+
+OS_FPU_CPACR                EQU     0xE000ED88
+OS_FPU_CPACR_ENABLE         EQU     0x00F00000
+OS_NVIC_INT_CTRL            EQU     0xE000ED04
+OS_NVIC_SYSPRI2             EQU     0xE000ED20
+OS_NVIC_PENDSV_PRI          EQU     0xF0F00000
+OS_NVIC_PENDSVSET           EQU     0x10000000
+OS_TASK_STATUS_RUNNING      EQU     0x0010
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+
+    MACRO SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+    ENDM
+
+HalStartFirstTask
+    MOV     R0, #2
+    MSR     CONTROL, R0
+
+    LDR     R1, =g_losTask
+    LDR     R0, [R1, #4]
+
+    LDR     R12, [R0]                  /* Get the stack pointer of the current task. */
+    LDMFD   R12!, {R1-R3}              /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 = excReturn.*/
+    LDR     R4, =g_secureContext
+    STR     R1, [R4]                   /* Set the secureContext to g_secureContext handler. */
+    MSR     PSPLIM, R2                 /* Set the stackLmit for the PSPLIM about current task. */
+    ISB
+
+    LDR.W   R1, =OS_FPU_CPACR
+    LDR     R1, [R1]
+    AND     R1, R1, #OS_FPU_CPACR_ENABLE
+    CMP     R1, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU1
+    ADD     R12, R12, #64
+    VPUSH   S0;
+    VPOP    S0;
+
+__DisabledFPU1
+    ADD     R12, R12, #36
+    MSR     PSP, R12
+    CPSIE   I
+    BX      R3
+
+ArchIntLock
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+ArchIntUnLock
+    MRS     R0, PRIMASK
+    CPSIE   I
+    BX      LR
+
+ArchIntRestore
+    MSR     PRIMASK, R0
+    BX      LR
+
+ArchTaskSchedule
+    LDR     R0, =OS_NVIC_INT_CTRL
+    LDR     R1, =OS_NVIC_PENDSVSET
+    STR     R1, [R0]
+    DSB
+    ISB
+    BX      LR
+
+HalPendSV
+    MRS     R12, PRIMASK
+    CPSID   I
+
+HalTaskSwitch
+    SIGNAL_CONTEXT_RESTORE
+
+    PUSH    {R12, LR}
+    BLX     OsSchedTaskSwitch
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R0, LR
+    BNE     TaskContextSwitch
+    MSR     PRIMASK, R12
+    BX      LR
+
+TaskContextSwitch
+    MOV     LR, R0
+    MRS     R0, PSP
+
+    LDR     R2, =g_secureContext
+    LDR     R1, [R2]
+    CBZ     R1, __SaveNSContext               /* If the g_secureContext is NULL, so no secure context to save. */
+
+    PUSH    {R0-R1, R12, R14}                 /* Store registers, include LR, PRIMASK. */
+    BL      HalSecureContextSave              /* Store the secure context to g_secureContext->curStackPointer. */
+    POP     {R0-R3}
+    MOV     LR, R3
+    MOV     R12, R2                           /* R2 = PRIMASK. */
+
+__SaveNSContext
+    STMFD   R0!, {R4-R12}
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU2
+    VSTMDB  R0!, {D8-D15}
+
+__DisabledFPU2
+    LDR     R5, =g_losTask
+    LDR     R6, [R5]                          /* Get the stackPointer handler of the current task. */
+    SUBS    R0, R0, #12
+    STR     R0, [R6]                          /* Save the new top of stack in TCB. */
+    MRS     R2, PSPLIM
+    MOV     R3, LR
+    STMIA   R0!, {R1, R2-R3}                  /* Store g_secureContext, PSPLIM and LR on the stack of current task. */
+
+    LDR     R0, [R5, #4]
+    STR     R0, [R5]
+    LDR     R1, [R0]
+
+SignalContextRestore
+    LDMIA   R1!, {R0, R2-R3}                  /* Restore secureContext, PSPLIM and LR from the current task stack. */
+    MSR     PSPLIM, R2
+    MOV     LR, R3
+    LDR     R2, =g_secureContext
+    STR     R0, [R2]                          /* Set the secureContext of the new task to g_secureContext. */
+    CBZ     R0, __RestoreNSContext            /* If there is no secure context for the new task, so restore from the non-secure context. */
+    PUSH    {R1, R3}
+    BL      HalSecureContextLoad              /* Restore the secure context. */
+    POP     {R1, R3}
+    MOV     LR, R3
+
+__RestoreNSContext
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU3
+    VLDMIA  R1!, {D8-D15}
+
+__DisabledFPU3
+    LDMFD   R1!, {R4-R12}
+    MSR     PSP,  R1
+
+    MSR     PRIMASK, R12
+    BX      LR
+
+HalSVCStartSchedule
+    LDR     R4, =OS_NVIC_SYSPRI2
+    LDR     R5, =OS_NVIC_PENDSV_PRI
+    STR     R5, [R4]
+    CPSIE   I
+    DSB
+    ISB
+    SVC     2
+
+HalSVCSecureContextAlloc
+    SVC     0
+    BX      LR
+
+HalSVCSecureContextFree
+    SVC     1
+    BX      LR
+
+HalSVCHandler
+    TST     LR, #0x04
+    ITE     EQ
+    MRSEQ   R1, MSP
+    MRSNE   R1, PSP
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]                     /* Get the SVC number. */
+
+    PUSH    {LR}
+    MOV     R2, R1                            /* Get the stack for R2. */
+    LDMFD   R2!, {R1}                         /* Get the input arg for HalSecureSVCHandler. */
+    STMFD   R2!, {R1}
+    BL      HalSecureSVCHandler
+    POP     {LR}
+    BX      LR
+
+    END
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_exc.S
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_exc.S
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    PRESERVE8
+    SECTION    .text:CODE(2)
+    THUMB
+
+    EXPORT  HalExcNMI
+    EXPORT  HalExcHardFault
+    EXPORT  HalExcMemFault
+    EXPORT  HalExcBusFault
+    EXPORT  HalExcUsageFault
+
+    IMPORT HalExcHandleEntry
+    IMPORT g_uwExcTbl
+    IMPORT g_taskScheduled
+
+OS_FLG_BGD_ACTIVE   EQU   0x0002
+
+OS_EXC_CAUSE_NMI            EQU   16
+OS_EXC_CAUSE_HARDFAULT      EQU   17
+
+HF_DEBUGEVT     EQU   20
+HF_VECTBL       EQU   21
+
+FLAG_ADDR_VALID             EQU   0x10000
+FLAG_HWI_ACTIVE             EQU   0x20000
+FLAG_NO_FLOAT               EQU   0x10000000
+
+OS_NVIC_FSR                 EQU   0xE000ED28      ;include BusFault/MemFault/UsageFault State Register
+OS_NVIC_HFSR                EQU   0xE000ED2C      ;HardFault State Register
+OS_NVIC_BFAR                EQU   0xE000ED38
+OS_NVIC_MMAR                EQU   0xE000ED34
+OS_NVIC_ACT_BASE            EQU   0xE000E300
+OS_NVIC_SHCSRS              EQU   0xE000ED24
+OS_NVIC_SHCSR_MASK          EQU   0xC00
+
+HalExcNMI
+    MOV  R0, #OS_EXC_CAUSE_NMI
+    MOV  R1, #0
+    B  osExcDispatch
+
+HalExcHardFault
+    MOV  R0, #OS_EXC_CAUSE_HARDFAULT
+    LDR  R2, =OS_NVIC_HFSR
+    LDR  R2, [R2]
+
+    MOV  R1, #HF_DEBUGEVT
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x80000000
+    BNE  osExcDispatch     ; DEBUGEVT
+
+    AND  R0, R0 , #0x000000FF
+    MOV  R1, #HF_VECTBL
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x00000002
+    BNE  osExcDispatch     ; VECTBL
+
+    ;if not DEBUGEVT and VECTBL then is FORCED
+    AND  R0, R0, #0x000000FF
+
+    LDR  R2, =OS_NVIC_FSR
+    LDR  R2, [R2]
+
+    TST  R2, #0x8000     ; BFARVALID
+    BNE  _HFBusFault     ; BusFault
+
+    TST  R2, #0x80       ; MMARVALID
+    BNE  _HFMemFault     ; MemFault
+
+    MOV  R12,#0
+    B    osHFExcCommonBMU
+
+_HFBusFault
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    B    osHFExcCommonBMU
+
+_HFMemFault
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+
+osHFExcCommonBMU
+    CLZ  R2, R2
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R2
+    LDRB R2, [R3]
+    ORR  R0, R0, R2, LSL #0x8
+    ORR  R0, R0 ,R12
+    B    osExcDispatch
+
+HalExcBusFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x8000 ; BFARVALID
+    BEQ  _ExcBusNoADDR
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1F00
+
+    B    osExcCommonBMU
+
+_ExcBusNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcMemFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x80 ; MMARVALID
+    BEQ  _ExcMemNoADDR
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1B
+
+    B    osExcCommonBMU
+
+_ExcMemNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcUsageFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    MOV  R1, #0x030F
+    LSL  R1, R1, #16
+    AND  R0, R0, R1
+    MOV  R12, #0
+
+osExcCommonBMU
+    CLZ  R0, R0
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R0
+    LDRB R0, [R3]
+    ORR  R0, R0, R12
+
+; R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid),  R1 -- EXCADDR
+osExcDispatch
+    LDR   R2, =OS_NVIC_ACT_BASE
+    MOV   R12, #8                       ; R12 is hwi check loop counter
+
+_hwiActiveCheck
+    LDR   R3, [R2]                      ; R3 store active hwi register when exc
+    CMP   R3, #0
+    BEQ   _hwiActiveCheckNext
+
+    ; exc occurred in IRQ
+    ORR   R0, R0, #FLAG_HWI_ACTIVE
+    RBIT  R2, R3
+    CLZ   R2, R2
+    AND   R12, R12, #1
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as pid
+
+_ExcInMSP
+    CMP   LR, #0xFFFFFFE9
+    BNE   _NoFloatInMsp
+    ADD   R3, R13, #104
+    PUSH  {R3}
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    VPUSH {D8-D15}
+    B     _handleEntry
+
+_NoFloatInMsp
+    ADD   R3, R13, #32
+    PUSH  {R3} ; save IRQ SP            ; store message-->exc: MSP(R13)
+
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+    B     _handleEntry
+
+_hwiActiveCheckNext
+    ADD   R2, R2, #4                        ; next NVIC ACT ADDR
+    SUBS  R12, R12, #1
+    BNE   _hwiActiveCheck
+
+    ;/*NMI interrupt excption*/
+    LDR   R2, =OS_NVIC_SHCSRS
+    LDRH  R2,[R2]
+    LDR   R3,=OS_NVIC_SHCSR_MASK
+    AND   R2, R2,R3
+    CMP   R2,#0
+    BNE   _ExcInMSP
+    ; exc occurred in Task or Init or exc
+    ; reserved for register info from task stack
+
+    LDR  R2, =g_taskScheduled
+    LDR  R2, [R2]
+    TST  R2, #1         ; OS_FLG_BGD_ACTIVE
+    BEQ  _ExcInMSP                      ; if exc occurred in Init then branch
+
+
+    CMP   LR, #0xFFFFFFED               ;auto push floating registers
+    BNE   _NoFloatInPsp
+
+    ; exc occurred in Task
+    MOV   R2,  R13
+    SUB   R13, #96                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #104
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+    VPUSH {D8-D15}
+
+    ; copy auto saved task register
+
+    LDMFD R3!, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    VLDMIA  R3!, {D8-D15}
+    VSTMDB  R2!, {D8-D15}
+    STMFD R2!, {R4-R11}
+    B     _handleEntry
+
+_NoFloatInPsp
+    MOV   R2,  R13                           ;no auto push floating registers
+    SUB   R13, #32                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #32
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+
+    LDMFD R3, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    STMFD R2!, {R4-R11}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+
+_handleEntry
+    MOV R3, R13                         ; R13:the 4th param
+    CPSID I
+    CPSID F
+    B  HalExcHandleEntry
+
+    NOP
+    END
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_interrupt.c
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_interrupt.c
@@ -0,0 +1,654 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_interrupt.h"
+#include "securec.h"
+#include <stdarg.h>
+#include "los_arch_interrupt.h"
+#include "los_context.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
+#include "los_cpup.h"
+#endif
+
+/*lint -save -e40 -e522 -e533*/
+UINT32 g_intCount = 0;
+
+/*lint -restore*/
+#pragma location = ".data.vector"
+#pragma data_alignment = LOSCFG_ARCH_HWI_VECTOR_ALIGN
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_DEBUG_TOOLS == 1)
+STATIC UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM] = {0};
+STATIC CHAR *g_hwiFormName[OS_HWI_MAX_NUM] = {0};
+
+UINT32 OsGetHwiFormCnt(UINT32 index)
+{
+    return g_hwiFormCnt[index];
+}
+
+CHAR *OsGetHwiFormName(UINT32 index)
+{
+    return g_hwiFormName[index];
+}
+
+BOOL OsGetHwiCreated(UINT32 index)
+{
+    if (g_hwiForm[index] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return TRUE;
+    }
+
+    return FALSE;
+}
+#endif
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+    HWI_PROC_FUNC pfnHandler;
+    VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+    }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+    }
+}
+#endif
+
+WEAK VOID SysTick_Handler(VOID)
+{
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HwiNumGet
+ Description : Get an interrupt number
+ Input       : None
+ Output      : None
+ Return      : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+    return __get_IPSR();
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+    return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function    : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+/*lint -e529*/
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+    while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+    UINT32 hwiIndex;
+    UINT32 intSave;
+
+#if (LOSCFG_KERNEL_RUNSTOP == 1)
+    SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
+#endif
+
+    intSave = LOS_IntLock();
+
+    g_intCount++;
+
+    LOS_IntRestore(intSave);
+
+    hwiIndex = HwiNumGet();
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
+    OsCpupIrqStart(hwiIndex);
+#endif
+
+    HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+        g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+    }
+#else
+    if (g_hwiHandlerForm[hwiIndex] != 0) {
+        g_hwiHandlerForm[hwiIndex]();
+    }
+#endif
+
+#if (LOSCFG_DEBUG_TOOLS == 1)
+    ++g_hwiFormCnt[hwiIndex];
+#endif
+
+    HalAftInterruptHandler(hwiIndex);
+
+#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
+    OsCpupIrqEnd(hwiIndex);
+#endif
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+    intSave = LOS_IntLock();
+    g_intCount--;
+    LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiCreate
+ Description : create hardware interrupt
+ Input       : hwiNum   --- hwi num to create
+               hwiPrio  --- priority of the hwi
+               hwiMode  --- unused
+               hwiHandler --- hwi handler
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T hwiMode,
+                                           HWI_PROC_FUNC hwiHandler,
+                                           HwiIrqParam *irqParam)
+{
+    (VOID)hwiMode;
+    UINTPTR intSave;
+
+    if (hwiHandler == NULL) {
+        return OS_ERRNO_HWI_PROC_FUNC_NULL;
+    }
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return OS_ERRNO_HWI_ALREADY_CREATED;
+    }
+
+    if (hwiPrio > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (irqParam != NULL) {
+        OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+    } else {
+        OsSetVector(hwiNum, hwiHandler, NULL);
+    }
+#else
+    (VOID)irqParam;
+    OsSetVector(hwiNum, hwiHandler);
+#endif
+
+#if (LOSCFG_DEBUG_TOOLS == 1)
+    if ((irqParam != NULL) && (irqParam->pName != NULL)) {
+        g_hwiFormName[hwiNum + OS_SYS_VECTOR_CNT] = (CHAR *)irqParam->pName;
+    }
+    g_hwiFormCnt[hwiNum + OS_SYS_VECTOR_CNT] = 0;
+#endif
+
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input       : hwiNum   --- hwi num to delete
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+    (VOID)irqParam;
+    UINT32 intSave;
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    intSave = LOS_IntLock();
+
+    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+#define FAULT_STATUS_REG_BIT            32
+#define USGFAULT                        (1 << 18)
+#define BUSFAULT                        (1 << 17)
+#define MEMFAULT                        (1 << 16)
+#define DIV0FAULT                       (1 << 4)
+#define HARDFAULT_IRQN                  (-13)
+
+ExcInfo g_excInfo = {0};
+
+UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
+    0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
+    0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
+    0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
+    0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
+};
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcNvicDump(VOID)
+{
+#define OS_NR_NVIC_EXC_DUMP_TYPES   7
+    UINT32 *base = NULL;
+    UINT32 len, i, j;
+    UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
+        OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
+    };
+    UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
+        OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
+        OS_NVIC_INT_CTRL_SIZE
+    };
+    CHAR strRgEnable[] = "enable";
+    CHAR strRgPending[] = "pending";
+    CHAR strRgActive[] = "active";
+    CHAR strRgPriority[] = "priority";
+    CHAR strRgException[] = "exception";
+    CHAR strRgShcsr[] = "shcsr";
+    CHAR strRgIntCtrl[] = "control";
+    CHAR *strRgs[] = {
+        strRgEnable, strRgPending, strRgActive, strRgPriority,
+        strRgException, strRgShcsr, strRgIntCtrl
+    };
+
+    PRINTK("\r\nOS exception NVIC dump:\n");
+    for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
+        base = (UINT32 *)rgNvicBases[i];
+        len = rgNvicLens[i];
+        PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
+        len = (len >> 2); /* 2: Gets the next register offset */
+        for (j = 0; j < len; j++) {
+            PRINTK("0x%x ", *(base + j));
+            if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
+                PRINTK("\n");
+            }
+        }
+        PRINTK("\n");
+    }
+}
+
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+    CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+    PRINTK("Type      = %d\n", excInfo->type);
+    PRINTK("ThrdPid   = %d\n", excInfo->thrdPid);
+    PRINTK("Phase     = %s\n", phaseStr[excInfo->phase]);
+    PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Current task info:\n");
+    if (excInfo->phase == OS_EXC_IN_TASK) {
+        LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+        PRINTK("Task name = %s\n", taskCB->taskName);
+        PRINTK("Task ID   = %d\n", taskCB->taskID);
+        PRINTK("Task SP   = %p\n", taskCB->stackPointer);
+        PRINTK("Task ST   = 0x%x\n", taskCB->topOfStack);
+        PRINTK("Task SS   = 0x%x\n", taskCB->stackSize);
+    } else if (excInfo->phase == OS_EXC_IN_HWI) {
+        PRINTK("Exception occur in interrupt phase!\n");
+    } else {
+        PRINTK("Exception occur in system init phase!\n");
+    }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Exception reg dump:\n");
+    PRINTK("PC        = 0x%x\n", excInfo->context->uwPC);
+    PRINTK("LR        = 0x%x\n", excInfo->context->uwLR);
+    PRINTK("SP        = 0x%x\n", excInfo->context->uwSP);
+    PRINTK("R0        = 0x%x\n", excInfo->context->uwR0);
+    PRINTK("R1        = 0x%x\n", excInfo->context->uwR1);
+    PRINTK("R2        = 0x%x\n", excInfo->context->uwR2);
+    PRINTK("R3        = 0x%x\n", excInfo->context->uwR3);
+    PRINTK("R4        = 0x%x\n", excInfo->context->uwR4);
+    PRINTK("R5        = 0x%x\n", excInfo->context->uwR5);
+    PRINTK("R6        = 0x%x\n", excInfo->context->uwR6);
+    PRINTK("R7        = 0x%x\n", excInfo->context->uwR7);
+    PRINTK("R8        = 0x%x\n", excInfo->context->uwR8);
+    PRINTK("R9        = 0x%x\n", excInfo->context->uwR9);
+    PRINTK("R10       = 0x%x\n", excInfo->context->uwR10);
+    PRINTK("R11       = 0x%x\n", excInfo->context->uwR11);
+    PRINTK("R12       = 0x%x\n", excInfo->context->uwR12);
+    PRINTK("PriMask   = 0x%x\n", excInfo->context->uwPriMask);
+    PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+    UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+    UINT32 index;
+
+    OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
+
+    PRINTK("----- backtrace start -----\n");
+    for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+        if (LR[index] == 0) {
+            break;
+        }
+        PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
+    }
+    PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+    PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+    MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+    UINT32 errCnt;
+    UINT32 i;
+
+    (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+    errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+    if (errCnt < OS_SYS_MEM_NUM) {
+        errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+    }
+
+    if (errCnt == 0) {
+        PRINTK("all memory pool check passed!\n");
+        return;
+    }
+
+    for (i = 0; i < errCnt; i++) {
+        PRINTK("pool num    = %d\n", i);
+        PRINTK("pool type   = %d\n", memExcInfo[i].type);
+        PRINTK("pool addr   = 0x%x\n", memExcInfo[i].startAddr);
+        PRINTK("pool size   = 0x%x\n", memExcInfo[i].size);
+        PRINTK("pool free   = 0x%x\n", memExcInfo[i].free);
+        PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
+        PRINTK("pool error node addr  = 0x%x\n", memExcInfo[i].errorAddr);
+        PRINTK("pool error node len   = 0x%x\n", memExcInfo[i].errorLen);
+        PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
+    }
+#endif
+    UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+    if (ret == LOS_OK) {
+        PRINTK("system heap memcheck over, all passed!\n");
+    }
+
+    PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+    PRINTK("*************Exception Information**************\n");
+    OsExcTypeInfo(excInfo);
+    OsExcCurTaskInfo(excInfo);
+    OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+    OsExcBackTraceInfo(excInfo);
+#endif
+    OsGetAllTskInfo();
+    OsExcNvicDump();
+    OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+    UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
+    g_intCount++;
+    g_excInfo.nestCnt++;
+
+    g_excInfo.type = excType & OS_NULL_SHORT;
+
+    if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
+        g_excInfo.faultAddr = faultAddr;
+    } else {
+        g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+    }
+    if (g_losTask.runTask != NULL) {
+        if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
+            g_excInfo.phase = OS_EXC_IN_HWI;
+            g_excInfo.thrdPid = pid;
+        } else {
+            g_excInfo.phase = OS_EXC_IN_TASK;
+            g_excInfo.thrdPid = g_losTask.runTask->taskID;
+        }
+    } else {
+        g_excInfo.phase = OS_EXC_IN_INIT;
+        g_excInfo.thrdPid = OS_NULL_INT;
+    }
+    if (excType & OS_EXC_FLAG_NO_FLOAT) {
+        g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
+    } else {
+        g_excInfo.context = excBufAddr;
+    }
+
+    OsDoExcHook(EXC_INTERRUPT);
+    OsExcInfoDisplay(&g_excInfo);
+    ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function    : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    UINT32 index;
+    g_hwiForm[0] = 0;             /* [0] Top of Stack */
+    g_hwiForm[1] = (HWI_PROC_FUNC)Reset_Handler; /* [1] reset */
+    for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
+        g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+    }
+    /* Exception handler register */
+    g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT]   = (HWI_PROC_FUNC)HalExcNMI;
+    g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT]        = (HWI_PROC_FUNC)HalExcHardFault;
+    g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault;
+    g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT]         = (HWI_PROC_FUNC)HalExcBusFault;
+    g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT]       = (HWI_PROC_FUNC)HalExcUsageFault;
+    g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT]           = (HWI_PROC_FUNC)HalSVCHandler;
+    g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT]           = (HWI_PROC_FUNC)HalPendSV;
+    g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT]          = (HWI_PROC_FUNC)SysTick_Handler;
+
+    /* Interrupt vector table location */
+    SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
+#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
+    NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
+#endif
+
+    /* Enable USGFAULT, BUSFAULT, MEMFAULT */
+    *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+    /* Enable DIV 0 and unaligned exception */
+    *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
+
+    return;
+}
+
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_timer.c
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_timer.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "los_tick.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+    UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
+
+    tick->freq = OS_SYS_CLOCK;
+
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
+#else
+    OsSetVector(tick->irqNum, handler);
+#endif
+#endif
+
+    ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
+    if (ret == 1) {
+        return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
+    }
+
+    return LOS_OK;
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+    if (nextResponseTime > g_archTickTimer.periodMax) {
+        nextResponseTime = g_archTickTimer.periodMax;
+    }
+
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
+    SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+    UINT32 hwCycle = 0;
+    UINTPTR intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
+    *period = SysTick->LOAD;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
+    LOS_IntRestore(intSave);
+    return (UINT64)hwCycle;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return LOS_OK;
+}
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_trustzone.c
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_trustzone.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_trustzone.h"
+#include "los_secure_macros.h"
+#include "los_secure_context.h"
+#include "los_debug.h"
+#include "los_arch_context.h"
+#include "los_interrupt.h"
+
+OsSecureContext *g_secureContext = NULL;
+
+VOID HalSecureSVCHandler(UINT32 svcID, UINTPTR arg)
+{
+    switch (svcID) {
+        case OS_SVC_START_SCHEDULE:
+            HalSecureContextInit();
+            HalStartFirstTask();
+            break;
+        case OS_SVC_ALLOCATE_SECURE_CONTEXT:
+            g_secureContext = HalSecureContextAlloc(arg);
+            LOS_ASSERT(g_secureContext != NULL);
+            HalSecureContextLoad(g_secureContext);
+            break;
+        case OS_SVC_FREE_SECURE_CONTEXT:
+            LOS_ASSERT(g_secureContext != NULL);
+            HalSecureContextFree(g_secureContext);
+            break;
+        default:
+            PRINT_ERR("Incorrect svc id = %u\n", svcID);
+            break;
+    }
+}
+
+VOID HalStartToRun(VOID)
+{
+    HalSVCStartSchedule();
+}
+
+VOID LOS_SecureContextAlloc(UINT32 secureStackSize)
+{
+    if (secureStackSize == 0) {
+        return;
+    }
+
+    LOS_ASSERT((__get_IPSR() == 0) && (__get_PRIMASK() == 0));
+    secureStackSize = LOS_Align(secureStackSize, sizeof(UINTPTR));
+    HalSVCSecureContextAlloc(secureStackSize);
+}
+
+VOID LOS_SecureContextFree(VOID)
+{
+    HalSVCSecureContextFree();
+}
+
--- a/arch/arm/cortex-m55/iar/TZ/non_secure/los_trustzone.h
+++ b/arch/arm/cortex-m55/iar/TZ/non_secure/los_trustzone.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_TRUSTZONE_H
+#define _LOS_TRUSTZONE_H
+
+#include "los_config.h"
+#include "los_task.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+extern VOID LOS_SecureContextAlloc(UINT32 secureStackSize);
+extern VOID LOS_SecureContextFree(VOID);
+
+extern VOID HalStartFirstTask(VOID);
+extern VOID HalSVCStartSchedule(VOID);
+extern VOID HalSVCSecureContextAlloc(UINT32 secureStackSize);
+extern VOID HalSVCSecureContextFree(VOID);
+extern VOID HalSVCHandler(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
+
--- a/arch/arm/cortex-m55/iar/TZ/secure/los_secure_context.c
+++ b/arch/arm/cortex-m55/iar/TZ/secure/los_secure_context.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_secure_context.h"
+#include "los_secure_macros.h"
+#include "los_secure_heap.h"
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextInit(VOID)
+{
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return;
+    }
+
+    HalSecureContextInitAsm();
+}
+
+OS_CMSE_NS_ENTRY OsSecureContext *HalSecureContextAlloc(UINT32 size)
+{
+    OsSecureContext *secureContext = NULL;
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return NULL;
+    }
+
+    secureContext = HalSecureMalloc(sizeof(OsSecureContext));
+    if (secureContext == NULL) {
+        return NULL;
+    }
+
+    secureContext->stackLimit = HalSecureMalloc(size);
+    if (secureContext->stackLimit == NULL) {
+        HalSecureFree(secureContext);
+        return NULL;
+    }
+
+    secureContext->stackStart = secureContext->stackLimit + size;
+    secureContext->curStackPointer = secureContext->stackStart;
+
+    return secureContext;
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextFree(OsSecureContext *secureContext)
+{
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return;
+    }
+
+    HalSecureFree(secureContext->stackLimit);
+    secureContext->stackLimit = NULL;
+    HalSecureFree(secureContext);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextLoad(OsSecureContext *secureContext)
+{
+    HalSecureContextLoadAsm(secureContext);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextSave(OsSecureContext *secureContext)
+{
+    HalSecureContextSaveAsm(secureContext);
+}
+
--- a/arch/arm/cortex-m55/iar/TZ/secure/los_secure_context.h
+++ b/arch/arm/cortex-m55/iar/TZ/secure/los_secure_context.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_SECURE_CONTEXT_H
+#define _LOS_SECURE_CONTEXT_H
+
+#include "los_config.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct {
+    UINT8 *curStackPointer;
+    UINT8 *stackLimit;
+    UINT8 *stackStart;
+} OsSecureContext;
+
+extern VOID HalSecureContextInit(VOID);
+extern OsSecureContext *HalSecureContextAlloc(UINT32 size);
+extern VOID HalSecureContextFree(OsSecureContext *secureContext);
+extern VOID HalSecureContextLoad(OsSecureContext *secureContext);
+extern VOID HalSecureContextSave(OsSecureContext *secureContext);
+
+extern VOID HalSecureContextInitAsm(VOID);
+extern VOID HalSecureContextLoadAsm(OsSecureContext *secureContext);
+extern VOID HalSecureContextSaveAsm(OsSecureContext *secureContext);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
--- a/arch/arm/cortex-m55/iar/TZ/secure/los_secure_context_asm.S
+++ b/arch/arm/cortex-m55/iar/TZ/secure/los_secure_context_asm.S
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    PRESERVE8
+
+    EXPORT HalSecureContextInitAsm
+    EXPORT HalSecureContextLoadAsm
+    EXPORT HalSecureContextSaveAsm
+
+OS_SECURE_SCB_AIRCR     EQU     0xE000ED0C
+
+    SECTION     .text:CODE(2)
+    THUMB
+    REQUIRE8
+
+HalSecureContextInitAsm
+    LDR     R0, =OS_SECURE_SCB_AIRCR
+    LDR     R1, [R0]
+
+    MOV     R2, #0xFFFF
+    LSL     R2, R2, #16
+    BIC     R1, R1, R2
+    MOV     R2, #0x05FA
+    LSL     R2, R2, #16
+    ORR     R1, R1, R2
+
+    BIC     R1, R1, #0x4000
+    MOV     R2, #0x4000
+    ORR     R1, R1, R2
+    STR     R1, [R0]
+
+    MOV     R0, #0
+    MSR     PSPLIM, R0
+    MSR     PSP, R0
+    MOV     R0, #2
+    MSR     CONTROL, R0 
+    BX      LR
+
+HalSecureContextLoadAsm
+    MRS     R1, IPSR
+    CBZ     R1, __ThreadMode
+
+    LDMIA   R0!, {R1, R2}               /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext->stackLimit. */
+    MSR     PSPLIM, R2                  /* Restore PSPLIM. */
+    MSR     PSP, R1                     /* Restore PSP. */
+    BX      LR
+
+HalSecureContextSaveAsm
+    MRS     R0, IPSR
+    CBZ     R0, __ThreadMode
+
+    MRS     R0, PSP
+    STR     R0, [R1]                    /* g_secureContext->curStackPointer = R0. */
+    MOV     R0, #0
+    MSR     PSPLIM, R0                  /* No PSPLIM for the current task. */
+    MSR     PSP, R0                     /* No secure stack for the current task. */
+
+__ThreadMode
+    BX      LR
+
+    END
--- a/arch/arm/cortex-m55/iar/TZ/secure/los_secure_heap.c
+++ b/arch/arm/cortex-m55/iar/TZ/secure/los_secure_heap.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_secure_heap.h"
+#include "los_secure_macros.h"
+#include "los_config.h"
+#include "los_list.h"
+
+#pragma data_alignment = 0x4
+STATIC UINT8 g_secureHeap[LOSCFG_SECURE_HEAP_SIZE] = {0};
+STATIC LOS_DL_LIST g_secureHeapFreeList = {NULL, NULL};
+
+struct OsSecureHeapNode {
+    LOS_DL_LIST freeNode;
+    struct OsSecureHeapNode *preNode;
+    UINT32 size : 24;
+    UINT32 used : 8;
+};
+
+#define OS_SECURE_HEAP_NODE_HEAD_SIZE   sizeof(struct OsSecureHeapNode)
+#define OS_SECURE_HEAP_ALIGN_SIZE       sizeof(UINTPTR)
+
+#define OS_SECURE_HEAP_NODE_USED        1
+#define OS_SECURE_HEAP_NODE_FREE        0
+
+#define OS_SECURE_HEAP_FIRST_NODE     ((struct OsSecureHeapNode *)g_secureHeap)
+#define OS_SECURE_HEAP_NEXT_NODE(node) \
+    ((struct OsSecureHeapNode *)((UINT8 *)(node) + (node)->size))
+#define OS_SECURE_HEAP_END_NODE \
+    ((struct OsSecureHeapNode *)((UINT8 *)g_secureHeap + LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE))
+
+STATIC INLINE VOID OsSecureHeapListInit(LOS_DL_LIST *head)
+{
+    head->pstPrev = head;
+    head->pstNext = head;
+}
+
+STATIC INLINE VOID OsSecureHeapListDelete(LOS_DL_LIST *node)
+{
+    node->pstNext->pstPrev = node->pstPrev;
+    node->pstPrev->pstNext = node->pstNext;
+    node->pstNext = NULL;
+    node->pstPrev = NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapListAdd(LOS_DL_LIST *listNode, LOS_DL_LIST *node)
+{
+    node->pstNext = listNode->pstNext;
+    node->pstPrev = listNode;
+    listNode->pstNext->pstPrev = node;
+    listNode->pstNext = node;
+}
+
+STATIC struct OsSecureHeapNode *OsSecureHeapFindSuitableFreeBlock(UINT32 allocSize)
+{
+    LOS_DL_LIST *listNodeHead = &g_secureHeapFreeList;
+    struct OsSecureHeapNode *tmpNode = NULL;
+
+    LOS_DL_LIST_FOR_EACH_ENTRY(tmpNode, listNodeHead, struct OsSecureHeapNode, freeNode) {
+        if (tmpNode->size >= allocSize) {
+            return tmpNode;
+        }
+    }
+
+    return NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapClearNode(struct OsSecureHeapNode *node)
+{
+    node->preNode = NULL;
+    node->size = 0;
+    node->used = 0;
+    node->freeNode.pstPrev = NULL;
+    node->freeNode.pstNext = NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapMergeNode(struct OsSecureHeapNode *node)
+{
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    node->preNode->size += node->size;
+    nextNode = (struct OsSecureHeapNode *)((UINTPTR)node + node->size);
+    nextNode->preNode = node->preNode;
+    OsSecureHeapClearNode(node);
+}
+
+STATIC INLINE VOID OsSecureHeapSplitNode(struct OsSecureHeapNode *allocNode, UINT32 allocSize)
+{
+    struct OsSecureHeapNode *newFreeNode = NULL;
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    newFreeNode = (struct OsSecureHeapNode *)((UINT8 *)allocNode + allocSize);
+    newFreeNode->preNode = allocNode;
+    newFreeNode->size = allocNode->size - allocSize;
+    newFreeNode->used = OS_SECURE_HEAP_NODE_FREE;
+    allocNode->size = allocSize;
+    nextNode = OS_SECURE_HEAP_NEXT_NODE(newFreeNode);
+    nextNode->preNode = newFreeNode;
+    if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+        OsSecureHeapListDelete(&nextNode->freeNode);
+        OsSecureHeapMergeNode(nextNode);
+    }
+
+    OsSecureHeapListAdd(&g_secureHeapFreeList, &newFreeNode->freeNode);
+}
+
+STATIC INLINE VOID OsSecureHeapFreeNode(struct OsSecureHeapNode *node)
+{
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    if ((node->preNode != NULL) && (node->preNode->used == OS_SECURE_HEAP_NODE_FREE)) {
+        struct OsSecureHeapNode *preNode = node->preNode;
+        OsSecureHeapMergeNode(node);
+        nextNode = OS_SECURE_HEAP_NEXT_NODE(preNode);
+        if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+            OsSecureHeapListDelete(&nextNode->freeNode);
+            OsSecureHeapMergeNode(nextNode);
+        }
+
+        OsSecureHeapListDelete(&preNode->freeNode);
+        preNode->used = OS_SECURE_HEAP_NODE_FREE;
+        OsSecureHeapListAdd(&g_secureHeapFreeList, &preNode->freeNode);
+    } else {
+        nextNode = OS_SECURE_HEAP_NEXT_NODE(node);
+        if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+            OsSecureHeapListDelete(&nextNode->freeNode);
+            OsSecureHeapMergeNode(nextNode);
+        }
+
+        node->used = OS_SECURE_HEAP_NODE_FREE;
+        OsSecureHeapListAdd(&g_secureHeapFreeList, &node->freeNode);
+    }
+}
+
+STATIC INLINE VOID *OsSecureHeapAllocNode(UINT32 size)
+{
+    struct OsSecureHeapNode *allocNode = NULL;
+    UINT32 allocSize;
+
+    allocSize = LOS_Align(size + OS_SECURE_HEAP_NODE_HEAD_SIZE, OS_SECURE_HEAP_ALIGN_SIZE);
+    allocNode = OsSecureHeapFindSuitableFreeBlock(allocSize);
+    if (allocNode == NULL) {
+        return NULL;
+    }
+    if ((allocSize + OS_SECURE_HEAP_NODE_HEAD_SIZE + OS_SECURE_HEAP_ALIGN_SIZE) <= allocNode->size) {
+        OsSecureHeapSplitNode(allocNode, allocSize);
+    }
+    OsSecureHeapListDelete(&allocNode->freeNode);
+    allocNode->used = OS_SECURE_HEAP_NODE_USED;
+
+    return (allocNode + 1);
+}
+
+STATIC INLINE VOID OsSecureHeapInit(VOID)
+{
+    struct OsSecureHeapNode *newNode = NULL;
+    struct OsSecureHeapNode *endNode = NULL;
+
+    newNode = OS_SECURE_HEAP_FIRST_NODE;
+    newNode->size = LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE;
+    newNode->preNode = OS_SECURE_HEAP_END_NODE;
+    newNode->used = OS_SECURE_HEAP_NODE_FREE;
+
+    OsSecureHeapListInit(&g_secureHeapFreeList);
+    OsSecureHeapListAdd(&g_secureHeapFreeList, &newNode->freeNode);
+
+    endNode = OS_SECURE_HEAP_END_NODE;
+    endNode->preNode = newNode;
+    endNode->size = OS_SECURE_HEAP_NODE_HEAD_SIZE;
+    endNode->used = OS_SECURE_HEAP_NODE_USED;
+}
+
+OS_CMSE_NS_ENTRY VOID *HalSecureMalloc(UINT32 size)
+{
+    if (size == 0) {
+        return NULL;
+    }
+
+    if ((g_secureHeapFreeList.pstPrev == NULL) &&
+        (g_secureHeapFreeList.pstNext == NULL)) {
+        OsSecureHeapInit();
+    }
+
+    return OsSecureHeapAllocNode(size);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureFree(VOID *ptr)
+{
+    struct OsSecureHeapNode *node = NULL;
+
+    if (ptr == NULL) {
+        return;
+    }
+
+    node = (struct OsSecureHeapNode *)((UINTPTR)ptr - OS_SECURE_HEAP_NODE_HEAD_SIZE);
+    if (node->used != OS_SECURE_HEAP_NODE_USED) {
+        return;
+    }
+
+    OsSecureHeapFreeNode(node);
+}
+
--- a/arch/arm/cortex-m55/iar/TZ/secure/los_secure_heap.h
+++ b/arch/arm/cortex-m55/iar/TZ/secure/los_secure_heap.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_SECURE_HEAP_H
+#define _LOS_SECURE_HEAP_H
+
+#include "los_config.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+VOID *HalSecureMalloc(UINT32 size);
+VOID HalSecureFree(VOID *ptr);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
+
--- a/arch/arm/cortex-m55/iar/TZ/secure/los_secure_macros.h
+++ b/arch/arm/cortex-m55/iar/TZ/secure/los_secure_macros.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_SECURE_MACROS_H
+#define _LOS_SECURE_MACROS_H
+
+#include "los_config.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#define OS_CMSE_NS_ENTRY      __attribute__((cmse_nonsecure_entry))
+#define OS_CMSE_NS_CALL       __attribute__((cmse_nonsecure_call))
+#define OS_IPSR_READ(ipsr)    __asm volatile("MRS %0, IPSR" : "=r" (ipsr))
+
+#define OS_SVC_ALLOCATE_SECURE_CONTEXT  0
+#define OS_SVC_FREE_SECURE_CONTEXT      1
+#define OS_SVC_START_SCHEDULE           2
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
+
--- a/arch/arm/cortex-m7/gcc/los_arch_atomic.h
+++ b/arch/arm/cortex-m7/gcc/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m7/gcc/los_context.c
+++ b/arch/arm/cortex-m7/gcc/los_context.c
@@ -59,7 +59,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/arm/cortex-m7/iar/los_arch_atomic.h
+++ b/arch/arm/cortex-m7/iar/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/arm/cortex-m7/iar/los_context.c
+++ b/arch/arm/cortex-m7/iar/los_context.c
@@ -59,7 +59,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/csky/v2/gcc/los_arch_atomic.h
+++ b/arch/csky/v2/gcc/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/csky/v2/gcc/los_context.c
+++ b/arch/csky/v2/gcc/los_context.c
@@ -63,7 +63,7 @@ LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    LOS_IntLock();
+    (VOID)LOS_IntLock();
    while (1) {
    }
 }
--- a/arch/csky/v2/gcc/los_interrupt.c
+++ b/arch/csky/v2/gcc/los_interrupt.c
@@ -612,7 +612,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
    HalHwiHandleReInit((UINT32)&g_hwiForm);

    HalSetVbr((UINT32)&g_hwiForm);
-    for (int i = 0; i < BYTES_OF_128_INT; i++) {
+    for (i = 0; i < BYTES_OF_128_INT; i++) {
        VIC_REG->IABR[i] = 0x0;
        VIC_REG->ICPR[i] = MASK_32_BITS;
    }
--- a/arch/include/los_arch.h
+++ b/arch/include/los_arch.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -62,6 +62,14 @@ STATIC INLINE UINTPTR ArchMspGet(VOID)
    __asm("mrs %0, msp" : "=r" (msp));
    return msp;
 }
+
+#define ARCH_LR_GET()                           \
+({                                              \
+    UINTPTR lr;                                 \
+    __asm("mov %0, lr" : "=r" (lr));            \
+    (lr);                                       \
+})
+#define ArchLRGet ARCH_LR_GET
 #elif defined(__CLANG_ARM) || defined(__GNUC__)
 STATIC INLINE UINTPTR ArchSpGet(VOID)
 {
@@ -83,6 +91,14 @@ STATIC INLINE UINTPTR ArchMspGet(VOID)
    __asm volatile("mrs %0, msp" : "=r" (msp));
    return msp;
 }
+
+#define ARCH_LR_GET()                           \
+({                                              \
+    UINTPTR lr;                                 \
+    __asm volatile("mov %0, lr" : "=r" (lr));   \
+    (lr);                                       \
+})
+#define ArchLRGet ARCH_LR_GET
 #else
 /* Other platforms to be improved  */
 #endif
--- a/arch/include/los_interrupt.h
+++ b/arch/include/los_interrupt.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -107,13 +107,16 @@ UINT32 ArchIntUnLock(VOID);
 *
 * @attention
 * <ul>
- * <li>The hardware interrupt module is usable only when the configuration item for hardware interrupt tailoring is enabled.</li>
- * <li>Hardware interrupt number value range: [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. The value range applicable for a Cortex-A7 platform is [32,95].</li>
+ * <li>The hardware interrupt module is usable only when the configuration item for hardware
+ * interrupt tailoring is enabled.</li>
+ * <li>Hardware interrupt number value range: [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. The value range
+ * applicable for a Cortex-A7 platform is [32,95].</li>
 * <li>OS_HWI_MAX_NUM specifies the maximum number of interrupts that can be created.</li>
 * <li>Before executing an interrupt on a platform, refer to the chip manual of the platform.</li>
 * </ul>
 *
- * @param  hwiNum   [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable for a Cortex-A7 platform is [32,95].
+ * @param  hwiNum   [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable
+ *                       for a Cortex-A7 platform is [32,95].
 * @param  irqParam [IN] Type #HwiIrqParam *. ID of hardware interrupt which will base on
 *                                                when delete the hardware interrupt.
 * @retval #OS_ERRNO_HWI_NUM_INVALID              0x02000900: Invalid interrupt number.
@@ -133,13 +136,16 @@ UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam);
 *
 * @attention
 * <ul>
- * <li>The hardware interrupt module is usable only when the configuration item for hardware interrupt tailoring is enabled.</li>
- * <li>Hardware interrupt number value range: [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. The value range applicable for a Cortex-A7 platform is [32,95].</li>
+ * <li>The hardware interrupt module is usable only when the configuration item for hardware
+ * interrupt tailoring is enabled.</li>
+ * <li>Hardware interrupt number value range: [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. The value range
+ * applicable for a Cortex-A7 platform is [32,95].</li>
 * <li>OS_HWI_MAX_NUM specifies the maximum number of interrupts that can be created.</li>
 * <li>Before executing an interrupt on a platform, refer to the chip manual of the platform.</li>
 * </ul>
 *
- * @param  hwiNum   [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable for a Cortex-A7 platform is [32,95].
+ * @param  hwiNum   [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable for a
+ *                       Cortex-A7 platform is [32,95].
 * @param  hwiPrio  [IN] Type#HWI_PRIOR_T: hardware interrupt priority. Ignore this parameter temporarily.
 * @param  mode     [IN] Type#HWI_MODE_T: hardware interrupt mode. Ignore this parameter temporarily.
 * @param  handler  [IN] Type#HWI_PROC_FUNC: interrupt handler used when a hardware interrupt is triggered.
@@ -149,7 +155,8 @@ UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam);
 * @retval #OS_ERRNO_HWI_PROC_FUNC_NULL               0x02000901: Null hardware interrupt handling function.
 * @retval #OS_ERRNO_HWI_NUM_INVALID                  0x02000900: Invalid interrupt number.
 * @retval #OS_ERRNO_HWI_NO_MEMORY                    0x02000903: Insufficient memory for hardware interrupt creation.
- * @retval #OS_ERRNO_HWI_ALREADY_CREATED              0x02000904: The interrupt handler being created has already been created.
+ * @retval #OS_ERRNO_HWI_ALREADY_CREATED              0x02000904: The interrupt handler being created has
+ *                                                                already been created.
 * @retval #LOS_OK                                    0         : The interrupt is successfully created.
 * @par Dependency:
 * <ul><li>los_interrupt.h: the header file that contains the API declaration.</li></ul>
--- a/arch/risc-v/nuclei/gcc/los_arch_atomic.h
+++ b/arch/risc-v/nuclei/gcc/los_arch_atomic.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #define _LOS_ARCH_ATOMIC_H

 #include "los_compiler.h"
+#include "los_interrupt.h"

 #ifdef __cplusplus
 #if __cplusplus
--- a/arch/risc-v/nuclei/gcc/nmsis/DSP/Include/riscv_common_tables.h
+++ b/arch/risc-v/nuclei/gcc/nmsis/DSP/Include/riscv_common_tables.h
@@ -1,379 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      NMSIS DSP Library
- * Title:        riscv_common_tables.h
- * Description:  Extern declaration for common tables
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: RISC-V Cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- * Copyright (c) 2019 Nuclei Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _RISCV_COMMON_TABLES_H
-#define _RISCV_COMMON_TABLES_H
-
-#include "riscv_math.h"
-
-#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_ALLOW_TABLES) 
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREV_1024)
-    extern const uint16_t riscvBitRevTable[1024];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_16)
-    extern const float32_t twiddleCoef_16[32];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_32)
-    extern const float32_t twiddleCoef_32[64];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_64)
-    extern const float32_t twiddleCoef_64[128];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_128)
-    extern const float32_t twiddleCoef_128[256];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_256)
-    extern const float32_t twiddleCoef_256[512];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_512)
-    extern const float32_t twiddleCoef_512[1024];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_1024)
-    extern const float32_t twiddleCoef_1024[2048];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_2048)
-    extern const float32_t twiddleCoef_2048[4096];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_F32_4096)
-    extern const float32_t twiddleCoef_4096[8192];
-    #define twiddleCoef twiddleCoef_4096
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_16)
-    extern const q31_t twiddleCoef_16_q31[24];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_32)
-    extern const q31_t twiddleCoef_32_q31[48];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_64)
-    extern const q31_t twiddleCoef_64_q31[96];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_128)
-    extern const q31_t twiddleCoef_128_q31[192];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_256)
-    extern const q31_t twiddleCoef_256_q31[384];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_512)
-    extern const q31_t twiddleCoef_512_q31[768];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_1024)
-    extern const q31_t twiddleCoef_1024_q31[1536];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_2048)
-    extern const q31_t twiddleCoef_2048_q31[3072];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q31_4096)
-    extern const q31_t twiddleCoef_4096_q31[6144];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_16)
-    extern const q15_t twiddleCoef_16_q15[24];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_32)
-    extern const q15_t twiddleCoef_32_q15[48];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_64)
-    extern const q15_t twiddleCoef_64_q15[96];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_128)
-    extern const q15_t twiddleCoef_128_q15[192];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_256)
-    extern const q15_t twiddleCoef_256_q15[384];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_512)
-    extern const q15_t twiddleCoef_512_q15[768];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_1024)
-    extern const q15_t twiddleCoef_1024_q15[1536];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_2048)
-    extern const q15_t twiddleCoef_2048_q15[3072];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_Q15_4096)
-    extern const q15_t twiddleCoef_4096_q15[6144];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_32)
-    extern const float32_t twiddleCoef_rfft_32[32];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_64)
-    extern const float32_t twiddleCoef_rfft_64[64];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_128)
-    extern const float32_t twiddleCoef_rfft_128[128];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_256)
-    extern const float32_t twiddleCoef_rfft_256[256];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_512)
-    extern const float32_t twiddleCoef_rfft_512[512];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_1024)
-    extern const float32_t twiddleCoef_rfft_1024[1024];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_2048)
-    extern const float32_t twiddleCoef_rfft_2048[2048];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_TWIDDLECOEF_RFFT_F32_4096)
-    extern const float32_t twiddleCoef_rfft_4096[4096];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  /* floating-point bit reversal tables */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_16)
-    #define RISCVBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
-    extern const uint16_t riscvBitRevIndexTable16[RISCVBITREVINDEXTABLE_16_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_32)
-    #define RISCVBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
-    extern const uint16_t riscvBitRevIndexTable32[RISCVBITREVINDEXTABLE_32_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_64)
-    #define RISCVBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
-    extern const uint16_t riscvBitRevIndexTable64[RISCVBITREVINDEXTABLE_64_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_128)
-    #define RISCVBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
-    extern const uint16_t riscvBitRevIndexTable128[RISCVBITREVINDEXTABLE_128_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_256)
-    #define RISCVBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
-    extern const uint16_t riscvBitRevIndexTable256[RISCVBITREVINDEXTABLE_256_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_512)
-    #define RISCVBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
-    extern const uint16_t riscvBitRevIndexTable512[RISCVBITREVINDEXTABLE_512_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_1024)
-    #define RISCVBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
-    extern const uint16_t riscvBitRevIndexTable1024[RISCVBITREVINDEXTABLE_1024_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_2048)
-    #define RISCVBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
-    extern const uint16_t riscvBitRevIndexTable2048[RISCVBITREVINDEXTABLE_2048_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FLT_4096)
-    #define RISCVBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
-    extern const uint16_t riscvBitRevIndexTable4096[RISCVBITREVINDEXTABLE_4096_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  
-  /* fixed-point bit reversal tables */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_16)
-    #define RISCVBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
-    extern const uint16_t riscvBitRevIndexTable_fixed_16[RISCVBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_32)
-    #define RISCVBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
-    extern const uint16_t riscvBitRevIndexTable_fixed_32[RISCVBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_64)
-    #define RISCVBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
-    extern const uint16_t riscvBitRevIndexTable_fixed_64[RISCVBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_128)
-    #define RISCVBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
-    extern const uint16_t riscvBitRevIndexTable_fixed_128[RISCVBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_256)
-    #define RISCVBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
-    extern const uint16_t riscvBitRevIndexTable_fixed_256[RISCVBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_512)
-    #define RISCVBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
-    extern const uint16_t riscvBitRevIndexTable_fixed_512[RISCVBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_1024)
-    #define RISCVBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
-    extern const uint16_t riscvBitRevIndexTable_fixed_1024[RISCVBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_2048)
-    #define RISCVBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-    extern const uint16_t riscvBitRevIndexTable_fixed_2048[RISCVBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_BITREVIDX_FXT_4096)
-    #define RISCVBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-    extern const uint16_t riscvBitRevIndexTable_fixed_4096[RISCVBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) */
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_F32)
-    extern const float32_t realCoefA[8192];
-    extern const float32_t realCoefB[8192];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_Q31)
-    extern const q31_t realCoefAQ31[8192];
-    extern const q31_t realCoefBQ31[8192];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_REALCOEF_Q15)
-    extern const q15_t realCoefAQ15[8192];
-    extern const q15_t realCoefBQ15[8192];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_128)
-    extern const float32_t Weights_128[256];
-    extern const float32_t cos_factors_128[128];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_512)
-    extern const float32_t Weights_512[1024];
-    extern const float32_t cos_factors_512[512];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_2048)
-    extern const float32_t Weights_2048[4096];
-    extern const float32_t cos_factors_2048[2048];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_F32_8192)
-    extern const float32_t Weights_8192[16384];
-    extern const float32_t cos_factors_8192[8192];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_128)
-    extern const q15_t WeightsQ15_128[256];
-    extern const q15_t cos_factorsQ15_128[128];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_512)
-    extern const q15_t WeightsQ15_512[1024];
-    extern const q15_t cos_factorsQ15_512[512];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_2048)
-    extern const q15_t WeightsQ15_2048[4096];
-    extern const q15_t cos_factorsQ15_2048[2048];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q15_8192)
-    extern const q15_t WeightsQ15_8192[16384];
-    extern const q15_t cos_factorsQ15_8192[8192];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_128)  
-    extern const q31_t WeightsQ31_128[256];
-    extern const q31_t cos_factorsQ31_128[128];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_512) 
-    extern const q31_t WeightsQ31_512[1024];
-    extern const q31_t cos_factorsQ31_512[512];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_2048) 
-    extern const q31_t WeightsQ31_2048[4096];
-    extern const q31_t cos_factorsQ31_2048[2048];
-  #endif
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FFT_TABLES) || defined(RISCV_TABLE_DCT4_Q31_8192) 
-    extern const q31_t WeightsQ31_8192[16384];
-    extern const q31_t cos_factorsQ31_8192[8192];
-  #endif
-    
-#endif /* if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FFT_TABLES) */
-
-#if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FAST_ALLOW_TABLES)
-
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_RECIP_Q15)
-    extern const q15_t riscvRecipTableQ15[64];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_RECIP_Q31)
-    extern const q31_t riscvRecipTableQ31[64];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */
-  
-  /* Tables for Fast Math Sine and Cosine */
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_F32)
-    extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q31)
-    extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */
-  
-  #if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_ALL_FAST_TABLES) || defined(RISCV_TABLE_SIN_Q15)
-    extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-  #endif /* !defined(RISCV_DSP_CONFIG_TABLES) defined(RISCV_ALL_FAST_TABLES) */
-
-#endif /* if !defined(RISCV_DSP_CONFIG_TABLES) || defined(RISCV_FAST_TABLES) */
-
-#endif /*  RISCV_COMMON_TABLES_H */
--- a/arch/risc-v/nuclei/gcc/nmsis/DSP/Include/riscv_const_structs.h
+++ b/arch/risc-v/nuclei/gcc/nmsis/DSP/Include/riscv_const_structs.h
@@ -1,67 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      NMSIS DSP Library
- * Title:        riscv_const_structs.h
- * Description:  Constant structs that are initialized for user convenience.
- *               For example, some can be given as arguments to the riscv_cfft_f32() function.
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: RISC-V Cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- * Copyright (c) 2019 Nuclei Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _RISCV_CONST_STRUCTS_H
-#define _RISCV_CONST_STRUCTS_H
-
-#include "riscv_math.h"
-#include "riscv_common_tables.h"
-
-   extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len16;
-   extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len32;
-   extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len64;
-   extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len128;
-   extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len256;
-   extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len512;
-   extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len1024;
-   extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len2048;
-   extern const riscv_cfft_instance_f32 riscv_cfft_sR_f32_len4096;
-
-   extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len16;
-   extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len32;
-   extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len64;
-   extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len128;
-   extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len256;
-   extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len512;
-   extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len1024;
-   extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len2048;
-   extern const riscv_cfft_instance_q31 riscv_cfft_sR_q31_len4096;
-
-   extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len16;
-   extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len32;
-   extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len64;
-   extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len128;
-   extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len256;
-   extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len512;
-   extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len1024;
-   extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len2048;
-   extern const riscv_cfft_instance_q15 riscv_cfft_sR_q15_len4096;
-
-#endif
--- a/arch/risc-v/nuclei/gcc/nmsis/DSP/Include/riscv_math.h
+++ b/arch/risc-v/nuclei/gcc/nmsis/DSP/Include/riscv_math.h
--- a/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imac.a
+++ b/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imac.a
--- a/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imacp.a
+++ b/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imacp.a
--- a/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imafc.a
+++ b/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imafc.a
--- a/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imafcp.a
+++ b/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imafcp.a
--- a/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imafdc.a
+++ b/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imafdc.a
--- a/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imafdcp.a
+++ b/arch/risc-v/nuclei/gcc/nmsis/Library/DSP/GCC/libnmsis_dsp_rv32imafdcp.a
--- a/Show More
+++ b/Show More