!901 risc-v系统异常时无法输出异常信息

Merge pull request !901 from zhushengle/medeleg
2022-11-10 10:30:50 +00:00
parent 2f08268983 914913fab6
commit 1cd2ae7b4e
1 changed files with 1 additions and 2 deletions
--- a/arch/risc-v/riscv32/gcc/los_exc.S
+++ b/arch/risc-v/riscv32/gcc/los_exc.S
@@ -139,8 +139,7 @@ HalTrapEntry:
    sw    a0, 0 * REGBYTES(sp)
    csrr  t0, mtval
    sw    t0, 1 * REGBYTES(sp)
-    csrr  t0, medeleg
-    sw    t0, 2 * REGBYTES(sp)
+    sw    zero, 2 * REGBYTES(sp)
    sw    gp, 3 * REGBYTES(sp)
    mv    a0, sp
    csrw  mscratch, sp