task: risc-v系统异常时取消对medeleg寄存器的保存

部分开源架构不支持该寄存器，且非常用寄存器 Close #I60IS5 Signed-off-by: zhushengle <zhushengle@huawei.com> Change-Id: I8db31f84a24cc6143513c725691e4ba780ca99e9
2022-11-10 16:07:37 +08:00 · 2022-11-10 16:07:37 +08:00 · 914913fab6
parent 2f08268983
commit 914913fab6
1 changed files with 1 additions and 2 deletions
--- a/arch/risc-v/riscv32/gcc/los_exc.S
+++ b/arch/risc-v/riscv32/gcc/los_exc.S
@ -139,8 +139,7 @@ HalTrapEntry:
    sw    a0, 0 * REGBYTES(sp)
    csrr  t0, mtval
    sw    t0, 1 * REGBYTES(sp)
-    csrr  t0, medeleg
-    sw    t0, 2 * REGBYTES(sp)
+    sw    zero, 2 * REGBYTES(sp)
    sw    gp, 3 * REGBYTES(sp)
    mv    a0, sp
    csrw  mscratch, sp