feature: 新增cortex-m55的iar与trustzone支持
close: #I5G26W Signed-off-by: arvinzzz <zhaotianyu9@huawei.com> Change-Id: I1fbcbc6530085902afa86dc04c1760ffe5e97483
This commit is contained in:
parent
85663b9258
commit
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# Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without modification,
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# are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
# conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
# of conditions and the following disclaimer in the documentation and/or other materials
|
||||
# provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
# to endorse or promote products derived from this software without specific prior written
|
||||
# permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import("//kernel/liteos_m/liteos.gni")
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module_group("iar") {
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if (defined(LOSCFG_SECURE_TRUSTZONE)) {
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modules = [ "TZ" ]
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} else {
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modules = [ "NTZ" ]
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}
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}
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@ -0,0 +1,45 @@
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# Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without modification,
|
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# are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
# conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
# of conditions and the following disclaimer in the documentation and/or other materials
|
||||
# provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
# to endorse or promote products derived from this software without specific prior written
|
||||
# permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import("//kernel/liteos_m/liteos.gni")
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module_name = "arch"
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kernel_module(module_name) {
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sources = [
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"los_context.c",
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"los_dispatch.S",
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"los_exc.S",
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"los_interrupt.c",
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"los_timer.c",
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]
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configs += [ "$LITEOSTOPDIR:warn_config" ]
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}
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config("public") {
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include_dirs = [ "." ]
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}
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# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
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# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without modification,
|
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# are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
# conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
# of conditions and the following disclaimer in the documentation and/or other materials
|
||||
# provided with the distribution.
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||||
#
|
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# 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
# to endorse or promote products derived from this software without specific prior written
|
||||
# permission.
|
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#
|
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
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# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import("//kernel/liteos_m/liteos.gni")
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module_name = "arch"
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kernel_module(module_name) {
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sources = [
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"non_secure/los_context.c",
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"non_secure/los_dispatch.S",
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"non_secure/los_exc.S",
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"non_secure/los_interrupt.c",
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"non_secure/los_timer.c",
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"non_secure/los_trustzone.c",
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]
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configs += [ "$LITEOSTOPDIR:warn_config" ]
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include_dirs = [
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"non_secure",
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"secure",
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]
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}
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config("public") {
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include_dirs = [ "non_secure" ]
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}
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/*
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* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
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* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
|
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* are permitted provided that the following conditions are met:
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*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _LOS_ARCH_ATOMIC_H
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#define _LOS_ARCH_ATOMIC_H
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#include "los_compiler.h"
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#ifdef __cplusplus
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#if __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#endif /* __cplusplus */
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STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
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{
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INT32 val;
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__asm__ __volatile__("ldrex %0, [%1]\n"
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: "=&r"(val)
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: "r"(v)
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: "cc");
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return val;
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}
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STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
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{
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UINT32 status;
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do {
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__asm__ __volatile__("ldrex %0, [%1]\n"
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"strex %0, %2, [%1]\n"
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: "=&r"(status)
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: "r"(v), "r"(setVal)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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}
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STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
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{
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INT32 val;
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UINT32 status;
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do {
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__asm__ __volatile__("ldrex %1, [%2]\n"
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"add %1, %1, %3\n"
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"strex %0, %1, [%2]"
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: "=&r"(status), "=&r"(val)
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: "r"(v), "r"(addVal)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return val;
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}
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STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
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{
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INT32 val;
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UINT32 status;
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do {
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__asm__ __volatile__("ldrex %1, [%2]\n"
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"sub %1, %1, %3\n"
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"strex %0, %1, [%2]"
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: "=&r"(status), "=&r"(val)
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: "r"(v), "r"(subVal)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return val;
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}
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STATIC INLINE VOID ArchAtomicInc(Atomic *v)
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{
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(VOID)ArchAtomicAdd(v, 1);
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}
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STATIC INLINE VOID ArchAtomicDec(Atomic *v)
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{
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(VOID)ArchAtomicSub(v, 1);
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}
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STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
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{
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return ArchAtomicAdd(v, 1);
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}
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STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
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{
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return ArchAtomicSub(v, 1);
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}
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/**
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* @ingroup los_arch_atomic
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* @brief Atomic exchange for 32-bit variable.
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*
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* @par Description:
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* This API is used to implement the atomic exchange for 32-bit variable
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* and return the previous value of the atomic variable.
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* @attention
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* <ul>The pointer v must not be NULL.</ul>
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*
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* @param v [IN] The variable pointer.
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* @param val [IN] The exchange value.
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*
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* @retval #INT32 The previous value of the atomic variable
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* @par Dependency:
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* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
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* @see
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*/
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STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
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{
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INT32 prevVal = 0;
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UINT32 status = 0;
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do {
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__asm__ __volatile__("ldrex %0, [%3]\n"
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"strex %1, %4, [%3]"
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: "=&r"(prevVal), "=&r"(status), "+m"(*v)
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: "r"(v), "r"(val)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prevVal;
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}
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/**
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* @ingroup los_arch_atomic
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* @brief Atomic exchange for 32-bit variable with compare.
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*
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* @par Description:
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* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
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* @attention
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* <ul>The pointer v must not be NULL.</ul>
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*
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* @param v [IN] The variable pointer.
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* @param val [IN] The new value.
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* @param oldVal [IN] The old value.
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*
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* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
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* @retval FALSE The previous value of the atomic variable is equal to oldVal.
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* @par Dependency:
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* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
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* @see
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*/
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STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
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{
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INT32 prevVal = 0;
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UINT32 status = 0;
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do {
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__asm__ __volatile__("ldrex %0, %2\n"
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"mov %1, #0\n"
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"cmp %0, %3\n"
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"bne 1f\n"
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"strex %1, %4, %2\n"
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"1:"
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: "=&r"(prevVal), "=&r"(status), "+Q"(*v)
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: "r"(oldVal), "r"(val)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prevVal != oldVal;
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}
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STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
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{
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INT64 val;
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UINT32 intSave;
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intSave = LOS_IntLock();
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val = *v;
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LOS_IntRestore(intSave);
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return val;
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}
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STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
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{
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UINT32 intSave;
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intSave = LOS_IntLock();
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*v = setVal;
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LOS_IntRestore(intSave);
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}
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STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
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{
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INT64 val;
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UINT32 intSave;
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intSave = LOS_IntLock();
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*v += addVal;
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val = *v;
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LOS_IntRestore(intSave);
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return val;
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}
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STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
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{
|
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INT64 val;
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UINT32 intSave;
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intSave = LOS_IntLock();
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*v -= subVal;
|
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val = *v;
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LOS_IntRestore(intSave);
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|
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return val;
|
||||
}
|
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|
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STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
|
||||
{
|
||||
(VOID)ArchAtomic64Add(v, 1);
|
||||
}
|
||||
|
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STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
|
||||
{
|
||||
return ArchAtomic64Add(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
|
||||
{
|
||||
(VOID)ArchAtomic64Sub(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
|
||||
{
|
||||
return ArchAtomic64Sub(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
|
||||
{
|
||||
INT64 prevVal;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
prevVal = *v;
|
||||
*v = val;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return prevVal;
|
||||
}
|
||||
|
||||
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
|
||||
{
|
||||
INT64 prevVal;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
prevVal = *v;
|
||||
if (prevVal == oldVal) {
|
||||
*v = val;
|
||||
}
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return prevVal != oldVal;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
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#endif /* _LOS_ARCH_ATOMIC_H */
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@ -0,0 +1,133 @@
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/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_ARCH_CONTEXT_H
|
||||
#define _LOS_ARCH_CONTEXT_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_compiler.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef struct TagTskContext {
|
||||
UINT32 secureContext;
|
||||
UINT32 stackLimit;
|
||||
UINT32 excReturn;
|
||||
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined(__FPU_USED) && (__FPU_USED == 1U)))
|
||||
UINT32 S16;
|
||||
UINT32 S17;
|
||||
UINT32 S18;
|
||||
UINT32 S19;
|
||||
UINT32 S20;
|
||||
UINT32 S21;
|
||||
UINT32 S22;
|
||||
UINT32 S23;
|
||||
UINT32 S24;
|
||||
UINT32 S25;
|
||||
UINT32 S26;
|
||||
UINT32 S27;
|
||||
UINT32 S28;
|
||||
UINT32 S29;
|
||||
UINT32 S30;
|
||||
UINT32 S31;
|
||||
#endif
|
||||
UINT32 uwR4;
|
||||
UINT32 uwR5;
|
||||
UINT32 uwR6;
|
||||
UINT32 uwR7;
|
||||
UINT32 uwR8;
|
||||
UINT32 uwR9;
|
||||
UINT32 uwR10;
|
||||
UINT32 uwR11;
|
||||
UINT32 uwPriMask;
|
||||
UINT32 uwR0;
|
||||
UINT32 uwR1;
|
||||
UINT32 uwR2;
|
||||
UINT32 uwR3;
|
||||
UINT32 uwR12;
|
||||
UINT32 uwLR;
|
||||
UINT32 uwPC;
|
||||
UINT32 uwxPSR;
|
||||
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined(__FPU_USED) && (__FPU_USED == 1U)))
|
||||
UINT32 S0;
|
||||
UINT32 S1;
|
||||
UINT32 S2;
|
||||
UINT32 S3;
|
||||
UINT32 S4;
|
||||
UINT32 S5;
|
||||
UINT32 S6;
|
||||
UINT32 S7;
|
||||
UINT32 S8;
|
||||
UINT32 S9;
|
||||
UINT32 S10;
|
||||
UINT32 S11;
|
||||
UINT32 S12;
|
||||
UINT32 S13;
|
||||
UINT32 S14;
|
||||
UINT32 S15;
|
||||
UINT32 FPSCR;
|
||||
UINT32 NO_NAME;
|
||||
#endif
|
||||
} TaskContext;
|
||||
|
||||
/**
|
||||
* @ingroup los_config
|
||||
* @brief: Task start running function.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to start a task.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param: None.
|
||||
*
|
||||
* @retval None.
|
||||
*
|
||||
* @par Dependency:
|
||||
* <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalStartToRun(VOID);
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_ARCH_CONTEXT_H */
|
|
@ -0,0 +1,683 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_ARCH_INTERRUPT_H
|
||||
#define _LOS_ARCH_INTERRUPT_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_compiler.h"
|
||||
#include "los_interrupt.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Maximum number of used hardware interrupts.
|
||||
*/
|
||||
#ifndef OS_HWI_MAX_NUM
|
||||
#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
|
||||
#endif
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Highest priority of a hardware interrupt.
|
||||
*/
|
||||
#ifndef OS_HWI_PRIO_HIGHEST
|
||||
#define OS_HWI_PRIO_HIGHEST 0
|
||||
#endif
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Lowest priority of a hardware interrupt.
|
||||
*/
|
||||
#ifndef OS_HWI_PRIO_LOWEST
|
||||
#define OS_HWI_PRIO_LOWEST 7
|
||||
#endif
|
||||
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Define the type of a hardware interrupt vector table function.
|
||||
*/
|
||||
typedef VOID (**HWI_VECTOR_FUNC)(void);
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Count of interrupts.
|
||||
*/
|
||||
extern UINT32 g_intCount;
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Count of M-Core system interrupt vector.
|
||||
*/
|
||||
#define OS_SYS_VECTOR_CNT 16
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Count of M-Core interrupt vector.
|
||||
*/
|
||||
#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* AIRCR register priority group parameter .
|
||||
*/
|
||||
#define OS_NVIC_AIRCR_PRIGROUP 7
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Boot interrupt vector table.
|
||||
*/
|
||||
extern UINT32 _BootVectors[];
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Hardware interrupt error code: Invalid interrupt number.
|
||||
*
|
||||
* Value: 0x02000900
|
||||
*
|
||||
* Solution: Ensure that the interrupt number is valid.
|
||||
* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
|
||||
*/
|
||||
#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Hardware interrupt error code: Null hardware interrupt handling function.
|
||||
*
|
||||
* Value: 0x02000901
|
||||
*
|
||||
* Solution: Pass in a valid non-null hardware interrupt handling function.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
|
||||
*
|
||||
* Value: 0x02000902
|
||||
*
|
||||
* Solution: Increase the configured maximum number of supported hardware interrupts.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
|
||||
*
|
||||
* Value: 0x02000903
|
||||
*
|
||||
* Solution: Expand the configured memory.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Hardware interrupt error code: The interrupt has already been created.
|
||||
*
|
||||
* Value: 0x02000904
|
||||
*
|
||||
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Hardware interrupt error code: Invalid interrupt priority.
|
||||
*
|
||||
* Value: 0x02000905
|
||||
*
|
||||
* Solution: Ensure that the interrupt priority is valid.
|
||||
* The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
|
||||
*/
|
||||
#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Hardware interrupt error code: Incorrect interrupt creation mode.
|
||||
*
|
||||
* Value: 0x02000906
|
||||
*
|
||||
* Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
|
||||
* OS_HWI_MODE_FAST of which the value can be 0 or 1.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
|
||||
*
|
||||
* Value: 0x02000907
|
||||
*
|
||||
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* SysTick control and status register.
|
||||
*/
|
||||
#define OS_SYSTICK_CONTROL_REG 0xE000E010
|
||||
|
||||
/* *
|
||||
* @ingroup los_hw
|
||||
* SysTick current value register.
|
||||
*/
|
||||
#define OS_SYSTICK_CURRENT_REG 0xE000E018
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt Priority-Level Registers.
|
||||
*/
|
||||
#define OS_NVIC_PRI_BASE 0xE000E400
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt enable register for 0-31.
|
||||
*/
|
||||
#define OS_NVIC_SETENA_BASE 0xE000E100
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* interrupt pending register.
|
||||
*/
|
||||
#define OS_NVIC_SETPEND_BASE 0xE000E200
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt active register.
|
||||
*/
|
||||
#define OS_NVIC_INT_ACT_BASE 0xE000E300
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt disable register for 0-31.
|
||||
*/
|
||||
#define OS_NVIC_CLRENA_BASE 0xE000E180
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt control and status register.
|
||||
*/
|
||||
#define OS_NVIC_INT_CTRL 0xE000ED04
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Vector table offset register.
|
||||
*/
|
||||
#define OS_NVIC_VTOR 0xE000ED08
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Application interrupt and reset control register
|
||||
*/
|
||||
#define OS_NVIC_AIRCR 0xE000ED0C
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* System exception priority register.
|
||||
*/
|
||||
#define OS_NVIC_EXCPRI_BASE 0xE000ED18
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 1 :reset.
|
||||
*/
|
||||
#define OS_EXC_RESET 1
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 2 :Non-Maskable Interrupt.
|
||||
*/
|
||||
#define OS_EXC_NMI 2
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 3 :(hard)fault.
|
||||
*/
|
||||
#define OS_EXC_HARD_FAULT 3
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 4 :MemManage fault.
|
||||
*/
|
||||
#define OS_EXC_MPU_FAULT 4
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 5 :Bus fault.
|
||||
*/
|
||||
#define OS_EXC_BUS_FAULT 5
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 6 :Usage fault.
|
||||
*/
|
||||
#define OS_EXC_USAGE_FAULT 6
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 11 :SVCall.
|
||||
*/
|
||||
#define OS_EXC_SVC_CALL 11
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 12 :Debug monitor.
|
||||
*/
|
||||
#define OS_EXC_DBG_MONITOR 12
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 14 :PendSV.
|
||||
*/
|
||||
#define OS_EXC_PEND_SV 14
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Interrupt No. 15 :SysTick.
|
||||
*/
|
||||
#define OS_EXC_SYS_TICK 15
|
||||
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
|
||||
#else
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
|
||||
#endif
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* @brief: Hardware interrupt entry function.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used as all hardware interrupt handling function entry.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalInterrupt(VOID);
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* @brief: Default vector handling function.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to configure interrupt for null function.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalHwiDefaultHandler(VOID);
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* @brief: Reset the vector table.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to reset the vector table.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID Reset_Handler(VOID);
|
||||
|
||||
/* *
|
||||
* @ingroup los_arch_interrupt
|
||||
* @brief: Pended System Call.
|
||||
*
|
||||
* @par Description:
|
||||
* PendSV can be pended and is useful for an OS to pend an exception
|
||||
* so that an action can be performed after other important tasks are completed.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalPendSV(VOID);
|
||||
|
||||
|
||||
#define OS_EXC_IN_INIT 0
|
||||
#define OS_EXC_IN_TASK 1
|
||||
#define OS_EXC_IN_HWI 2
|
||||
|
||||
#define OS_EXC_MAX_BUF_LEN 25
|
||||
#define OS_EXC_MAX_NEST_DEPTH 1
|
||||
|
||||
#define OS_NVIC_SHCSR 0xE000ED24
|
||||
#define OS_NVIC_CCR 0xE000ED14
|
||||
|
||||
#define OS_NVIC_INT_ENABLE_SIZE 0x20
|
||||
#define OS_NVIC_INT_PRI_SIZE 0xF0
|
||||
#define OS_NVIC_EXCPRI_SIZE 0xC
|
||||
#define OS_NVIC_INT_CTRL_SIZE 4
|
||||
#define OS_NVIC_SHCSR_SIZE 4
|
||||
|
||||
#define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE
|
||||
#define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE
|
||||
|
||||
#define OS_EXC_FLAG_NO_FLOAT 0x10000000
|
||||
#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
|
||||
#define OS_EXC_FLAG_IN_HWI 0x02
|
||||
|
||||
#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
|
||||
|
||||
#define OS_EXC_EVENT 0x00000001
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* the struct of register files
|
||||
*
|
||||
* description: the register files that saved when exception triggered
|
||||
*
|
||||
* notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
|
||||
*/
|
||||
typedef struct TagExcContext {
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
UINT32 S16;
|
||||
UINT32 S17;
|
||||
UINT32 S18;
|
||||
UINT32 S19;
|
||||
UINT32 S20;
|
||||
UINT32 S21;
|
||||
UINT32 S22;
|
||||
UINT32 S23;
|
||||
UINT32 S24;
|
||||
UINT32 S25;
|
||||
UINT32 S26;
|
||||
UINT32 S27;
|
||||
UINT32 S28;
|
||||
UINT32 S29;
|
||||
UINT32 S30;
|
||||
UINT32 S31;
|
||||
#endif
|
||||
UINT32 uwR4;
|
||||
UINT32 uwR5;
|
||||
UINT32 uwR6;
|
||||
UINT32 uwR7;
|
||||
UINT32 uwR8;
|
||||
UINT32 uwR9;
|
||||
UINT32 uwR10;
|
||||
UINT32 uwR11;
|
||||
UINT32 uwPriMask;
|
||||
/* auto save */
|
||||
UINT32 uwSP;
|
||||
UINT32 uwR0;
|
||||
UINT32 uwR1;
|
||||
UINT32 uwR2;
|
||||
UINT32 uwR3;
|
||||
UINT32 uwR12;
|
||||
UINT32 uwLR;
|
||||
UINT32 uwPC;
|
||||
UINT32 uwxPSR;
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED) && (__FPU_USED== 1U)))
|
||||
UINT32 S0;
|
||||
UINT32 S1;
|
||||
UINT32 S2;
|
||||
UINT32 S3;
|
||||
UINT32 S4;
|
||||
UINT32 S5;
|
||||
UINT32 S6;
|
||||
UINT32 S7;
|
||||
UINT32 S8;
|
||||
UINT32 S9;
|
||||
UINT32 S10;
|
||||
UINT32 S11;
|
||||
UINT32 S12;
|
||||
UINT32 S13;
|
||||
UINT32 S14;
|
||||
UINT32 S15;
|
||||
UINT32 FPSCR;
|
||||
UINT32 NO_NAME;
|
||||
#endif
|
||||
} EXC_CONTEXT_S;
|
||||
|
||||
typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
|
||||
VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
|
||||
|
||||
VOID HalExcNMI(VOID);
|
||||
VOID HalExcHardFault(VOID);
|
||||
VOID HalExcMemFault(VOID);
|
||||
VOID HalExcBusFault(VOID);
|
||||
VOID HalExcUsageFault(VOID);
|
||||
VOID HalSVCHandler(VOID);
|
||||
VOID HalHwiInit(VOID);
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the bus status register was being pushed.
|
||||
*/
|
||||
#define OS_EXC_BF_STKERR 1
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the bus status register was out of the stack.
|
||||
*/
|
||||
#define OS_EXC_BF_UNSTKERR 2
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Bus status register imprecise data access violation.
|
||||
*/
|
||||
#define OS_EXC_BF_IMPRECISERR 3
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Bus status register exact data access violation.
|
||||
*/
|
||||
#define OS_EXC_BF_PRECISERR 4
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Bus status register access violation while pointing.
|
||||
*/
|
||||
#define OS_EXC_BF_IBUSERR 5
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the memory management status register was being pushed.
|
||||
*/
|
||||
#define OS_EXC_MF_MSTKERR 6
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
|
||||
*/
|
||||
#define OS_EXC_MF_MUNSTKERR 7
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Memory management status register data access violation.
|
||||
*/
|
||||
#define OS_EXC_MF_DACCVIOL 8
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Memory management status register access violation.
|
||||
*/
|
||||
#define OS_EXC_MF_IACCVIOL 9
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
|
||||
*/
|
||||
#define OS_EXC_UF_DIVBYZERO 10
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Usage error, error caused by unaligned access.
|
||||
*/
|
||||
#define OS_EXC_UF_UNALIGNED 11
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
|
||||
*/
|
||||
#define OS_EXC_UF_NOCP 12
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
|
||||
*/
|
||||
#define OS_EXC_UF_INVPC 13
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
|
||||
*/
|
||||
#define OS_EXC_UF_INVSTATE 14
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
|
||||
*/
|
||||
#define OS_EXC_UF_UNDEFINSTR 15
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: NMI
|
||||
*/
|
||||
|
||||
#define OS_EXC_CAUSE_NMI 16
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: hard fault
|
||||
*/
|
||||
#define OS_EXC_CAUSE_HARDFAULT 17
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: The task handler exits.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_TASK_EXIT 18
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: A fatal error.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_FATAL_ERR 19
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Hard Fault caused by a debug event.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_DEBUGEVT 20
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_VECTBL 21
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Exception information structure
|
||||
*
|
||||
* Description: Exception information saved when an exception is triggered on the Cortex-M33 platform.
|
||||
*
|
||||
*/
|
||||
typedef struct TagExcInfo {
|
||||
/**< Exception occurrence phase: 0 means that an exception occurs in initialization,
|
||||
* 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
|
||||
UINT16 phase;
|
||||
/**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
|
||||
UINT16 type;
|
||||
/**< If the exact address access error indicates the wrong access address when the exception occurred */
|
||||
UINT32 faultAddr;
|
||||
/**< An exception occurs in an interrupt, indicating the interrupt number.
|
||||
* An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
|
||||
UINT32 thrdPid;
|
||||
/**< Number of nested exceptions. Currently only registered hook functions are supported
|
||||
* when an exception is entered for the first time */
|
||||
UINT16 nestCnt;
|
||||
/**< reserve */
|
||||
UINT16 reserved;
|
||||
/**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
|
||||
EXC_CONTEXT_S *context;
|
||||
} ExcInfo;
|
||||
|
||||
extern UINT32 g_curNestCount;
|
||||
extern UINT32 g_intCount;
|
||||
extern UINT8 g_uwExcTbl[32];
|
||||
extern ExcInfo g_excInfo;
|
||||
|
||||
#define MAX_INT_INFO_SIZE (8 + 0x164)
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_ARCH_INTERRUPT_H */
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_ARCH_TIMER_H
|
||||
#define _LOS_ARCH_TIMER_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_compiler.h"
|
||||
#include "los_timer.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_ARCH_TIMER_H */
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_context.h"
|
||||
#include "securec.h"
|
||||
#include "los_arch_context.h"
|
||||
#include "los_arch_interrupt.h"
|
||||
#include "los_task.h"
|
||||
#include "los_sched.h"
|
||||
#include "los_interrupt.h"
|
||||
#include "los_debug.h"
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchInit
|
||||
Description : arch init function
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
|
||||
{
|
||||
HalHwiInit();
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchSysExit
|
||||
Description : Task exit function
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
|
||||
{
|
||||
LOS_IntLock();
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchTskStackInit
|
||||
Description : Task stack initialization function
|
||||
Input : taskID --- TaskID
|
||||
stackSize --- Total size of the stack
|
||||
topStack --- Top of task's stack
|
||||
Output : None
|
||||
Return : Context pointer
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
|
||||
{
|
||||
TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
|
||||
|
||||
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined(__FPU_USED) && (__FPU_USED == 1U)))
|
||||
context->S16 = 0xAA000010;
|
||||
context->S17 = 0xAA000011;
|
||||
context->S18 = 0xAA000012;
|
||||
context->S19 = 0xAA000013;
|
||||
context->S20 = 0xAA000014;
|
||||
context->S21 = 0xAA000015;
|
||||
context->S22 = 0xAA000016;
|
||||
context->S23 = 0xAA000017;
|
||||
context->S24 = 0xAA000018;
|
||||
context->S25 = 0xAA000019;
|
||||
context->S26 = 0xAA00001A;
|
||||
context->S27 = 0xAA00001B;
|
||||
context->S28 = 0xAA00001C;
|
||||
context->S29 = 0xAA00001D;
|
||||
context->S30 = 0xAA00001E;
|
||||
context->S31 = 0xAA00001F;
|
||||
context->S0 = 0xAA000000;
|
||||
context->S1 = 0xAA000001;
|
||||
context->S2 = 0xAA000002;
|
||||
context->S3 = 0xAA000003;
|
||||
context->S4 = 0xAA000004;
|
||||
context->S5 = 0xAA000005;
|
||||
context->S6 = 0xAA000006;
|
||||
context->S7 = 0xAA000007;
|
||||
context->S8 = 0xAA000008;
|
||||
context->S9 = 0xAA000009;
|
||||
context->S10 = 0xAA00000A;
|
||||
context->S11 = 0xAA00000B;
|
||||
context->S12 = 0xAA00000C;
|
||||
context->S13 = 0xAA00000D;
|
||||
context->S14 = 0xAA00000E;
|
||||
context->S15 = 0xAA00000F;
|
||||
context->FPSCR = 0x00000000;
|
||||
context->NO_NAME = 0xAA000011;
|
||||
#endif
|
||||
|
||||
context->secureContext = 0UL;
|
||||
context->stackLimit = (UINT32)topStack;
|
||||
context->excReturn = 0xFFFFFFBC;
|
||||
|
||||
context->uwR4 = 0x04040404L;
|
||||
context->uwR5 = 0x05050505L;
|
||||
context->uwR6 = 0x06060606L;
|
||||
context->uwR7 = 0x07070707L;
|
||||
context->uwR8 = 0x08080808L;
|
||||
context->uwR9 = 0x09090909L;
|
||||
context->uwR10 = 0x10101010L;
|
||||
context->uwR11 = 0x11111111L;
|
||||
context->uwPriMask = 0;
|
||||
context->uwR0 = taskID;
|
||||
context->uwR1 = 0x01010101L;
|
||||
context->uwR2 = 0x02020202L;
|
||||
context->uwR3 = 0x03030303L;
|
||||
context->uwR12 = 0x12121212L;
|
||||
context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
|
||||
context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
|
||||
context->uwxPSR = 0x01000000L;
|
||||
|
||||
return (VOID *)context;
|
||||
}
|
||||
|
||||
VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
|
||||
{
|
||||
TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
|
||||
(VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
|
||||
|
||||
context->uwR0 = param;
|
||||
context->uwPC = sigHandler;
|
||||
context->stackLimit = (UINT32)stackTop;
|
||||
context->excReturn = 0xFFFFFFBC;
|
||||
context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
|
||||
|
||||
return (VOID *)context;
|
||||
}
|
||||
|
||||
LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
|
||||
{
|
||||
(VOID)LOS_IntLock();
|
||||
OsSchedStart();
|
||||
HalStartToRun();
|
||||
return LOS_OK; /* never return */
|
||||
}
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv8.1-m.main
|
||||
.fpu vfpv3-d16-fp16
|
||||
.thumb
|
||||
|
||||
.equ OS_FPU_CPACR, 0xE000ED88
|
||||
.equ OS_FPU_CPACR_ENABLE, 0x00F00000
|
||||
.equ OS_NVIC_INT_CTRL, 0xE000ED04
|
||||
.equ OS_NVIC_SYSPRI2, 0xE000ED20
|
||||
.equ OS_NVIC_PENDSV_PRI, 0xF0F00000
|
||||
.equ OS_NVIC_PENDSVSET, 0x10000000
|
||||
.equ OS_TASK_STATUS_RUNNING, 0x0010
|
||||
|
||||
.section .text
|
||||
.thumb
|
||||
|
||||
.macro SIGNAL_CONTEXT_RESTORE
|
||||
PUSH {R12, LR}
|
||||
BLX OsSignalTaskContextRestore
|
||||
POP {R12, LR}
|
||||
CMP R0, #0
|
||||
MOV R1, R0
|
||||
BNE SignalContextRestore
|
||||
.endm
|
||||
|
||||
.type HalStartFirstTask, %function
|
||||
.global HalStartFirstTask
|
||||
HalStartFirstTask:
|
||||
MOV R0, #2
|
||||
MSR CONTROL, R0
|
||||
|
||||
LDR R1, =g_losTask
|
||||
LDR R0, [R1, #4]
|
||||
|
||||
LDR R12, [R0] /* Get the stack pointer of the current task. */
|
||||
LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 = excReturn.*/
|
||||
LDR R4, =g_secureContext
|
||||
STR R1, [R4] /* Set the secureContext to g_secureContext handler. */
|
||||
MSR PSPLIM, R2 /* Set the stackLmit for the PSPLIM about current task. */
|
||||
ISB
|
||||
|
||||
LDR.W R1, =OS_FPU_CPACR
|
||||
LDR R1, [R1]
|
||||
AND R1, R1, #OS_FPU_CPACR_ENABLE
|
||||
CMP R1, #OS_FPU_CPACR_ENABLE
|
||||
BNE __DisabledFPU1
|
||||
ADD R12, R12, #64
|
||||
VPUSH {S0}
|
||||
VPOP {S0}
|
||||
|
||||
__DisabledFPU1:
|
||||
ADD R12, R12, #36
|
||||
MSR PSP, R12
|
||||
CPSIE I
|
||||
BX R3
|
||||
|
||||
.type ArchIntLock, %function
|
||||
.global ArchIntLock
|
||||
ArchIntLock:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
|
||||
MRS R0, PRIMASK
|
||||
CPSID I
|
||||
BX LR
|
||||
.fnend
|
||||
|
||||
.type ArchIntUnLock, %function
|
||||
.global ArchIntUnLock
|
||||
ArchIntUnLock:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
|
||||
MRS R0, PRIMASK
|
||||
CPSIE I
|
||||
BX LR
|
||||
.fnend
|
||||
|
||||
.type ArchIntRestore, %function
|
||||
.global ArchIntRestore
|
||||
ArchIntRestore:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
|
||||
MSR PRIMASK, R0
|
||||
BX LR
|
||||
.fnend
|
||||
|
||||
.type ArchTaskSchedule, %function
|
||||
.global ArchTaskSchedule
|
||||
ArchTaskSchedule:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
|
||||
ldr r0, =OS_NVIC_INT_CTRL
|
||||
ldr r1, =OS_NVIC_PENDSVSET
|
||||
str r1, [r0]
|
||||
dsb
|
||||
isb
|
||||
bx lr
|
||||
.fnend
|
||||
|
||||
.type HalPendSV, %function
|
||||
.global HalPendSV
|
||||
HalPendSV:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
|
||||
mrs r12, PRIMASK
|
||||
cpsid I
|
||||
|
||||
HalTaskSwitch:
|
||||
SIGNAL_CONTEXT_RESTORE
|
||||
|
||||
push {r12, lr}
|
||||
blx OsSchedTaskSwitch
|
||||
pop {r12, lr}
|
||||
cmp r0, #0
|
||||
mov r0, lr
|
||||
bne TaskContextSwitch
|
||||
msr PRIMASK, r12
|
||||
bx lr
|
||||
|
||||
TaskContextSwitch:
|
||||
mov lr, r0
|
||||
mrs r0, psp
|
||||
|
||||
LDR R2, =g_secureContext
|
||||
LDR R1, [R2]
|
||||
CBZ R1, __SaveNSContext /* If the g_secureContext is NULL, so no secure context to save. */
|
||||
|
||||
PUSH {R0-R1, R12, R14} /* Store registers, include LR, PRIMASK. */
|
||||
BL HalSecureContextSave /* Store the secure context to g_secureContext->curStackPointer. */
|
||||
POP {R0-R3}
|
||||
MOV LR, R3
|
||||
MOV R12, R2 /* R2 = PRIMASK. */
|
||||
|
||||
__SaveNSContext:
|
||||
STMFD R0!, {R4-R12}
|
||||
LDR.W R3, =OS_FPU_CPACR
|
||||
LDR R3, [R3]
|
||||
AND R3, R3, #OS_FPU_CPACR_ENABLE
|
||||
CMP R3, #OS_FPU_CPACR_ENABLE
|
||||
BNE __DisabledFPU2
|
||||
VSTMDB R0!, {D8-D15}
|
||||
|
||||
__DisabledFPU2:
|
||||
LDR R5, =g_losTask
|
||||
LDR R6, [R5] /* Get the stackPointer handler of the current task. */
|
||||
SUBS R0, R0, #12
|
||||
STR R0, [R6] /* Save the new top of stack in TCB. */
|
||||
MRS R2, PSPLIM
|
||||
MOV R3, LR
|
||||
STMIA R0!, {R1, R2-R3} /* Store g_secureContext, PSPLIM and LR on the stack of current task. */
|
||||
|
||||
LDR R0, [R5, #4]
|
||||
STR R0, [R5]
|
||||
LDR R1, [R0]
|
||||
|
||||
SignalContextRestore:
|
||||
LDMIA R1!, {R0, R2-R3} /* Restore secureContext, PSPLIM and LR from the current task stack. */
|
||||
MSR PSPLIM, R2
|
||||
MOV LR, R3
|
||||
LDR R2, =g_secureContext
|
||||
STR R0, [R2] /* Set the secureContext of the new task to g_secureContext. */
|
||||
CBZ R0, __RestoreNSContext /* If there is no secure context for the new task, so restore from the non-secure context. */
|
||||
PUSH {R1, R3}
|
||||
BL HalSecureContextLoad /* Restore the secure context. */
|
||||
POP {R1, R3}
|
||||
MOV LR, R3
|
||||
|
||||
__RestoreNSContext:
|
||||
LDR.W R3, =OS_FPU_CPACR
|
||||
LDR R3, [R3]
|
||||
AND R3, R3, #OS_FPU_CPACR_ENABLE
|
||||
CMP R3, #OS_FPU_CPACR_ENABLE
|
||||
BNE __DisabledFPU3
|
||||
VLDMIA R1!, {D8-D15}
|
||||
|
||||
__DisabledFPU3:
|
||||
LDMFD R1!, {R4-R12}
|
||||
MSR PSP, R1
|
||||
|
||||
MSR PRIMASK, R12
|
||||
BX LR
|
||||
.fnend
|
||||
|
||||
.type HalSVCStartSchedule, %function
|
||||
.global HalSVCStartSchedule
|
||||
HalSVCStartSchedule:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
LDR R4, =OS_NVIC_SYSPRI2
|
||||
LDR R5, =OS_NVIC_PENDSV_PRI
|
||||
STR R5, [R4]
|
||||
CPSIE I
|
||||
DSB
|
||||
ISB
|
||||
SVC 2
|
||||
.fnend
|
||||
|
||||
.type HalSVCSecureContextAlloc, %function
|
||||
.global HalSVCSecureContextAlloc
|
||||
HalSVCSecureContextAlloc:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
SVC 0
|
||||
BX LR
|
||||
.fnend
|
||||
|
||||
.type HalSVCSecureContextFree, %function
|
||||
.global HalSVCSecureContextFree
|
||||
HalSVCSecureContextFree:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
SVC 1
|
||||
BX LR
|
||||
.fnend
|
||||
|
||||
.type HalSVCHandler, %function
|
||||
.global HalSVCHandler
|
||||
HalSVCHandler:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
TST LR, #0x04
|
||||
ITE EQ
|
||||
MRSEQ R1, MSP
|
||||
MRSNE R1, PSP
|
||||
LDR R0, [R1, #24]
|
||||
LDRB R0, [R0, #-2] /* Get the SVC number. */
|
||||
|
||||
PUSH {LR}
|
||||
MOV R2, R1 /* Get the stack for R2. */
|
||||
LDMFD R2!, {R1} /* Get the input arg for HalSecureSVCHandler. */
|
||||
STMFD R2!, {R1}
|
||||
BL HalSecureSVCHandler
|
||||
POP {LR}
|
||||
BX LR
|
||||
.fnend
|
|
@ -0,0 +1,368 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv8.1-m.main
|
||||
.fpu vfpv3-d16-fp16
|
||||
.thumb
|
||||
.section .text
|
||||
|
||||
|
||||
.global HalExcNMI
|
||||
.global HalExcHardFault
|
||||
.global HalExcMemFault
|
||||
.global HalExcBusFault
|
||||
.global HalExcUsageFault
|
||||
|
||||
.extern HalExcHandleEntry
|
||||
.extern g_uwExcTbl
|
||||
.extern g_taskScheduled
|
||||
|
||||
.equ OS_FLG_BGD_ACTIVE, 0x0002
|
||||
|
||||
.equ OS_EXC_CAUSE_NMI, 16
|
||||
.equ OS_EXC_CAUSE_HARDFAULT, 17
|
||||
|
||||
.equ HF_DEBUGEVT, 20
|
||||
.equ HF_VECTBL, 21
|
||||
|
||||
.equ FLAG_ADDR_VALID, 0x10000
|
||||
.equ FLAG_HWI_ACTIVE, 0x20000
|
||||
.equ FLAG_NO_FLOAT, 0x10000000
|
||||
|
||||
.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Register
|
||||
.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Register
|
||||
.equ OS_NVIC_BFAR , 0xE000ED38
|
||||
.equ OS_NVIC_MMAR , 0xE000ED34
|
||||
.equ OS_NVIC_ACT_BASE , 0xE000E300
|
||||
.equ OS_NVIC_SHCSRS , 0xE000ED24
|
||||
.equ OS_NVIC_SHCSR_MASK , 0xC00
|
||||
|
||||
.type HalExcNMI, %function
|
||||
.global HalExcNMI
|
||||
HalExcNMI:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
MOV R0, #OS_EXC_CAUSE_NMI
|
||||
MOV R1, #0
|
||||
B osExcDispatch
|
||||
.fnend
|
||||
|
||||
.type HalExcHardFault, %function
|
||||
.global HalExcHardFault
|
||||
HalExcHardFault:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
MOV R0, #OS_EXC_CAUSE_HARDFAULT
|
||||
LDR R2, =OS_NVIC_HFSR
|
||||
LDR R2, [R2]
|
||||
|
||||
MOV R1, #HF_DEBUGEVT
|
||||
ORR R0, R0, R1, LSL #0x8
|
||||
TST R2, #0x80000000
|
||||
BNE osExcDispatch // DEBUGEVT
|
||||
|
||||
AND R0, R0 , #0x000000FF
|
||||
MOV R1, #HF_VECTBL
|
||||
ORR R0, R0, R1, LSL #0x8
|
||||
TST R2, #0x00000002
|
||||
BNE osExcDispatch // VECTBL
|
||||
|
||||
//if not DEBUGEVT and VECTBL then is FORCED
|
||||
AND R0, R0, #0x000000FF
|
||||
|
||||
LDR R2, =OS_NVIC_FSR
|
||||
LDR R2, [R2]
|
||||
|
||||
TST R2, #0x8000 // BFARVALID
|
||||
BNE _HFBusFault // BusFault
|
||||
|
||||
TST R2, #0x80 // MMARVALID
|
||||
BNE _HFMemFault // MemFault
|
||||
|
||||
MOV R12,#0
|
||||
B osHFExcCommonBMU
|
||||
.fnend
|
||||
|
||||
.type _HFBusFault, %function
|
||||
|
||||
_HFBusFault:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
LDR R1, =OS_NVIC_BFAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
B osHFExcCommonBMU
|
||||
.fnend
|
||||
|
||||
.type _HFMemFault, %function
|
||||
|
||||
_HFMemFault:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
LDR R1, =OS_NVIC_MMAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
.fnend
|
||||
|
||||
.type osHFExcCommonBMU, %function
|
||||
.global osHFExcCommonBMU
|
||||
osHFExcCommonBMU:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
CLZ R2, R2
|
||||
LDR R3, =g_uwExcTbl
|
||||
ADD R3, R3, R2
|
||||
LDRB R2, [R3]
|
||||
ORR R0, R0, R2, LSL #0x8
|
||||
ORR R0, R0 ,R12
|
||||
B osExcDispatch
|
||||
.fnend
|
||||
|
||||
.type HalExcBusFault, %function
|
||||
.global HalExcBusFault
|
||||
HalExcBusFault:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
LDR R0, =OS_NVIC_FSR
|
||||
LDR R0, [R0]
|
||||
|
||||
TST R0, #0x8000 // BFARVALID
|
||||
BEQ _ExcBusNoADDR
|
||||
LDR R1, =OS_NVIC_BFAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
AND R0, R0, #0x1F00
|
||||
|
||||
B osExcCommonBMU
|
||||
.fnend
|
||||
|
||||
.type _ExcBusNoADDR, %function
|
||||
.global _ExcBusNoADDR
|
||||
_ExcBusNoADDR:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
MOV R12,#0
|
||||
B osExcCommonBMU
|
||||
.fnend
|
||||
|
||||
.type HalExcMemFault, %function
|
||||
.global HalExcMemFault
|
||||
HalExcMemFault:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
LDR R0, =OS_NVIC_FSR
|
||||
LDR R0, [R0]
|
||||
|
||||
TST R0, #0x80 // MMARVALID
|
||||
BEQ _ExcMemNoADDR
|
||||
LDR R1, =OS_NVIC_MMAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
AND R0, R0, #0x1B
|
||||
|
||||
B osExcCommonBMU
|
||||
.fnend
|
||||
|
||||
.type _ExcMemNoADDR, %function
|
||||
.global _ExcMemNoADDR
|
||||
_ExcMemNoADDR:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
MOV R12,#0
|
||||
B osExcCommonBMU
|
||||
.fnend
|
||||
|
||||
.type HalExcUsageFault, %function
|
||||
.global HalExcUsageFault
|
||||
HalExcUsageFault:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
LDR R0, =OS_NVIC_FSR
|
||||
LDR R0, [R0]
|
||||
|
||||
MOVW R1, #0x030F
|
||||
LSL R1, R1, #16
|
||||
AND R0, R0, R1
|
||||
MOV R12, #0
|
||||
|
||||
.fnend
|
||||
|
||||
.type osExcCommonBMU, %function
|
||||
.global osExcCommonBMU
|
||||
osExcCommonBMU:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
CLZ R0, R0
|
||||
LDR R3, =g_uwExcTbl
|
||||
ADD R3, R3, R0
|
||||
LDRB R0, [R3]
|
||||
ORR R0, R0, R12
|
||||
.fnend
|
||||
// R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid), R1 -- EXCADDR
|
||||
|
||||
.type osExcDispatch, %function
|
||||
.global osExcDispatch
|
||||
osExcDispatch:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
LDR R2, =OS_NVIC_ACT_BASE
|
||||
MOV R12, #8 // R12 is hwi check loop counter
|
||||
.fnend
|
||||
|
||||
.type _hwiActiveCheck, %function
|
||||
.global _hwiActiveCheck
|
||||
_hwiActiveCheck:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
LDR R3, [R2] // R3 store active hwi register when exc
|
||||
CMP R3, #0
|
||||
BEQ _hwiActiveCheckNext
|
||||
|
||||
// exc occurred in IRQ
|
||||
ORR R0, R0, #FLAG_HWI_ACTIVE
|
||||
RBIT R2, R3
|
||||
CLZ R2, R2
|
||||
AND R12, R12, #1
|
||||
ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as pid
|
||||
.fnend
|
||||
|
||||
.type _ExcInMSP, %function
|
||||
.global _ExcInMSP
|
||||
_ExcInMSP:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
CMP LR, #0xFFFFFFE9
|
||||
BNE _NoFloatInMsp
|
||||
ADD R3, R13, #104
|
||||
PUSH {R3}
|
||||
MRS R12, PRIMASK // store message-->exc: disable int?
|
||||
PUSH {R4-R12} // store message-->exc: {R4-R12}
|
||||
VPUSH {D8-D15}
|
||||
B _handleEntry
|
||||
.fnend
|
||||
|
||||
.type _NoFloatInMsp, %function
|
||||
.global _NoFloatInMsp
|
||||
_NoFloatInMsp:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
ADD R3, R13, #32
|
||||
PUSH {R3} // save IRQ SP // store message-->exc: MSP(R13)
|
||||
|
||||
MRS R12, PRIMASK // store message-->exc: disable int?
|
||||
PUSH {R4-R12} // store message-->exc: {R4-R12}
|
||||
ORR R0, R0, #FLAG_NO_FLOAT
|
||||
B _handleEntry
|
||||
.fnend
|
||||
|
||||
.type _hwiActiveCheckNext, %function
|
||||
.global _hwiActiveCheckNext
|
||||
_hwiActiveCheckNext:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
ADD R2, R2, #4 // next NVIC ACT ADDR
|
||||
SUBS R12, R12, #1
|
||||
BNE _hwiActiveCheck
|
||||
|
||||
/*NMI interrupt excption*/
|
||||
LDR R2, =OS_NVIC_SHCSRS
|
||||
LDRH R2,[R2]
|
||||
LDR R3,=OS_NVIC_SHCSR_MASK
|
||||
AND R2, R2,R3
|
||||
CMP R2,#0
|
||||
BNE _ExcInMSP
|
||||
// exc occurred in Task or Init or exc
|
||||
// reserved for register info from task stack
|
||||
|
||||
LDR R2, =g_taskScheduled
|
||||
LDR R2, [R2]
|
||||
TST R2, #1 // OS_FLG_BGD_ACTIVE
|
||||
BEQ _ExcInMSP // if exc occurred in Init then branch
|
||||
|
||||
|
||||
CMP LR, #0xFFFFFFED //auto push floating registers
|
||||
BNE _NoFloatInPsp
|
||||
|
||||
// exc occurred in Task
|
||||
MOV R2, R13
|
||||
SUB R13, #96 // add 8 Bytes reg(for STMFD)
|
||||
|
||||
MRS R3, PSP
|
||||
ADD R12, R3, #104
|
||||
PUSH {R12} // save task SP
|
||||
|
||||
MRS R12, PRIMASK
|
||||
PUSH {R4-R12}
|
||||
VPUSH {D8-D15}
|
||||
|
||||
// copy auto saved task register
|
||||
|
||||
LDMFD R3!, {R4-R11} // R4-R11 store PSP reg(auto push when exc in task)
|
||||
VLDMIA R3!, {D8-D15}
|
||||
VSTMDB R2!, {D8-D15}
|
||||
STMFD R2!, {R4-R11}
|
||||
B _handleEntry
|
||||
.fnend
|
||||
|
||||
.type _NoFloatInPsp, %function
|
||||
.global _NoFloatInPsp
|
||||
_NoFloatInPsp:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
MOV R2, R13 // no auto push floating registers
|
||||
SUB R13, #32 // add 8 Bytes reg(for STMFD)
|
||||
|
||||
MRS R3, PSP
|
||||
ADD R12, R3, #32
|
||||
PUSH {R12} // save task SP
|
||||
|
||||
MRS R12, PRIMASK
|
||||
PUSH {R4-R12}
|
||||
|
||||
LDMFD R3, {R4-R11} // R4-R11 store PSP reg(auto push when exc in task)
|
||||
STMFD R2!, {R4-R11}
|
||||
ORR R0, R0, #FLAG_NO_FLOAT
|
||||
.fnend
|
||||
|
||||
.type _handleEntry, %function
|
||||
.global _handleEntry
|
||||
_handleEntry:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
MOV R3, R13 // R13:the 4th param
|
||||
CPSID I
|
||||
CPSID F
|
||||
B HalExcHandleEntry
|
||||
|
||||
NOP
|
||||
.fnend
|
||||
|
|
@ -0,0 +1,649 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include "los_interrupt.h"
|
||||
#include <stdarg.h>
|
||||
#include "securec.h"
|
||||
#include "los_context.h"
|
||||
#include "los_arch_interrupt.h"
|
||||
#include "los_debug.h"
|
||||
#include "los_hook.h"
|
||||
#include "los_task.h"
|
||||
#include "los_sched.h"
|
||||
#include "los_memory.h"
|
||||
#include "los_membox.h"
|
||||
#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
|
||||
#include "los_cpup.h"
|
||||
#endif
|
||||
|
||||
#define DEF_HANDLER_START_INDEX 2
|
||||
UINT32 g_intCount = 0;
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt form mapping handling function array.
|
||||
*/
|
||||
STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
|
||||
|
||||
#if (LOSCFG_DEBUG_TOOLS == 1)
|
||||
STATIC UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM] = {0};
|
||||
STATIC CHAR *g_hwiFormName[OS_HWI_MAX_NUM] = {0};
|
||||
|
||||
UINT32 OsGetHwiFormCnt(UINT32 index)
|
||||
{
|
||||
return g_hwiFormCnt[index];
|
||||
}
|
||||
|
||||
CHAR *OsGetHwiFormName(UINT32 index)
|
||||
{
|
||||
return g_hwiFormName[index];
|
||||
}
|
||||
|
||||
BOOL OsGetHwiCreated(UINT32 index)
|
||||
{
|
||||
if (g_hwiForm[index] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
|
||||
typedef struct {
|
||||
HWI_PROC_FUNC pfnHandler;
|
||||
VOID *pParm;
|
||||
} HWI_HANDLER_FUNC;
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt handler form mapping handling function array.
|
||||
*/
|
||||
STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
|
||||
{
|
||||
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
|
||||
g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
|
||||
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
|
||||
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* hardware interrupt handler form mapping handling function array.
|
||||
*/
|
||||
STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
|
||||
{
|
||||
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
|
||||
g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
|
||||
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HwiNumGet
|
||||
Description : Get an interrupt number
|
||||
Input : None
|
||||
Output : None
|
||||
Return : Interrupt Indexes number
|
||||
**************************************************************************** */
|
||||
STATIC UINT32 HwiNumGet(VOID)
|
||||
{
|
||||
return __get_IPSR();
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_EnableIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_DisableIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
if (priority > OS_HWI_PRIO_LOWEST) {
|
||||
return OS_ERRNO_HWI_PRIO_INVALID;
|
||||
}
|
||||
|
||||
NVIC_SetPriority((IRQn_Type)hwiNum, priority);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
HwiControllerOps g_archHwiOps = {
|
||||
.enableIrq = HwiUnmask,
|
||||
.disableIrq = HwiMask,
|
||||
.setIrqPriority = HwiSetPriority,
|
||||
.getCurIrqNum = HwiNumGet,
|
||||
.triggerIrq = HwiPending,
|
||||
.clearIrq = HwiClear,
|
||||
};
|
||||
|
||||
inline UINT32 ArchIsIntActive(VOID)
|
||||
{
|
||||
return (g_intCount > 0);
|
||||
}
|
||||
/* ****************************************************************************
|
||||
Function : HalHwiDefaultHandler
|
||||
Description : default handler of the hardware interrupt
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
/*lint -e529*/
|
||||
LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
|
||||
{
|
||||
PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
WEAK VOID HalPreInterruptHandler(UINT32 arg)
|
||||
{
|
||||
(VOID)arg;
|
||||
return;
|
||||
}
|
||||
|
||||
WEAK VOID HalAftInterruptHandler(UINT32 arg)
|
||||
{
|
||||
(VOID)arg;
|
||||
return;
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HalInterrupt
|
||||
Description : Hardware interrupt entry function
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
|
||||
{
|
||||
UINT32 hwiIndex;
|
||||
UINT32 intSave;
|
||||
|
||||
#if (LOSCFG_KERNEL_RUNSTOP == 1)
|
||||
SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
|
||||
#endif
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
g_intCount++;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
hwiIndex = HwiNumGet();
|
||||
|
||||
OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
|
||||
#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
|
||||
OsCpupIrqStart(hwiIndex);
|
||||
#endif
|
||||
|
||||
HalPreInterruptHandler(hwiIndex);
|
||||
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
|
||||
g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
|
||||
}
|
||||
#else
|
||||
if (g_hwiHandlerForm[hwiIndex] != 0) {
|
||||
g_hwiHandlerForm[hwiIndex]();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (LOSCFG_DEBUG_TOOLS == 1)
|
||||
++g_hwiFormCnt[hwiIndex];
|
||||
#endif
|
||||
|
||||
HalAftInterruptHandler(hwiIndex);
|
||||
|
||||
#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
|
||||
OsCpupIrqEnd(hwiIndex);
|
||||
#endif
|
||||
|
||||
OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
g_intCount--;
|
||||
LOS_IntRestore(intSave);
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchHwiCreate
|
||||
Description : create hardware interrupt
|
||||
Input : hwiNum --- hwi num to create
|
||||
hwiPrio --- priority of the hwi
|
||||
hwiMode --- unused
|
||||
hwiHandler --- hwi handler
|
||||
irqParam --- param of the hwi handler
|
||||
Output : None
|
||||
Return : LOS_OK on success or error code on failure
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
|
||||
HWI_PRIOR_T hwiPrio,
|
||||
HWI_MODE_T hwiMode,
|
||||
HWI_PROC_FUNC hwiHandler,
|
||||
HwiIrqParam *irqParam)
|
||||
{
|
||||
(VOID)hwiMode;
|
||||
UINT32 intSave;
|
||||
|
||||
if (hwiHandler == NULL) {
|
||||
return OS_ERRNO_HWI_PROC_FUNC_NULL;
|
||||
}
|
||||
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
|
||||
return OS_ERRNO_HWI_ALREADY_CREATED;
|
||||
}
|
||||
|
||||
if (hwiPrio > OS_HWI_PRIO_LOWEST) {
|
||||
return OS_ERRNO_HWI_PRIO_INVALID;
|
||||
}
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
if (irqParam != NULL) {
|
||||
OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
|
||||
} else {
|
||||
OsSetVector(hwiNum, hwiHandler, NULL);
|
||||
}
|
||||
#else
|
||||
(VOID)irqParam;
|
||||
OsSetVector(hwiNum, hwiHandler);
|
||||
#endif
|
||||
|
||||
#if (LOSCFG_DEBUG_TOOLS == 1)
|
||||
if ((irqParam != NULL) && (irqParam->pName != NULL)) {
|
||||
g_hwiFormName[hwiNum + OS_SYS_VECTOR_CNT] = (CHAR *)irqParam->pName;
|
||||
}
|
||||
g_hwiFormCnt[hwiNum + OS_SYS_VECTOR_CNT] = 0;
|
||||
#endif
|
||||
|
||||
HwiUnmask((IRQn_Type)hwiNum);
|
||||
HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
|
||||
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchHwiDelete
|
||||
Description : Delete hardware interrupt
|
||||
Input : hwiNum --- hwi num to delete
|
||||
irqParam --- param of the hwi handler
|
||||
Output : None
|
||||
Return : LOS_OK on success or error code on failure
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
|
||||
{
|
||||
(VOID)irqParam;
|
||||
UINT32 intSave;
|
||||
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_DisableIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
|
||||
g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
|
||||
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
#define FAULT_STATUS_REG_BIT 32
|
||||
#define USGFAULT (1 << 18)
|
||||
#define BUSFAULT (1 << 17)
|
||||
#define MEMFAULT (1 << 16)
|
||||
#define DIV0FAULT (1 << 4)
|
||||
#define UNALIGNFAULT (1 << 3)
|
||||
#define HARDFAULT_IRQN (-13)
|
||||
|
||||
ExcInfo g_excInfo = {0};
|
||||
|
||||
UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
|
||||
0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
|
||||
0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
|
||||
0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
|
||||
0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
|
||||
};
|
||||
|
||||
#if (LOSCFG_KERNEL_PRINTF != 0)
|
||||
STATIC VOID OsExcNvicDump(VOID)
|
||||
{
|
||||
#define OS_NR_NVIC_EXC_DUMP_TYPES 7
|
||||
UINT32 *base = NULL;
|
||||
UINT32 len, i, j;
|
||||
UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
|
||||
OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
|
||||
OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
|
||||
};
|
||||
UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
|
||||
OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
|
||||
OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
|
||||
OS_NVIC_INT_CTRL_SIZE
|
||||
};
|
||||
CHAR strRgEnable[] = "enable";
|
||||
CHAR strRgPending[] = "pending";
|
||||
CHAR strRgActive[] = "active";
|
||||
CHAR strRgPriority[] = "priority";
|
||||
CHAR strRgException[] = "exception";
|
||||
CHAR strRgShcsr[] = "shcsr";
|
||||
CHAR strRgIntCtrl[] = "control";
|
||||
CHAR *strRgs[] = {
|
||||
strRgEnable, strRgPending, strRgActive, strRgPriority,
|
||||
strRgException, strRgShcsr, strRgIntCtrl
|
||||
};
|
||||
|
||||
PRINTK("\r\nOS exception NVIC dump:\n");
|
||||
for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
|
||||
base = (UINT32 *)rgNvicBases[i];
|
||||
len = rgNvicLens[i];
|
||||
PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
|
||||
len = (len >> 2); /* 2: Gets the next register offset */
|
||||
for (j = 0; j < len; j++) {
|
||||
PRINTK("0x%x ", *(base + j));
|
||||
if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
|
||||
PRINTK("\n");
|
||||
}
|
||||
}
|
||||
PRINTK("\n");
|
||||
}
|
||||
}
|
||||
|
||||
STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
|
||||
|
||||
PRINTK("Type = %d\n", excInfo->type);
|
||||
PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
|
||||
PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
|
||||
PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
|
||||
}
|
||||
|
||||
STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
PRINTK("Current task info:\n");
|
||||
if (excInfo->phase == OS_EXC_IN_TASK) {
|
||||
LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
|
||||
PRINTK("Task name = %s\n", taskCB->taskName);
|
||||
PRINTK("Task ID = %d\n", taskCB->taskID);
|
||||
PRINTK("Task SP = %p\n", taskCB->stackPointer);
|
||||
PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
|
||||
PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
|
||||
} else if (excInfo->phase == OS_EXC_IN_HWI) {
|
||||
PRINTK("Exception occur in interrupt phase!\n");
|
||||
} else {
|
||||
PRINTK("Exception occur in system init phase!\n");
|
||||
}
|
||||
}
|
||||
|
||||
STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
PRINTK("Exception reg dump:\n");
|
||||
PRINTK("PC = 0x%x\n", excInfo->context->uwPC);
|
||||
PRINTK("LR = 0x%x\n", excInfo->context->uwLR);
|
||||
PRINTK("SP = 0x%x\n", excInfo->context->uwSP);
|
||||
PRINTK("R0 = 0x%x\n", excInfo->context->uwR0);
|
||||
PRINTK("R1 = 0x%x\n", excInfo->context->uwR1);
|
||||
PRINTK("R2 = 0x%x\n", excInfo->context->uwR2);
|
||||
PRINTK("R3 = 0x%x\n", excInfo->context->uwR3);
|
||||
PRINTK("R4 = 0x%x\n", excInfo->context->uwR4);
|
||||
PRINTK("R5 = 0x%x\n", excInfo->context->uwR5);
|
||||
PRINTK("R6 = 0x%x\n", excInfo->context->uwR6);
|
||||
PRINTK("R7 = 0x%x\n", excInfo->context->uwR7);
|
||||
PRINTK("R8 = 0x%x\n", excInfo->context->uwR8);
|
||||
PRINTK("R9 = 0x%x\n", excInfo->context->uwR9);
|
||||
PRINTK("R10 = 0x%x\n", excInfo->context->uwR10);
|
||||
PRINTK("R11 = 0x%x\n", excInfo->context->uwR11);
|
||||
PRINTK("R12 = 0x%x\n", excInfo->context->uwR12);
|
||||
PRINTK("PriMask = 0x%x\n", excInfo->context->uwPriMask);
|
||||
PRINTK("xPSR = 0x%x\n", excInfo->context->uwxPSR);
|
||||
}
|
||||
|
||||
#if (LOSCFG_KERNEL_BACKTRACE == 1)
|
||||
STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
|
||||
UINT32 index;
|
||||
|
||||
OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
|
||||
|
||||
PRINTK("----- backtrace start -----\n");
|
||||
for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
|
||||
if (LR[index] == 0) {
|
||||
break;
|
||||
}
|
||||
PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
|
||||
}
|
||||
PRINTK("----- backtrace end -----\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
STATIC VOID OsExcMemPoolCheckInfo(VOID)
|
||||
{
|
||||
PRINTK("\r\nmemory pools check:\n");
|
||||
#if (LOSCFG_PLATFORM_EXC == 1)
|
||||
MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
|
||||
UINT32 errCnt;
|
||||
UINT32 i;
|
||||
|
||||
(VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
|
||||
|
||||
errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
|
||||
if (errCnt < OS_SYS_MEM_NUM) {
|
||||
errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
|
||||
}
|
||||
|
||||
if (errCnt == 0) {
|
||||
PRINTK("all memory pool check passed!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < errCnt; i++) {
|
||||
PRINTK("pool num = %d\n", i);
|
||||
PRINTK("pool type = %d\n", memExcInfo[i].type);
|
||||
PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
|
||||
PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
|
||||
PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
|
||||
PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
|
||||
PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
|
||||
PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
|
||||
PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
|
||||
}
|
||||
#endif
|
||||
UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
|
||||
if (ret == LOS_OK) {
|
||||
PRINTK("system heap memcheck over, all passed!\n");
|
||||
}
|
||||
|
||||
PRINTK("memory pool check end!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
|
||||
{
|
||||
#if (LOSCFG_KERNEL_PRINTF != 0)
|
||||
PRINTK("*************Exception Information**************\n");
|
||||
OsExcTypeInfo(excInfo);
|
||||
OsExcCurTaskInfo(excInfo);
|
||||
OsExcRegInfo(excInfo);
|
||||
#if (LOSCFG_KERNEL_BACKTRACE == 1)
|
||||
OsExcBackTraceInfo(excInfo);
|
||||
#endif
|
||||
OsGetAllTskInfo();
|
||||
OsExcNvicDump();
|
||||
OsExcMemPoolCheckInfo();
|
||||
#endif
|
||||
}
|
||||
|
||||
LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
|
||||
{
|
||||
UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
|
||||
g_intCount++;
|
||||
g_excInfo.nestCnt++;
|
||||
|
||||
g_excInfo.type = excType & OS_NULL_SHORT;
|
||||
|
||||
if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
|
||||
g_excInfo.faultAddr = faultAddr;
|
||||
} else {
|
||||
g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
|
||||
}
|
||||
if (g_losTask.runTask != NULL) {
|
||||
if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
|
||||
g_excInfo.phase = OS_EXC_IN_HWI;
|
||||
g_excInfo.thrdPid = pid;
|
||||
} else {
|
||||
g_excInfo.phase = OS_EXC_IN_TASK;
|
||||
g_excInfo.thrdPid = g_losTask.runTask->taskID;
|
||||
}
|
||||
} else {
|
||||
g_excInfo.phase = OS_EXC_IN_INIT;
|
||||
g_excInfo.thrdPid = OS_NULL_INT;
|
||||
}
|
||||
if (excType & OS_EXC_FLAG_NO_FLOAT) {
|
||||
g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
|
||||
} else {
|
||||
g_excInfo.context = excBufAddr;
|
||||
}
|
||||
|
||||
OsDoExcHook(EXC_INTERRUPT);
|
||||
OsExcInfoDisplay(&g_excInfo);
|
||||
ArchSysExit();
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HalHwiInit
|
||||
Description : initialization of the hardware interrupt
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
|
||||
{
|
||||
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
|
||||
UINT32 index;
|
||||
g_hwiForm[0] = 0; /* [0] Top of Stack */
|
||||
g_hwiForm[1] = 0; /* [1] reset */
|
||||
for (index = DEF_HANDLER_START_INDEX; index < OS_VECTOR_CNT; index++) {
|
||||
g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
|
||||
}
|
||||
/* Exception handler register */
|
||||
g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcNMI;
|
||||
g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcHardFault;
|
||||
g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault;
|
||||
g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcBusFault;
|
||||
g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcUsageFault;
|
||||
g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalSVCHandler;
|
||||
g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalPendSV;
|
||||
g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)OsTickHandler;
|
||||
|
||||
/* Interrupt vector table location */
|
||||
SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
|
||||
#endif
|
||||
#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
|
||||
NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
|
||||
#endif
|
||||
|
||||
/* Enable USGFAULT, BUSFAULT, MEMFAULT */
|
||||
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
|
||||
|
||||
/* Enable DIV 0 and unaligned exception */
|
||||
#ifdef LOSCFG_ARCH_UNALIGNED_EXC
|
||||
*(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
|
||||
#else
|
||||
*(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
|
||||
#endif
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_timer.h"
|
||||
#include "los_config.h"
|
||||
#include "los_tick.h"
|
||||
#include "los_arch_interrupt.h"
|
||||
|
||||
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
|
||||
STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
|
||||
STATIC UINT64 SysTickCycleGet(UINT32 *period);
|
||||
STATIC VOID SysTickLock(VOID);
|
||||
STATIC VOID SysTickUnlock(VOID);
|
||||
|
||||
STATIC ArchTickTimer g_archTickTimer = {
|
||||
.freq = 0,
|
||||
.irqNum = SysTick_IRQn,
|
||||
.periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
|
||||
.init = SysTickStart,
|
||||
.getCycle = SysTickCycleGet,
|
||||
.reload = SysTickReload,
|
||||
.lock = SysTickLock,
|
||||
.unlock = SysTickUnlock,
|
||||
.tickHandler = NULL,
|
||||
};
|
||||
|
||||
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
|
||||
{
|
||||
UINT32 ret;
|
||||
ArchTickTimer *tick = &g_archTickTimer;
|
||||
|
||||
tick->freq = OS_SYS_CLOCK;
|
||||
|
||||
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
OsSetVector(tick->irqNum, handler, NULL);
|
||||
#else
|
||||
OsSetVector(tick->irqNum, handler);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
ret = SysTick_Config(g_cyclesPerTick);
|
||||
if (ret == 1) {
|
||||
return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
|
||||
}
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
|
||||
{
|
||||
if (nextResponseTime > g_archTickTimer.periodMax) {
|
||||
nextResponseTime = g_archTickTimer.periodMax;
|
||||
}
|
||||
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
NVIC_ClearPendingIRQ(SysTick_IRQn);
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
|
||||
return nextResponseTime;
|
||||
}
|
||||
|
||||
STATIC UINT64 SysTickCycleGet(UINT32 *period)
|
||||
{
|
||||
UINT32 hwCycle = 0;
|
||||
UINT32 intSave = LOS_IntLock();
|
||||
UINT32 val = SysTick->VAL;
|
||||
*period = SysTick->LOAD;
|
||||
if (val != 0) {
|
||||
hwCycle = *period - val;
|
||||
}
|
||||
LOS_IntRestore(intSave);
|
||||
return (UINT64)hwCycle;
|
||||
}
|
||||
|
||||
STATIC VOID SysTickLock(VOID)
|
||||
{
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
STATIC VOID SysTickUnlock(VOID)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
ArchTickTimer *ArchSysTickTimerGet(VOID)
|
||||
{
|
||||
return &g_archTickTimer;
|
||||
}
|
||||
|
||||
UINT32 ArchEnterSleep(VOID)
|
||||
{
|
||||
__DSB();
|
||||
__WFI();
|
||||
__ISB();
|
||||
|
||||
return LOS_OK;
|
||||
}
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_trustzone.h"
|
||||
#include "los_secure_macros.h"
|
||||
#include "los_secure_context.h"
|
||||
#include "los_debug.h"
|
||||
#include "los_arch_context.h"
|
||||
#include "los_interrupt.h"
|
||||
|
||||
OsSecureContext *g_secureContext = NULL;
|
||||
|
||||
VOID HalSecureSVCHandler(UINT32 svcID, UINTPTR arg)
|
||||
{
|
||||
switch (svcID) {
|
||||
case OS_SVC_START_SCHEDULE:
|
||||
HalSecureContextInit();
|
||||
HalStartFirstTask();
|
||||
break;
|
||||
case OS_SVC_ALLOCATE_SECURE_CONTEXT:
|
||||
g_secureContext = HalSecureContextAlloc(arg);
|
||||
LOS_ASSERT(g_secureContext != NULL);
|
||||
HalSecureContextLoad(g_secureContext);
|
||||
break;
|
||||
case OS_SVC_FREE_SECURE_CONTEXT:
|
||||
HalSecureContextFree(g_secureContext);
|
||||
break;
|
||||
default:
|
||||
PRINT_ERR("Incorrect svc id = %u\n", svcID);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
VOID HalStartToRun(VOID)
|
||||
{
|
||||
HalSVCStartSchedule();
|
||||
}
|
||||
|
||||
VOID LOS_SecureContextAlloc(UINT32 secureStackSize)
|
||||
{
|
||||
if (secureStackSize == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
LOS_ASSERT((__get_IPSR() == 0) && (__get_PRIMASK() == 0));
|
||||
secureStackSize = LOS_Align(secureStackSize, sizeof(UINTPTR));
|
||||
HalSVCSecureContextAlloc(secureStackSize);
|
||||
}
|
||||
|
||||
VOID LOS_SecureContextFree(VOID)
|
||||
{
|
||||
HalSVCSecureContextFree();
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_TRUSTZONE_H
|
||||
#define _LOS_TRUSTZONE_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_task.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
extern VOID LOS_SecureContextAlloc(UINT32 secureStackSize);
|
||||
extern VOID LOS_SecureContextFree(VOID);
|
||||
|
||||
extern VOID HalStartFirstTask(VOID);
|
||||
extern VOID HalSVCStartSchedule(VOID);
|
||||
extern VOID HalSVCSecureContextAlloc(UINT32 secureStackSize);
|
||||
extern VOID HalSVCSecureContextFree(VOID);
|
||||
extern VOID HalSVCHandler(VOID);
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_secure_context.h"
|
||||
#include "los_secure_macros.h"
|
||||
#include "los_secure_heap.h"
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureContextInit(VOID)
|
||||
{
|
||||
UINT32 ipsr;
|
||||
|
||||
OS_IPSR_READ(ipsr);
|
||||
if (!ipsr) {
|
||||
return;
|
||||
}
|
||||
|
||||
HalSecureContextInitAsm();
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY OsSecureContext *HalSecureContextAlloc(UINT32 size)
|
||||
{
|
||||
OsSecureContext *secureContext = NULL;
|
||||
UINT32 ipsr;
|
||||
|
||||
OS_IPSR_READ(ipsr);
|
||||
if (!ipsr) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
secureContext = HalSecureMalloc(sizeof(OsSecureContext));
|
||||
if (secureContext == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
secureContext->stackLimit = HalSecureMalloc(size);
|
||||
if (secureContext->stackLimit == NULL) {
|
||||
HalSecureFree(secureContext);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
secureContext->stackStart = secureContext->stackLimit + size;
|
||||
secureContext->curStackPointer = secureContext->stackStart;
|
||||
|
||||
return secureContext;
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureContextFree(OsSecureContext *secureContext)
|
||||
{
|
||||
UINT32 ipsr;
|
||||
|
||||
OS_IPSR_READ(ipsr);
|
||||
if (!ipsr) {
|
||||
return;
|
||||
}
|
||||
|
||||
HalSecureFree(secureContext->stackLimit);
|
||||
secureContext->stackLimit = NULL;
|
||||
HalSecureFree(secureContext);
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureContextLoad(OsSecureContext *secureContext)
|
||||
{
|
||||
HalSecureContextLoadAsm(secureContext);
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureContextSave(OsSecureContext *secureContext)
|
||||
{
|
||||
HalSecureContextSaveAsm(secureContext);
|
||||
}
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_SECURE_CONTEXT_H
|
||||
#define _LOS_SECURE_CONTEXT_H
|
||||
|
||||
#include "los_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef struct {
|
||||
UINT8 *curStackPointer;
|
||||
UINT8 *stackLimit;
|
||||
UINT8 *stackStart;
|
||||
} OsSecureContext;
|
||||
|
||||
extern VOID HalSecureContextInit(VOID);
|
||||
extern OsSecureContext *HalSecureContextAlloc(UINT32 size);
|
||||
extern VOID HalSecureContextFree(OsSecureContext *secureContext);
|
||||
extern VOID HalSecureContextLoad(OsSecureContext *secureContext);
|
||||
extern VOID HalSecureContextSave(OsSecureContext *secureContext);
|
||||
|
||||
extern VOID HalSecureContextInitAsm(VOID);
|
||||
extern VOID HalSecureContextLoadAsm(OsSecureContext *secureContext);
|
||||
extern VOID HalSecureContextSaveAsm(OsSecureContext *secureContext);
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv8.1-m.main
|
||||
.fpu vfpv3-d16-fp16
|
||||
.thumb
|
||||
|
||||
.equ OS_SECURE_SCB_AIRCR, 0xE000ED0C
|
||||
|
||||
.section .text
|
||||
.thumb
|
||||
|
||||
.type HalSecureContextInitAsm, %function
|
||||
.global HalSecureContextInitAsm
|
||||
HalSecureContextInitAsm:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
LDR R0, =OS_SECURE_SCB_AIRCR
|
||||
LDR R1, [R0]
|
||||
|
||||
MOV R2, #0xFFFF
|
||||
LSL R2, R2, #16
|
||||
BIC R1, R1, R2
|
||||
MOV R2, #0x05FA
|
||||
LSL R2, R2, #16
|
||||
ORR R1, R1, R2
|
||||
|
||||
BIC R1, R1, #0x4000
|
||||
MOV R2, #0x4000
|
||||
ORR R1, R1, R2
|
||||
STR R1, [R0]
|
||||
|
||||
MOV R0, #0
|
||||
MSR PSPLIM, R0
|
||||
MSR PSP, R0
|
||||
MOV R0, #2
|
||||
MSR CONTROL, R0
|
||||
BX LR
|
||||
.fnend
|
||||
|
||||
.type HalSecureContextLoadAsm, %function
|
||||
.global HalSecureContextLoadAsm
|
||||
HalSecureContextLoadAsm:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
MRS R1, IPSR
|
||||
CBZ R1, __ThreadMode
|
||||
|
||||
LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext->stackLimit. */
|
||||
MSR PSPLIM, R2 /* Restore PSPLIM. */
|
||||
MSR PSP, R1 /* Restore PSP. */
|
||||
BX LR
|
||||
.fnend
|
||||
|
||||
.type HalSecureContextSaveAsm, %function
|
||||
.global HalSecureContextSaveAsm
|
||||
HalSecureContextSaveAsm:
|
||||
.fnstart
|
||||
.cantunwind
|
||||
MRS R0, IPSR
|
||||
CBZ R0, __ThreadMode
|
||||
|
||||
MRS R0, PSP
|
||||
STR R0, [R1] /* g_secureContext->curStackPointer = R0. */
|
||||
MOV R0, #0
|
||||
MSR PSPLIM, R0 /* No PSPLIM for the current task. */
|
||||
MSR PSP, R0 /* No secure stack for the current task. */
|
||||
.fnend
|
||||
|
||||
__ThreadMode:
|
||||
BX LR
|
|
@ -0,0 +1,229 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_secure_heap.h"
|
||||
#include "los_secure_macros.h"
|
||||
#include "los_config.h"
|
||||
#include "los_list.h"
|
||||
|
||||
STATIC UINT8 __attribute__((aligned(0x4)))g_secureHeap[LOSCFG_SECURE_HEAP_SIZE] = {0};
|
||||
STATIC LOS_DL_LIST g_secureHeapFreeList = {NULL, NULL};
|
||||
|
||||
struct OsSecureHeapNode {
|
||||
LOS_DL_LIST freeNode;
|
||||
struct OsSecureHeapNode *preNode;
|
||||
UINT32 size : 24;
|
||||
UINT32 used : 8;
|
||||
};
|
||||
|
||||
#define OS_SECURE_HEAP_NODE_HEAD_SIZE sizeof(struct OsSecureHeapNode)
|
||||
#define OS_SECURE_HEAP_ALIGN_SIZE sizeof(UINTPTR)
|
||||
|
||||
#define OS_SECURE_HEAP_NODE_USED 1
|
||||
#define OS_SECURE_HEAP_NODE_FREE 0
|
||||
|
||||
#define OS_SECURE_HEAP_FIRST_NODE ((struct OsSecureHeapNode *)g_secureHeap)
|
||||
#define OS_SECURE_HEAP_NEXT_NODE(node) \
|
||||
((struct OsSecureHeapNode *)((UINT8 *)(node) + (node)->size))
|
||||
#define OS_SECURE_HEAP_END_NODE \
|
||||
((struct OsSecureHeapNode *)((UINT8 *)g_secureHeap + LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE))
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapListInit(LOS_DL_LIST *head)
|
||||
{
|
||||
head->pstPrev = head;
|
||||
head->pstNext = head;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapListDelete(LOS_DL_LIST *node)
|
||||
{
|
||||
node->pstNext->pstPrev = node->pstPrev;
|
||||
node->pstPrev->pstNext = node->pstNext;
|
||||
node->pstNext = NULL;
|
||||
node->pstPrev = NULL;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapListAdd(LOS_DL_LIST *listNode, LOS_DL_LIST *node)
|
||||
{
|
||||
node->pstNext = listNode->pstNext;
|
||||
node->pstPrev = listNode;
|
||||
listNode->pstNext->pstPrev = node;
|
||||
listNode->pstNext = node;
|
||||
}
|
||||
|
||||
STATIC struct OsSecureHeapNode *OsSecureHeapFindSuitableFreeBlock(UINT32 allocSize)
|
||||
{
|
||||
LOS_DL_LIST *listNodeHead = &g_secureHeapFreeList;
|
||||
struct OsSecureHeapNode *tmpNode = NULL;
|
||||
|
||||
LOS_DL_LIST_FOR_EACH_ENTRY(tmpNode, listNodeHead, struct OsSecureHeapNode, freeNode) {
|
||||
if (tmpNode->size >= allocSize) {
|
||||
return tmpNode;
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapClearNode(struct OsSecureHeapNode *node)
|
||||
{
|
||||
node->preNode = NULL;
|
||||
node->size = 0;
|
||||
node->used = 0;
|
||||
node->freeNode.pstPrev = NULL;
|
||||
node->freeNode.pstNext = NULL;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapMergeNode(struct OsSecureHeapNode *node)
|
||||
{
|
||||
struct OsSecureHeapNode *nextNode = NULL;
|
||||
|
||||
node->preNode->size += node->size;
|
||||
nextNode = (struct OsSecureHeapNode *)((UINTPTR)node + node->size);
|
||||
nextNode->preNode = node->preNode;
|
||||
OsSecureHeapClearNode(node);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapSplitNode(struct OsSecureHeapNode *allocNode, UINT32 allocSize)
|
||||
{
|
||||
struct OsSecureHeapNode *newFreeNode = NULL;
|
||||
struct OsSecureHeapNode *nextNode = NULL;
|
||||
|
||||
newFreeNode = (struct OsSecureHeapNode *)((UINT8 *)allocNode + allocSize);
|
||||
newFreeNode->preNode = allocNode;
|
||||
newFreeNode->size = allocNode->size - allocSize;
|
||||
newFreeNode->used = OS_SECURE_HEAP_NODE_FREE;
|
||||
allocNode->size = allocSize;
|
||||
nextNode = OS_SECURE_HEAP_NEXT_NODE(newFreeNode);
|
||||
nextNode->preNode = newFreeNode;
|
||||
if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
|
||||
OsSecureHeapListDelete(&nextNode->freeNode);
|
||||
OsSecureHeapMergeNode(nextNode);
|
||||
}
|
||||
|
||||
OsSecureHeapListAdd(&g_secureHeapFreeList, &newFreeNode->freeNode);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapFreeNode(struct OsSecureHeapNode *node)
|
||||
{
|
||||
struct OsSecureHeapNode *nextNode = NULL;
|
||||
|
||||
if ((node->preNode != NULL) && (node->preNode->used == OS_SECURE_HEAP_NODE_FREE)) {
|
||||
struct OsSecureHeapNode *preNode = node->preNode;
|
||||
OsSecureHeapMergeNode(node);
|
||||
nextNode = OS_SECURE_HEAP_NEXT_NODE(preNode);
|
||||
if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
|
||||
OsSecureHeapListDelete(&nextNode->freeNode);
|
||||
OsSecureHeapMergeNode(nextNode);
|
||||
}
|
||||
|
||||
OsSecureHeapListDelete(&preNode->freeNode);
|
||||
preNode->used = OS_SECURE_HEAP_NODE_FREE;
|
||||
OsSecureHeapListAdd(&g_secureHeapFreeList, &preNode->freeNode);
|
||||
} else {
|
||||
nextNode = OS_SECURE_HEAP_NEXT_NODE(node);
|
||||
if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
|
||||
OsSecureHeapListDelete(&nextNode->freeNode);
|
||||
OsSecureHeapMergeNode(nextNode);
|
||||
}
|
||||
|
||||
node->used = OS_SECURE_HEAP_NODE_FREE;
|
||||
OsSecureHeapListAdd(&g_secureHeapFreeList, &node->freeNode);
|
||||
}
|
||||
}
|
||||
|
||||
STATIC INLINE VOID *OsSecureHeapAllocNode(UINT32 size)
|
||||
{
|
||||
struct OsSecureHeapNode *allocNode = NULL;
|
||||
UINT32 allocSize;
|
||||
|
||||
allocSize = LOS_Align(size + OS_SECURE_HEAP_NODE_HEAD_SIZE, OS_SECURE_HEAP_ALIGN_SIZE);
|
||||
allocNode = OsSecureHeapFindSuitableFreeBlock(allocSize);
|
||||
if (allocNode == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
if ((allocSize + OS_SECURE_HEAP_NODE_HEAD_SIZE + OS_SECURE_HEAP_ALIGN_SIZE) <= allocNode->size) {
|
||||
OsSecureHeapSplitNode(allocNode, allocSize);
|
||||
}
|
||||
OsSecureHeapListDelete(&allocNode->freeNode);
|
||||
allocNode->used = OS_SECURE_HEAP_NODE_USED;
|
||||
|
||||
return (allocNode + 1);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapInit(VOID)
|
||||
{
|
||||
struct OsSecureHeapNode *newNode = NULL;
|
||||
struct OsSecureHeapNode *endNode = NULL;
|
||||
|
||||
newNode = OS_SECURE_HEAP_FIRST_NODE;
|
||||
newNode->size = LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE;
|
||||
newNode->preNode = OS_SECURE_HEAP_END_NODE;
|
||||
newNode->used = OS_SECURE_HEAP_NODE_FREE;
|
||||
|
||||
OsSecureHeapListInit(&g_secureHeapFreeList);
|
||||
OsSecureHeapListAdd(&g_secureHeapFreeList, &newNode->freeNode);
|
||||
|
||||
endNode = OS_SECURE_HEAP_END_NODE;
|
||||
endNode->preNode = newNode;
|
||||
endNode->size = OS_SECURE_HEAP_NODE_HEAD_SIZE;
|
||||
endNode->used = OS_SECURE_HEAP_NODE_USED;
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID *HalSecureMalloc(UINT32 size)
|
||||
{
|
||||
if (size == 0) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if ((g_secureHeapFreeList.pstPrev == NULL) &&
|
||||
(g_secureHeapFreeList.pstNext == NULL)) {
|
||||
OsSecureHeapInit();
|
||||
}
|
||||
|
||||
return OsSecureHeapAllocNode(size);
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureFree(VOID *ptr)
|
||||
{
|
||||
struct OsSecureHeapNode *node = NULL;
|
||||
|
||||
if (ptr == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
node = (struct OsSecureHeapNode *)((UINTPTR)ptr - OS_SECURE_HEAP_NODE_HEAD_SIZE);
|
||||
if (node->used != OS_SECURE_HEAP_NODE_USED) {
|
||||
return;
|
||||
}
|
||||
|
||||
OsSecureHeapFreeNode(node);
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_SECURE_HEAP_H
|
||||
#define _LOS_SECURE_HEAP_H
|
||||
|
||||
#include "los_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
VOID *HalSecureMalloc(UINT32 size);
|
||||
VOID HalSecureFree(VOID *ptr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_SECURE_MACROS_H
|
||||
#define _LOS_SECURE_MACROS_H
|
||||
|
||||
#include "los_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define OS_CMSE_NS_ENTRY __attribute__((cmse_nonsecure_entry))
|
||||
#define OS_CMSE_NS_CALL __attribute__((cmse_nonsecure_call))
|
||||
#define OS_IPSR_READ(ipsr) __asm volatile("MRS %0, IPSR" : "=r" (ipsr))
|
||||
|
||||
#define OS_SVC_ALLOCATE_SECURE_CONTEXT 0
|
||||
#define OS_SVC_FREE_SECURE_CONTEXT 1
|
||||
#define OS_SVC_START_SCHEDULE 2
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without modification,
|
||||
# are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
# conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
# of conditions and the following disclaimer in the documentation and/or other materials
|
||||
# provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
# to endorse or promote products derived from this software without specific prior written
|
||||
# permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
import("//kernel/liteos_m/liteos.gni")
|
||||
|
||||
module_group("iar") {
|
||||
if (defined(LOSCFG_SECURE_TRUSTZONE)) {
|
||||
modules = [ "TZ" ]
|
||||
} else {
|
||||
modules = [ "NTZ" ]
|
||||
}
|
||||
}
|
|
@ -0,0 +1,46 @@
|
|||
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without modification,
|
||||
# are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
# conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
# of conditions and the following disclaimer in the documentation and/or other materials
|
||||
# provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
# to endorse or promote products derived from this software without specific prior written
|
||||
# permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
import("//kernel/liteos_m/liteos.gni")
|
||||
|
||||
module_name = "arch"
|
||||
kernel_module(module_name) {
|
||||
sources = [
|
||||
"los_context.c",
|
||||
"los_dispatch.S",
|
||||
"los_exc.S",
|
||||
"los_interrupt.c",
|
||||
"los_timer.c",
|
||||
]
|
||||
configs += [ "$LITEOSTOPDIR:warn_config" ]
|
||||
}
|
||||
|
||||
config("public") {
|
||||
include_dirs = [ "." ]
|
||||
}
|
|
@ -0,0 +1,296 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_ARCH_ATOMIC_H
|
||||
#define _LOS_ARCH_ATOMIC_H
|
||||
|
||||
#include "los_compiler.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
|
||||
{
|
||||
INT32 val;
|
||||
|
||||
asm volatile("ldrex %0, [%1]\n"
|
||||
: "=&r"(val)
|
||||
: "r"(v)
|
||||
: "cc");
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
|
||||
{
|
||||
UINT32 status;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %0, [%1]\n"
|
||||
"strex %0, %2, [%1]\n"
|
||||
: "=&r"(status)
|
||||
: "r"(v), "r"(setVal)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
}
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
|
||||
{
|
||||
INT32 val;
|
||||
UINT32 status;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %1, [%2]\n"
|
||||
"add %1, %1, %3\n"
|
||||
"strex %0, %1, [%2]"
|
||||
: "=&r"(status), "=&r"(val)
|
||||
: "r"(v), "r"(addVal)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
|
||||
{
|
||||
INT32 val;
|
||||
UINT32 status;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %1, [%2]\n"
|
||||
"sub %1, %1, %3\n"
|
||||
"strex %0, %1, [%2]"
|
||||
: "=&r"(status), "=&r"(val)
|
||||
: "r"(v), "r"(subVal)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
|
||||
{
|
||||
(VOID)ArchAtomicAdd(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
|
||||
{
|
||||
(VOID)ArchAtomicSub(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
|
||||
{
|
||||
return ArchAtomicAdd(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
|
||||
{
|
||||
return ArchAtomicSub(v, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @ingroup los_arch_atomic
|
||||
* @brief Atomic exchange for 32-bit variable.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to implement the atomic exchange for 32-bit variable
|
||||
* and return the previous value of the atomic variable.
|
||||
* @attention
|
||||
* <ul>The pointer v must not be NULL.</ul>
|
||||
*
|
||||
* @param v [IN] The variable pointer.
|
||||
* @param val [IN] The exchange value.
|
||||
*
|
||||
* @retval #INT32 The previous value of the atomic variable
|
||||
* @par Dependency:
|
||||
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see
|
||||
*/
|
||||
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
|
||||
{
|
||||
INT32 prevVal = 0;
|
||||
UINT32 status = 0;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %0, [%2]\n"
|
||||
"strex %1, %3, [%2]"
|
||||
: "=&r"(prevVal), "=&r"(status)
|
||||
: "r"(v), "r"(val)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
|
||||
return prevVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @ingroup los_arch_atomic
|
||||
* @brief Atomic exchange for 32-bit variable with compare.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
|
||||
* @attention
|
||||
* <ul>The pointer v must not be NULL.</ul>
|
||||
*
|
||||
* @param v [IN] The variable pointer.
|
||||
* @param val [IN] The new value.
|
||||
* @param oldVal [IN] The old value.
|
||||
*
|
||||
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
|
||||
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see
|
||||
*/
|
||||
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
|
||||
{
|
||||
INT32 prevVal = 0;
|
||||
UINT32 status = 0;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %0, [%2]\n"
|
||||
"mov %1, #0\n"
|
||||
"cmp %0, %3\n"
|
||||
"bne 1f\n"
|
||||
"strex %1, %4, [%2]\n"
|
||||
"1:"
|
||||
: "=&r"(prevVal), "=&r"(status)
|
||||
: "r"(v), "r"(oldVal), "r"(val)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
|
||||
return prevVal != oldVal;
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
|
||||
{
|
||||
INT64 val;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
val = *v;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
|
||||
{
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
*v = setVal;
|
||||
LOS_IntRestore(intSave);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
|
||||
{
|
||||
INT64 val;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
*v += addVal;
|
||||
val = *v;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
|
||||
{
|
||||
INT64 val;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
*v -= subVal;
|
||||
val = *v;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
|
||||
{
|
||||
(VOID)ArchAtomic64Add(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
|
||||
{
|
||||
return ArchAtomic64Add(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
|
||||
{
|
||||
(VOID)ArchAtomic64Sub(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
|
||||
{
|
||||
return ArchAtomic64Sub(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
|
||||
{
|
||||
INT64 prevVal;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
prevVal = *v;
|
||||
*v = val;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return prevVal;
|
||||
}
|
||||
|
||||
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
|
||||
{
|
||||
INT64 prevVal;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
prevVal = *v;
|
||||
if (prevVal == oldVal) {
|
||||
*v = val;
|
||||
}
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return prevVal != oldVal;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_ARCH_ATOMIC_H */
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_ARCH_CONTEXT_H
|
||||
#define _LOS_ARCH_CONTEXT_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_compiler.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef struct TagTskContext {
|
||||
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined(__FPU_USED) && (__FPU_USED == 1U)))
|
||||
UINT32 S16;
|
||||
UINT32 S17;
|
||||
UINT32 S18;
|
||||
UINT32 S19;
|
||||
UINT32 S20;
|
||||
UINT32 S21;
|
||||
UINT32 S22;
|
||||
UINT32 S23;
|
||||
UINT32 S24;
|
||||
UINT32 S25;
|
||||
UINT32 S26;
|
||||
UINT32 S27;
|
||||
UINT32 S28;
|
||||
UINT32 S29;
|
||||
UINT32 S30;
|
||||
UINT32 S31;
|
||||
#endif
|
||||
UINT32 uwR4;
|
||||
UINT32 uwR5;
|
||||
UINT32 uwR6;
|
||||
UINT32 uwR7;
|
||||
UINT32 uwR8;
|
||||
UINT32 uwR9;
|
||||
UINT32 uwR10;
|
||||
UINT32 uwR11;
|
||||
UINT32 uwPriMask;
|
||||
UINT32 uwR0;
|
||||
UINT32 uwR1;
|
||||
UINT32 uwR2;
|
||||
UINT32 uwR3;
|
||||
UINT32 uwR12;
|
||||
UINT32 uwLR;
|
||||
UINT32 uwPC;
|
||||
UINT32 uwxPSR;
|
||||
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined(__FPU_USED) && (__FPU_USED == 1U)))
|
||||
UINT32 S0;
|
||||
UINT32 S1;
|
||||
UINT32 S2;
|
||||
UINT32 S3;
|
||||
UINT32 S4;
|
||||
UINT32 S5;
|
||||
UINT32 S6;
|
||||
UINT32 S7;
|
||||
UINT32 S8;
|
||||
UINT32 S9;
|
||||
UINT32 S10;
|
||||
UINT32 S11;
|
||||
UINT32 S12;
|
||||
UINT32 S13;
|
||||
UINT32 S14;
|
||||
UINT32 S15;
|
||||
UINT32 FPSCR;
|
||||
UINT32 NO_NAME;
|
||||
#endif
|
||||
} TaskContext;
|
||||
|
||||
/**
|
||||
* @ingroup los_config
|
||||
* @brief: Task start running function.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to start a task.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param: None.
|
||||
*
|
||||
* @retval None.
|
||||
*
|
||||
* @par Dependency:
|
||||
* <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalStartToRun(VOID);
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_ARCH_CONTEXT_H */
|
||||
|
|
@ -0,0 +1,684 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_EXC_H
|
||||
#define _LOS_EXC_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_compiler.h"
|
||||
#include "los_interrupt.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Maximum number of used hardware interrupts.
|
||||
*/
|
||||
#ifndef OS_HWI_MAX_NUM
|
||||
#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
|
||||
#endif
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Highest priority of a hardware interrupt.
|
||||
*/
|
||||
#ifndef OS_HWI_PRIO_HIGHEST
|
||||
#define OS_HWI_PRIO_HIGHEST 0
|
||||
#endif
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Lowest priority of a hardware interrupt.
|
||||
*/
|
||||
#ifndef OS_HWI_PRIO_LOWEST
|
||||
#define OS_HWI_PRIO_LOWEST 7
|
||||
#endif
|
||||
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Define the type of a hardware interrupt vector table function.
|
||||
*/
|
||||
typedef VOID (**HWI_VECTOR_FUNC)(void);
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Count of interrupts.
|
||||
*/
|
||||
extern UINT32 g_intCount;
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Count of M-Core system interrupt vector.
|
||||
*/
|
||||
#define OS_SYS_VECTOR_CNT 16
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Count of M-Core interrupt vector.
|
||||
*/
|
||||
#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* AIRCR register priority group parameter .
|
||||
*/
|
||||
#define OS_NVIC_AIRCR_PRIGROUP 7
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Boot interrupt vector table.
|
||||
*/
|
||||
extern UINT32 _BootVectors[];
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Invalid interrupt number.
|
||||
*
|
||||
* Value: 0x02000900
|
||||
*
|
||||
* Solution: Ensure that the interrupt number is valid.
|
||||
* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
|
||||
*/
|
||||
#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Null hardware interrupt handling function.
|
||||
*
|
||||
* Value: 0x02000901
|
||||
*
|
||||
* Solution: Pass in a valid non-null hardware interrupt handling function.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
|
||||
*
|
||||
* Value: 0x02000902
|
||||
*
|
||||
* Solution: Increase the configured maximum number of supported hardware interrupts.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
|
||||
*
|
||||
* Value: 0x02000903
|
||||
*
|
||||
* Solution: Expand the configured memory.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: The interrupt has already been created.
|
||||
*
|
||||
* Value: 0x02000904
|
||||
*
|
||||
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Invalid interrupt priority.
|
||||
*
|
||||
* Value: 0x02000905
|
||||
*
|
||||
* Solution: Ensure that the interrupt priority is valid.
|
||||
* The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
|
||||
*/
|
||||
#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Incorrect interrupt creation mode.
|
||||
*
|
||||
* Value: 0x02000906
|
||||
*
|
||||
* Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
|
||||
* OS_HWI_MODE_FAST of which the value can be 0 or 1.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
|
||||
*
|
||||
* Value: 0x02000907
|
||||
*
|
||||
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* SysTick control and status register.
|
||||
*/
|
||||
#define OS_SYSTICK_CONTROL_REG 0xE000E010
|
||||
|
||||
/* *
|
||||
* @ingroup los_hw
|
||||
* SysTick current value register.
|
||||
*/
|
||||
#define OS_SYSTICK_CURRENT_REG 0xE000E018
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt Priority-Level Registers.
|
||||
*/
|
||||
#define OS_NVIC_PRI_BASE 0xE000E400
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt enable register for 0-31.
|
||||
*/
|
||||
#define OS_NVIC_SETENA_BASE 0xE000E100
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* interrupt pending register.
|
||||
*/
|
||||
#define OS_NVIC_SETPEND_BASE 0xE000E200
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt active register.
|
||||
*/
|
||||
#define OS_NVIC_INT_ACT_BASE 0xE000E300
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt disable register for 0-31.
|
||||
*/
|
||||
#define OS_NVIC_CLRENA_BASE 0xE000E180
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt control and status register.
|
||||
*/
|
||||
#define OS_NVIC_INT_CTRL 0xE000ED04
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Vector table offset register.
|
||||
*/
|
||||
#define OS_NVIC_VTOR 0xE000ED08
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Application interrupt and reset control register
|
||||
*/
|
||||
#define OS_NVIC_AIRCR 0xE000ED0C
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* System exception priority register.
|
||||
*/
|
||||
#define OS_NVIC_EXCPRI_BASE 0xE000ED18
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 1 :reset.
|
||||
*/
|
||||
#define OS_EXC_RESET 1
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 2 :Non-Maskable Interrupt.
|
||||
*/
|
||||
#define OS_EXC_NMI 2
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 3 :(hard)fault.
|
||||
*/
|
||||
#define OS_EXC_HARD_FAULT 3
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 4 :MemManage fault.
|
||||
*/
|
||||
#define OS_EXC_MPU_FAULT 4
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 5 :Bus fault.
|
||||
*/
|
||||
#define OS_EXC_BUS_FAULT 5
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 6 :Usage fault.
|
||||
*/
|
||||
#define OS_EXC_USAGE_FAULT 6
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 11 :SVCall.
|
||||
*/
|
||||
#define OS_EXC_SVC_CALL 11
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 12 :Debug monitor.
|
||||
*/
|
||||
#define OS_EXC_DBG_MONITOR 12
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 14 :PendSV.
|
||||
*/
|
||||
#define OS_EXC_PEND_SV 14
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 15 :SysTick.
|
||||
*/
|
||||
#define OS_EXC_SYS_TICK 15
|
||||
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
|
||||
#else
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
|
||||
#endif
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* @brief: Hardware interrupt entry function.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used as all hardware interrupt handling function entry.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalInterrupt(VOID);
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* @brief: Default vector handling function.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to configure interrupt for null function.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li
|
||||
></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalHwiDefaultHandler(VOID);
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* @brief: Reset the vector table.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to reset the vector table.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID Reset_Handler(VOID);
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* @brief: Pended System Call.
|
||||
*
|
||||
* @par Description:
|
||||
* PendSV can be pended and is useful for an OS to pend an exception
|
||||
* so that an action can be performed after other important tasks are completed.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalPendSV(VOID);
|
||||
|
||||
|
||||
#define OS_EXC_IN_INIT 0
|
||||
#define OS_EXC_IN_TASK 1
|
||||
#define OS_EXC_IN_HWI 2
|
||||
|
||||
#define OS_EXC_MAX_BUF_LEN 25
|
||||
#define OS_EXC_MAX_NEST_DEPTH 1
|
||||
|
||||
#define OS_NVIC_SHCSR 0xE000ED24
|
||||
#define OS_NVIC_CCR 0xE000ED14
|
||||
|
||||
#define OS_NVIC_INT_ENABLE_SIZE 0x20
|
||||
#define OS_NVIC_INT_PRI_SIZE 0xF0
|
||||
#define OS_NVIC_EXCPRI_SIZE 0xC
|
||||
#define OS_NVIC_INT_CTRL_SIZE 4
|
||||
#define OS_NVIC_SHCSR_SIZE 4
|
||||
|
||||
#define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE
|
||||
#define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE
|
||||
|
||||
#define OS_EXC_FLAG_NO_FLOAT 0x10000000
|
||||
#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
|
||||
#define OS_EXC_FLAG_IN_HWI 0x02
|
||||
|
||||
#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
|
||||
|
||||
#define OS_EXC_EVENT 0x00000001
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* the struct of register files
|
||||
*
|
||||
* description: the register files that saved when exception triggered
|
||||
*
|
||||
* notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
|
||||
*/
|
||||
typedef struct TagExcContext {
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
UINT32 S16;
|
||||
UINT32 S17;
|
||||
UINT32 S18;
|
||||
UINT32 S19;
|
||||
UINT32 S20;
|
||||
UINT32 S21;
|
||||
UINT32 S22;
|
||||
UINT32 S23;
|
||||
UINT32 S24;
|
||||
UINT32 S25;
|
||||
UINT32 S26;
|
||||
UINT32 S27;
|
||||
UINT32 S28;
|
||||
UINT32 S29;
|
||||
UINT32 S30;
|
||||
UINT32 S31;
|
||||
#endif
|
||||
UINT32 uwR4;
|
||||
UINT32 uwR5;
|
||||
UINT32 uwR6;
|
||||
UINT32 uwR7;
|
||||
UINT32 uwR8;
|
||||
UINT32 uwR9;
|
||||
UINT32 uwR10;
|
||||
UINT32 uwR11;
|
||||
UINT32 uwPriMask;
|
||||
/* auto save */
|
||||
UINT32 uwSP;
|
||||
UINT32 uwR0;
|
||||
UINT32 uwR1;
|
||||
UINT32 uwR2;
|
||||
UINT32 uwR3;
|
||||
UINT32 uwR12;
|
||||
UINT32 uwLR;
|
||||
UINT32 uwPC;
|
||||
UINT32 uwxPSR;
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED) && (__FPU_USED== 1U)))
|
||||
UINT32 S0;
|
||||
UINT32 S1;
|
||||
UINT32 S2;
|
||||
UINT32 S3;
|
||||
UINT32 S4;
|
||||
UINT32 S5;
|
||||
UINT32 S6;
|
||||
UINT32 S7;
|
||||
UINT32 S8;
|
||||
UINT32 S9;
|
||||
UINT32 S10;
|
||||
UINT32 S11;
|
||||
UINT32 S12;
|
||||
UINT32 S13;
|
||||
UINT32 S14;
|
||||
UINT32 S15;
|
||||
UINT32 FPSCR;
|
||||
UINT32 NO_NAME;
|
||||
#endif
|
||||
}EXC_CONTEXT_S;
|
||||
|
||||
typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
|
||||
VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
|
||||
|
||||
VOID HalExcNMI(VOID);
|
||||
VOID HalExcHardFault(VOID);
|
||||
VOID HalExcMemFault(VOID);
|
||||
VOID HalExcBusFault(VOID);
|
||||
VOID HalExcUsageFault(VOID);
|
||||
VOID HalSVCHandler(VOID);
|
||||
VOID HalHwiInit(VOID);
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the bus status register was being pushed.
|
||||
*/
|
||||
#define OS_EXC_BF_STKERR 1
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the bus status register was out of the stack.
|
||||
*/
|
||||
#define OS_EXC_BF_UNSTKERR 2
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Bus status register imprecise data access violation.
|
||||
*/
|
||||
#define OS_EXC_BF_IMPRECISERR 3
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Bus status register exact data access violation.
|
||||
*/
|
||||
#define OS_EXC_BF_PRECISERR 4
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Bus status register access violation while pointing.
|
||||
*/
|
||||
#define OS_EXC_BF_IBUSERR 5
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the memory management status register was being pushed.
|
||||
*/
|
||||
#define OS_EXC_MF_MSTKERR 6
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
|
||||
*/
|
||||
#define OS_EXC_MF_MUNSTKERR 7
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Memory management status register data access violation.
|
||||
*/
|
||||
#define OS_EXC_MF_DACCVIOL 8
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Memory management status register access violation.
|
||||
*/
|
||||
#define OS_EXC_MF_IACCVIOL 9
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
|
||||
*/
|
||||
#define OS_EXC_UF_DIVBYZERO 10
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Usage error, error caused by unaligned access.
|
||||
*/
|
||||
#define OS_EXC_UF_UNALIGNED 11
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
|
||||
*/
|
||||
#define OS_EXC_UF_NOCP 12
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
|
||||
*/
|
||||
#define OS_EXC_UF_INVPC 13
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
|
||||
*/
|
||||
#define OS_EXC_UF_INVSTATE 14
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
|
||||
*/
|
||||
#define OS_EXC_UF_UNDEFINSTR 15
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: NMI
|
||||
*/
|
||||
|
||||
#define OS_EXC_CAUSE_NMI 16
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: hard fault
|
||||
*/
|
||||
#define OS_EXC_CAUSE_HARDFAULT 17
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: The task handler exits.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_TASK_EXIT 18
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: A fatal error.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_FATAL_ERR 19
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Hard Fault caused by a debug event.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_DEBUGEVT 20
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_VECTBL 21
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Exception information structure
|
||||
*
|
||||
* Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
|
||||
*
|
||||
*/
|
||||
typedef struct TagExcInfo {
|
||||
/**< Exception occurrence phase: 0 means that an exception occurs in initialization,
|
||||
* 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
|
||||
UINT16 phase;
|
||||
/**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
|
||||
UINT16 type;
|
||||
/**< If the exact address access error indicates the wrong access address when the exception occurred */
|
||||
UINT32 faultAddr;
|
||||
/**< An exception occurs in an interrupt, indicating the interrupt number.
|
||||
* An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
|
||||
UINT32 thrdPid;
|
||||
/**< Number of nested exceptions. Currently only registered hook functions are supported
|
||||
* when an exception is entered for the first time */
|
||||
UINT16 nestCnt;
|
||||
/**< reserve */
|
||||
UINT16 reserved;
|
||||
/**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
|
||||
EXC_CONTEXT_S *context;
|
||||
} ExcInfo;
|
||||
|
||||
extern UINT32 g_curNestCount;
|
||||
extern UINT32 g_intCount;
|
||||
extern UINT8 g_uwExcTbl[32];
|
||||
extern ExcInfo g_excInfo;
|
||||
|
||||
#define MAX_INT_INFO_SIZE (8 + 0x164)
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_EXC_H */
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_ARCH_TIMER_H
|
||||
#define _LOS_ARCH_TIMER_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_compiler.h"
|
||||
#include "los_timer.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_ARCH_TIMER_H */
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_context.h"
|
||||
#include "securec.h"
|
||||
#include "los_arch_context.h"
|
||||
#include "los_arch_interrupt.h"
|
||||
#include "los_task.h"
|
||||
#include "los_sched.h"
|
||||
#include "los_interrupt.h"
|
||||
#include "los_debug.h"
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchInit
|
||||
Description : arch init function
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
|
||||
{
|
||||
HalHwiInit();
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchSysExit
|
||||
Description : Task exit function
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
|
||||
{
|
||||
LOS_IntLock();
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchTskStackInit
|
||||
Description : Task stack initialization function
|
||||
Input : taskID --- TaskID
|
||||
stackSize --- Total size of the stack
|
||||
topStack --- Top of task's stack
|
||||
Output : None
|
||||
Return : Context pointer
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
|
||||
{
|
||||
TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
|
||||
|
||||
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined(__FPU_USED) && (__FPU_USED == 1U)))
|
||||
context->S16 = 0xAA000010;
|
||||
context->S17 = 0xAA000011;
|
||||
context->S18 = 0xAA000012;
|
||||
context->S19 = 0xAA000013;
|
||||
context->S20 = 0xAA000014;
|
||||
context->S21 = 0xAA000015;
|
||||
context->S22 = 0xAA000016;
|
||||
context->S23 = 0xAA000017;
|
||||
context->S24 = 0xAA000018;
|
||||
context->S25 = 0xAA000019;
|
||||
context->S26 = 0xAA00001A;
|
||||
context->S27 = 0xAA00001B;
|
||||
context->S28 = 0xAA00001C;
|
||||
context->S29 = 0xAA00001D;
|
||||
context->S30 = 0xAA00001E;
|
||||
context->S31 = 0xAA00001F;
|
||||
context->S0 = 0xAA000000;
|
||||
context->S1 = 0xAA000001;
|
||||
context->S2 = 0xAA000002;
|
||||
context->S3 = 0xAA000003;
|
||||
context->S4 = 0xAA000004;
|
||||
context->S5 = 0xAA000005;
|
||||
context->S6 = 0xAA000006;
|
||||
context->S7 = 0xAA000007;
|
||||
context->S8 = 0xAA000008;
|
||||
context->S9 = 0xAA000009;
|
||||
context->S10 = 0xAA00000A;
|
||||
context->S11 = 0xAA00000B;
|
||||
context->S12 = 0xAA00000C;
|
||||
context->S13 = 0xAA00000D;
|
||||
context->S14 = 0xAA00000E;
|
||||
context->S15 = 0xAA00000F;
|
||||
context->FPSCR = 0x00000000;
|
||||
context->NO_NAME = 0xAA000011;
|
||||
#endif
|
||||
|
||||
context->uwR4 = 0x04040404L;
|
||||
context->uwR5 = 0x05050505L;
|
||||
context->uwR6 = 0x06060606L;
|
||||
context->uwR7 = 0x07070707L;
|
||||
context->uwR8 = 0x08080808L;
|
||||
context->uwR9 = 0x09090909L;
|
||||
context->uwR10 = 0x10101010L;
|
||||
context->uwR11 = 0x11111111L;
|
||||
context->uwPriMask = 0;
|
||||
context->uwR0 = taskID;
|
||||
context->uwR1 = 0x01010101L;
|
||||
context->uwR2 = 0x02020202L;
|
||||
context->uwR3 = 0x03030303L;
|
||||
context->uwR12 = 0x12121212L;
|
||||
context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
|
||||
context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
|
||||
context->uwxPSR = 0x01000000L;
|
||||
|
||||
return (VOID *)context;
|
||||
}
|
||||
|
||||
VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
|
||||
{
|
||||
UNUSED(stackTop);
|
||||
TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
|
||||
(VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
|
||||
|
||||
context->uwR0 = param;
|
||||
context->uwPC = sigHandler;
|
||||
context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
|
||||
|
||||
return (VOID *)context;
|
||||
}
|
||||
|
||||
LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
|
||||
{
|
||||
(VOID)LOS_IntLock();
|
||||
OsSchedStart();
|
||||
HalStartToRun();
|
||||
return LOS_OK; /* never return */
|
||||
}
|
|
@ -0,0 +1,175 @@
|
|||
;
|
||||
; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without modification,
|
||||
; are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
; conditions and the following disclaimer.
|
||||
;
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
; of conditions and the following disclaimer in the documentation and/or other materials
|
||||
; provided with the distribution.
|
||||
;
|
||||
; 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without specific prior written
|
||||
; permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
|
||||
PRESERVE8
|
||||
|
||||
EXPORT ArchIntLock
|
||||
EXPORT ArchIntUnLock
|
||||
EXPORT ArchIntRestore
|
||||
EXPORT HalStartToRun
|
||||
EXPORT ArchTaskSchedule
|
||||
EXPORT HalPendSV
|
||||
IMPORT OsSchedTaskSwitch
|
||||
IMPORT OsSignalTaskContextRestore
|
||||
IMPORT g_losTask
|
||||
|
||||
OS_FPU_CPACR EQU 0xE000ED88
|
||||
OS_FPU_CPACR_ENABLE EQU 0x00F00000
|
||||
OS_NVIC_INT_CTRL EQU 0xE000ED04
|
||||
OS_NVIC_SYSPRI2 EQU 0xE000ED20
|
||||
OS_NVIC_PENDSV_PRI EQU 0xF0F00000
|
||||
OS_NVIC_PENDSVSET EQU 0x10000000
|
||||
OS_TASK_STATUS_RUNNING EQU 0x0010
|
||||
|
||||
SECTION .text:CODE(2)
|
||||
THUMB
|
||||
REQUIRE8
|
||||
|
||||
MACRO SIGNAL_CONTEXT_RESTORE
|
||||
PUSH {R12, LR}
|
||||
BLX OsSignalTaskContextRestore
|
||||
POP {R12, LR}
|
||||
CMP R0, #0
|
||||
MOV R1, R0
|
||||
BNE SignalContextRestore
|
||||
ENDM
|
||||
|
||||
HalStartToRun
|
||||
LDR R4, =OS_NVIC_SYSPRI2
|
||||
LDR R5, =OS_NVIC_PENDSV_PRI
|
||||
STR R5, [R4]
|
||||
|
||||
MOV R0, #2
|
||||
MSR CONTROL, R0
|
||||
|
||||
LDR R1, =g_losTask
|
||||
LDR R0, [R1, #4]
|
||||
LDR R12, [R0]
|
||||
|
||||
LDR.W R1, =OS_FPU_CPACR
|
||||
LDR R1, [R1]
|
||||
AND R1, R1, #OS_FPU_CPACR_ENABLE
|
||||
CMP R1, #OS_FPU_CPACR_ENABLE
|
||||
BNE __DisabledFPU
|
||||
ADD R12, R12, #100
|
||||
|
||||
LDMFD R12!, {R0-R7}
|
||||
ADD R12, R12, #72
|
||||
MSR PSP, R12
|
||||
VPUSH S0;
|
||||
VPOP S0;
|
||||
MOV LR, R5
|
||||
CPSIE I
|
||||
BX R6
|
||||
|
||||
__DisabledFPU
|
||||
ADD R12, R12, #36
|
||||
|
||||
LDMFD R12!, {R0-R7}
|
||||
MSR PSP, R12
|
||||
MOV LR, R5
|
||||
CPSIE I
|
||||
BX R6
|
||||
|
||||
|
||||
ArchIntLock
|
||||
MRS R0, PRIMASK
|
||||
CPSID I
|
||||
BX LR
|
||||
|
||||
ArchIntUnLock
|
||||
MRS R0, PRIMASK
|
||||
CPSIE I
|
||||
BX LR
|
||||
|
||||
ArchIntRestore
|
||||
MSR PRIMASK, R0
|
||||
BX LR
|
||||
|
||||
ArchTaskSchedule
|
||||
LDR R0, =OS_NVIC_INT_CTRL
|
||||
LDR R1, =OS_NVIC_PENDSVSET
|
||||
STR R1, [R0]
|
||||
DSB
|
||||
ISB
|
||||
BX LR
|
||||
|
||||
HalPendSV
|
||||
MRS R12, PRIMASK
|
||||
CPSID I
|
||||
|
||||
HalTaskSwitch
|
||||
PUSH {R12, LR}
|
||||
BLX OsSchedTaskSwitch
|
||||
POP {R12, LR}
|
||||
CMP R0, #0
|
||||
MOV R0, LR
|
||||
BNE TaskContextSwitch
|
||||
MSR PRIMASK, R12
|
||||
BX LR
|
||||
|
||||
TaskContextSwitch
|
||||
MOV LR, R0
|
||||
MRS R0, PSP
|
||||
|
||||
STMFD R0!, {R4-R12}
|
||||
LDR.W R3, =OS_FPU_CPACR
|
||||
LDR R3, [R3]
|
||||
AND R3, R3, #OS_FPU_CPACR_ENABLE
|
||||
CMP R3, #OS_FPU_CPACR_ENABLE
|
||||
BNE __DisabledFPU1
|
||||
VSTMDB R0!, {D8-D15}
|
||||
|
||||
__DisabledFPU1
|
||||
LDR R5, =g_losTask
|
||||
LDR R6, [R5]
|
||||
STR R0, [R6]
|
||||
|
||||
LDR R0, [R5, #4]
|
||||
STR R0, [R5]
|
||||
LDR R1, [R0]
|
||||
|
||||
SignalContextRestore
|
||||
LDR.W R3, =OS_FPU_CPACR
|
||||
LDR R3, [R3]
|
||||
AND R3, R3, #OS_FPU_CPACR_ENABLE
|
||||
CMP R3, #OS_FPU_CPACR_ENABLE
|
||||
BNE __DisabledFPU2
|
||||
VLDMIA R1!, {D8-D15}
|
||||
|
||||
__DisabledFPU2
|
||||
LDMFD R1!, {R4-R12}
|
||||
MSR PSP, R1
|
||||
|
||||
MSR PRIMASK, R12
|
||||
BX LR
|
||||
|
||||
END
|
|
@ -0,0 +1,285 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
PRESERVE8
|
||||
SECTION .text:CODE(2)
|
||||
THUMB
|
||||
|
||||
EXPORT HalExcNMI
|
||||
EXPORT HalExcHardFault
|
||||
EXPORT HalExcMemFault
|
||||
EXPORT HalExcBusFault
|
||||
EXPORT HalExcUsageFault
|
||||
EXPORT HalSVCHandler
|
||||
|
||||
IMPORT HalExcHandleEntry
|
||||
IMPORT g_uwExcTbl
|
||||
IMPORT g_taskScheduled
|
||||
|
||||
OS_FLG_BGD_ACTIVE EQU 0x0002
|
||||
|
||||
OS_EXC_CAUSE_NMI EQU 16
|
||||
OS_EXC_CAUSE_HARDFAULT EQU 17
|
||||
|
||||
HF_DEBUGEVT EQU 20
|
||||
HF_VECTBL EQU 21
|
||||
|
||||
FLAG_ADDR_VALID EQU 0x10000
|
||||
FLAG_HWI_ACTIVE EQU 0x20000
|
||||
FLAG_NO_FLOAT EQU 0x10000000
|
||||
|
||||
OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Register
|
||||
OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Register
|
||||
OS_NVIC_BFAR EQU 0xE000ED38
|
||||
OS_NVIC_MMAR EQU 0xE000ED34
|
||||
OS_NVIC_ACT_BASE EQU 0xE000E300
|
||||
OS_NVIC_SHCSRS EQU 0xE000ED24
|
||||
OS_NVIC_SHCSR_MASK EQU 0xC00
|
||||
|
||||
HalExcNMI
|
||||
MOV R0, #OS_EXC_CAUSE_NMI
|
||||
MOV R1, #0
|
||||
B osExcDispatch
|
||||
|
||||
HalExcHardFault
|
||||
MOV R0, #OS_EXC_CAUSE_HARDFAULT
|
||||
LDR R2, =OS_NVIC_HFSR
|
||||
LDR R2, [R2]
|
||||
|
||||
MOV R1, #HF_DEBUGEVT
|
||||
ORR R0, R0, R1, LSL #0x8
|
||||
TST R2, #0x80000000
|
||||
BNE osExcDispatch ; DEBUGEVT
|
||||
|
||||
AND R0, R0 , #0x000000FF
|
||||
MOV R1, #HF_VECTBL
|
||||
ORR R0, R0, R1, LSL #0x8
|
||||
TST R2, #0x00000002
|
||||
BNE osExcDispatch ; VECTBL
|
||||
|
||||
;if not DEBUGEVT and VECTBL then is FORCED
|
||||
AND R0, R0, #0x000000FF
|
||||
|
||||
LDR R2, =OS_NVIC_FSR
|
||||
LDR R2, [R2]
|
||||
|
||||
TST R2, #0x8000 ; BFARVALID
|
||||
BNE _HFBusFault ; BusFault
|
||||
|
||||
TST R2, #0x80 ; MMARVALID
|
||||
BNE _HFMemFault ; MemFault
|
||||
|
||||
MOV R12,#0
|
||||
B osHFExcCommonBMU
|
||||
|
||||
_HFBusFault
|
||||
LDR R1, =OS_NVIC_BFAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
B osHFExcCommonBMU
|
||||
|
||||
_HFMemFault
|
||||
LDR R1, =OS_NVIC_MMAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
|
||||
osHFExcCommonBMU
|
||||
CLZ R2, R2
|
||||
LDR R3, =g_uwExcTbl
|
||||
ADD R3, R3, R2
|
||||
LDRB R2, [R3]
|
||||
ORR R0, R0, R2, LSL #0x8
|
||||
ORR R0, R0 ,R12
|
||||
B osExcDispatch
|
||||
|
||||
HalSVCHandler
|
||||
TST LR, #0x4
|
||||
ITE EQ
|
||||
MRSEQ R0, MSP
|
||||
MRSNE R0, PSP
|
||||
LDR R1, [R0,#24]
|
||||
LDRB R0, [R1,#-2]
|
||||
MOV R1, #0
|
||||
B osExcDispatch
|
||||
|
||||
HalExcBusFault
|
||||
LDR R0, =OS_NVIC_FSR
|
||||
LDR R0, [R0]
|
||||
|
||||
TST R0, #0x8000 ; BFARVALID
|
||||
BEQ _ExcBusNoADDR
|
||||
LDR R1, =OS_NVIC_BFAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
AND R0, R0, #0x1F00
|
||||
|
||||
B osExcCommonBMU
|
||||
|
||||
_ExcBusNoADDR
|
||||
MOV R12,#0
|
||||
B osExcCommonBMU
|
||||
|
||||
HalExcMemFault
|
||||
LDR R0, =OS_NVIC_FSR
|
||||
LDR R0, [R0]
|
||||
|
||||
TST R0, #0x80 ; MMARVALID
|
||||
BEQ _ExcMemNoADDR
|
||||
LDR R1, =OS_NVIC_MMAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
AND R0, R0, #0x1B
|
||||
|
||||
B osExcCommonBMU
|
||||
|
||||
_ExcMemNoADDR
|
||||
MOV R12,#0
|
||||
B osExcCommonBMU
|
||||
|
||||
HalExcUsageFault
|
||||
LDR R0, =OS_NVIC_FSR
|
||||
LDR R0, [R0]
|
||||
|
||||
MOV R1, #0x030F
|
||||
LSL R1, R1, #16
|
||||
AND R0, R0, R1
|
||||
MOV R12, #0
|
||||
|
||||
osExcCommonBMU
|
||||
CLZ R0, R0
|
||||
LDR R3, =g_uwExcTbl
|
||||
ADD R3, R3, R0
|
||||
LDRB R0, [R3]
|
||||
ORR R0, R0, R12
|
||||
|
||||
; R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid), R1 -- EXCADDR
|
||||
osExcDispatch
|
||||
LDR R2, =OS_NVIC_ACT_BASE
|
||||
MOV R12, #8 ; R12 is hwi check loop counter
|
||||
|
||||
_hwiActiveCheck
|
||||
LDR R3, [R2] ; R3 store active hwi register when exc
|
||||
CMP R3, #0
|
||||
BEQ _hwiActiveCheckNext
|
||||
|
||||
; exc occurred in IRQ
|
||||
ORR R0, R0, #FLAG_HWI_ACTIVE
|
||||
RBIT R2, R3
|
||||
CLZ R2, R2
|
||||
AND R12, R12, #1
|
||||
ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as uwPid
|
||||
|
||||
_ExcInMSP
|
||||
CMP LR, #0xFFFFFFE9
|
||||
BNE _NoFloatInMsp
|
||||
ADD R3, R13, #104
|
||||
PUSH {R3}
|
||||
MRS R12, PRIMASK ; store message-->exc: disable int?
|
||||
PUSH {R4-R12} ; store message-->exc: {R4-R12}
|
||||
VPUSH {D8-D15}
|
||||
B _handleEntry
|
||||
|
||||
_NoFloatInMsp
|
||||
ADD R3, R13, #32
|
||||
PUSH {R3} ; save IRQ SP ; store message-->exc: MSP(R13)
|
||||
|
||||
MRS R12, PRIMASK ; store message-->exc: disable int?
|
||||
PUSH {R4-R12} ; store message-->exc: {R4-R12}
|
||||
ORR R0, R0, #FLAG_NO_FLOAT
|
||||
B _handleEntry
|
||||
|
||||
_hwiActiveCheckNext
|
||||
ADD R2, R2, #4 ; next NVIC ACT ADDR
|
||||
SUBS R12, R12, #1
|
||||
BNE _hwiActiveCheck
|
||||
|
||||
;/*NMI interrupt excption*/
|
||||
LDR R2, =OS_NVIC_SHCSRS
|
||||
LDRH R2,[R2]
|
||||
LDR R3,=OS_NVIC_SHCSR_MASK
|
||||
AND R2, R2,R3
|
||||
CMP R2,#0
|
||||
BNE _ExcInMSP
|
||||
; exc occurred in Task or Init or exc
|
||||
; reserved for register info from task stack
|
||||
|
||||
LDR R2, =g_taskScheduled
|
||||
LDR R2, [R2]
|
||||
TST R2, #1 ; OS_FLG_BGD_ACTIVE
|
||||
BEQ _ExcInMSP ; if exc occurred in Init then branch
|
||||
|
||||
|
||||
CMP LR, #0xFFFFFFED ;auto push floating registers
|
||||
BNE _NoFloatInPsp
|
||||
|
||||
; exc occurred in Task
|
||||
MOV R2, R13
|
||||
SUB R13, #96 ; add 8 Bytes reg(for STMFD)
|
||||
|
||||
MRS R3, PSP
|
||||
ADD R12, R3, #104
|
||||
PUSH {R12} ; save task SP
|
||||
|
||||
MRS R12, PRIMASK
|
||||
PUSH {R4-R12}
|
||||
VPUSH {D8-D15}
|
||||
|
||||
; copy auto saved task register
|
||||
|
||||
LDMFD R3!, {R4-R11} ; R4-R11 store PSP reg(auto push when exc in task)
|
||||
VLDMIA R3!, {D8-D15}
|
||||
VSTMDB R2!, {D8-D15}
|
||||
STMFD R2!, {R4-R11}
|
||||
B _handleEntry
|
||||
|
||||
_NoFloatInPsp
|
||||
MOV R2, R13 ;no auto push floating registers
|
||||
SUB R13, #32 ; add 8 Bytes reg(for STMFD)
|
||||
|
||||
MRS R3, PSP
|
||||
ADD R12, R3, #32
|
||||
PUSH {R12} ; save task SP
|
||||
|
||||
MRS R12, PRIMASK
|
||||
PUSH {R4-R12}
|
||||
|
||||
LDMFD R3, {R4-R11} ; R4-R11 store PSP reg(auto push when exc in task)
|
||||
STMFD R2!, {R4-R11}
|
||||
ORR R0, R0, #FLAG_NO_FLOAT
|
||||
|
||||
_handleEntry
|
||||
MOV R3, R13 ; R13:the 4th param
|
||||
CPSID I
|
||||
CPSID F
|
||||
B HalExcHandleEntry
|
||||
|
||||
NOP
|
||||
END
|
|
@ -0,0 +1,654 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_interrupt.h"
|
||||
#include "securec.h"
|
||||
#include <stdarg.h>
|
||||
#include "los_arch_interrupt.h"
|
||||
#include "los_context.h"
|
||||
#include "los_debug.h"
|
||||
#include "los_hook.h"
|
||||
#include "los_task.h"
|
||||
#include "los_sched.h"
|
||||
#include "los_memory.h"
|
||||
#include "los_membox.h"
|
||||
#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
|
||||
#include "los_cpup.h"
|
||||
#endif
|
||||
|
||||
/*lint -save -e40 -e522 -e533*/
|
||||
UINT32 g_intCount = 0;
|
||||
|
||||
/*lint -restore*/
|
||||
#pragma location = ".data.vector"
|
||||
#pragma data_alignment = LOSCFG_ARCH_HWI_VECTOR_ALIGN
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* hardware interrupt form mapping handling function array.
|
||||
*/
|
||||
STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
|
||||
|
||||
#if (LOSCFG_DEBUG_TOOLS == 1)
|
||||
STATIC UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM] = {0};
|
||||
STATIC CHAR *g_hwiFormName[OS_HWI_MAX_NUM] = {0};
|
||||
|
||||
UINT32 OsGetHwiFormCnt(UINT32 index)
|
||||
{
|
||||
return g_hwiFormCnt[index];
|
||||
}
|
||||
|
||||
CHAR *OsGetHwiFormName(UINT32 index)
|
||||
{
|
||||
return g_hwiFormName[index];
|
||||
}
|
||||
|
||||
BOOL OsGetHwiCreated(UINT32 index)
|
||||
{
|
||||
if (g_hwiForm[index] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
|
||||
typedef struct {
|
||||
HWI_PROC_FUNC pfnHandler;
|
||||
VOID *pParm;
|
||||
} HWI_HANDLER_FUNC;
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* hardware interrupt handler form mapping handling function array.
|
||||
*/
|
||||
STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
|
||||
{
|
||||
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
|
||||
g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
|
||||
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
|
||||
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* hardware interrupt handler form mapping handling function array.
|
||||
*/
|
||||
STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
|
||||
{
|
||||
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
|
||||
g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
|
||||
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
WEAK VOID SysTick_Handler(VOID)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HwiNumGet
|
||||
Description : Get an interrupt number
|
||||
Input : None
|
||||
Output : None
|
||||
Return : Interrupt Indexes number
|
||||
**************************************************************************** */
|
||||
STATIC UINT32 HwiNumGet(VOID)
|
||||
{
|
||||
return __get_IPSR();
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_EnableIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_DisableIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
if (priority > OS_HWI_PRIO_LOWEST) {
|
||||
return OS_ERRNO_HWI_PRIO_INVALID;
|
||||
}
|
||||
|
||||
NVIC_SetPriority((IRQn_Type)hwiNum, priority);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
HwiControllerOps g_archHwiOps = {
|
||||
.enableIrq = HwiUnmask,
|
||||
.disableIrq = HwiMask,
|
||||
.setIrqPriority = HwiSetPriority,
|
||||
.getCurIrqNum = HwiNumGet,
|
||||
.triggerIrq = HwiPending,
|
||||
.clearIrq = HwiClear,
|
||||
};
|
||||
|
||||
inline UINT32 ArchIsIntActive(VOID)
|
||||
{
|
||||
return (g_intCount > 0);
|
||||
}
|
||||
/* ****************************************************************************
|
||||
Function : HalHwiDefaultHandler
|
||||
Description : default handler of the hardware interrupt
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
/*lint -e529*/
|
||||
LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
|
||||
{
|
||||
PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
WEAK VOID HalPreInterruptHandler(UINT32 arg)
|
||||
{
|
||||
(VOID)arg;
|
||||
return;
|
||||
}
|
||||
|
||||
WEAK VOID HalAftInterruptHandler(UINT32 arg)
|
||||
{
|
||||
(VOID)arg;
|
||||
return;
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HalInterrupt
|
||||
Description : Hardware interrupt entry function
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
|
||||
{
|
||||
UINT32 hwiIndex;
|
||||
UINT32 intSave;
|
||||
|
||||
#if (LOSCFG_KERNEL_RUNSTOP == 1)
|
||||
SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
|
||||
#endif
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
|
||||
g_intCount++;
|
||||
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
hwiIndex = HwiNumGet();
|
||||
|
||||
OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
|
||||
#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
|
||||
OsCpupIrqStart(hwiIndex);
|
||||
#endif
|
||||
|
||||
HalPreInterruptHandler(hwiIndex);
|
||||
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
|
||||
g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
|
||||
}
|
||||
#else
|
||||
if (g_hwiHandlerForm[hwiIndex] != 0) {
|
||||
g_hwiHandlerForm[hwiIndex]();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (LOSCFG_DEBUG_TOOLS == 1)
|
||||
++g_hwiFormCnt[hwiIndex];
|
||||
#endif
|
||||
|
||||
HalAftInterruptHandler(hwiIndex);
|
||||
|
||||
#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
|
||||
OsCpupIrqEnd(hwiIndex);
|
||||
#endif
|
||||
|
||||
OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
g_intCount--;
|
||||
LOS_IntRestore(intSave);
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchHwiCreate
|
||||
Description : create hardware interrupt
|
||||
Input : hwiNum --- hwi num to create
|
||||
hwiPrio --- priority of the hwi
|
||||
hwiMode --- unused
|
||||
hwiHandler --- hwi handler
|
||||
irqParam --- param of the hwi handler
|
||||
Output : None
|
||||
Return : LOS_OK on success or error code on failure
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
|
||||
HWI_PRIOR_T hwiPrio,
|
||||
HWI_MODE_T hwiMode,
|
||||
HWI_PROC_FUNC hwiHandler,
|
||||
HwiIrqParam *irqParam)
|
||||
{
|
||||
(VOID)hwiMode;
|
||||
UINTPTR intSave;
|
||||
|
||||
if (hwiHandler == NULL) {
|
||||
return OS_ERRNO_HWI_PROC_FUNC_NULL;
|
||||
}
|
||||
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
|
||||
return OS_ERRNO_HWI_ALREADY_CREATED;
|
||||
}
|
||||
|
||||
if (hwiPrio > OS_HWI_PRIO_LOWEST) {
|
||||
return OS_ERRNO_HWI_PRIO_INVALID;
|
||||
}
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
if (irqParam != NULL) {
|
||||
OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
|
||||
} else {
|
||||
OsSetVector(hwiNum, hwiHandler, NULL);
|
||||
}
|
||||
#else
|
||||
(VOID)irqParam;
|
||||
OsSetVector(hwiNum, hwiHandler);
|
||||
#endif
|
||||
|
||||
#if (LOSCFG_DEBUG_TOOLS == 1)
|
||||
if ((irqParam != NULL) && (irqParam->pName != NULL)) {
|
||||
g_hwiFormName[hwiNum + OS_SYS_VECTOR_CNT] = (CHAR *)irqParam->pName;
|
||||
}
|
||||
g_hwiFormCnt[hwiNum + OS_SYS_VECTOR_CNT] = 0;
|
||||
#endif
|
||||
|
||||
HwiUnmask((IRQn_Type)hwiNum);
|
||||
HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
|
||||
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchHwiDelete
|
||||
Description : Delete hardware interrupt
|
||||
Input : hwiNum --- hwi num to delete
|
||||
irqParam --- param of the hwi handler
|
||||
Output : None
|
||||
Return : LOS_OK on success or error code on failure
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
|
||||
{
|
||||
(VOID)irqParam;
|
||||
UINT32 intSave;
|
||||
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_DisableIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
|
||||
g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
|
||||
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
#define FAULT_STATUS_REG_BIT 32
|
||||
#define USGFAULT (1 << 18)
|
||||
#define BUSFAULT (1 << 17)
|
||||
#define MEMFAULT (1 << 16)
|
||||
#define DIV0FAULT (1 << 4)
|
||||
#define HARDFAULT_IRQN (-13)
|
||||
|
||||
ExcInfo g_excInfo = {0};
|
||||
|
||||
UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
|
||||
0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
|
||||
0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
|
||||
0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
|
||||
0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
|
||||
};
|
||||
|
||||
#if (LOSCFG_KERNEL_PRINTF != 0)
|
||||
STATIC VOID OsExcNvicDump(VOID)
|
||||
{
|
||||
#define OS_NR_NVIC_EXC_DUMP_TYPES 7
|
||||
UINT32 *base = NULL;
|
||||
UINT32 len, i, j;
|
||||
UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
|
||||
OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
|
||||
OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
|
||||
};
|
||||
UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
|
||||
OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
|
||||
OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
|
||||
OS_NVIC_INT_CTRL_SIZE
|
||||
};
|
||||
CHAR strRgEnable[] = "enable";
|
||||
CHAR strRgPending[] = "pending";
|
||||
CHAR strRgActive[] = "active";
|
||||
CHAR strRgPriority[] = "priority";
|
||||
CHAR strRgException[] = "exception";
|
||||
CHAR strRgShcsr[] = "shcsr";
|
||||
CHAR strRgIntCtrl[] = "control";
|
||||
CHAR *strRgs[] = {
|
||||
strRgEnable, strRgPending, strRgActive, strRgPriority,
|
||||
strRgException, strRgShcsr, strRgIntCtrl
|
||||
};
|
||||
|
||||
PRINTK("\r\nOS exception NVIC dump:\n");
|
||||
for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
|
||||
base = (UINT32 *)rgNvicBases[i];
|
||||
len = rgNvicLens[i];
|
||||
PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
|
||||
len = (len >> 2); /* 2: Gets the next register offset */
|
||||
for (j = 0; j < len; j++) {
|
||||
PRINTK("0x%x ", *(base + j));
|
||||
if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
|
||||
PRINTK("\n");
|
||||
}
|
||||
}
|
||||
PRINTK("\n");
|
||||
}
|
||||
}
|
||||
|
||||
STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
|
||||
|
||||
PRINTK("Type = %d\n", excInfo->type);
|
||||
PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
|
||||
PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
|
||||
PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
|
||||
}
|
||||
|
||||
STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
PRINTK("Current task info:\n");
|
||||
if (excInfo->phase == OS_EXC_IN_TASK) {
|
||||
LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
|
||||
PRINTK("Task name = %s\n", taskCB->taskName);
|
||||
PRINTK("Task ID = %d\n", taskCB->taskID);
|
||||
PRINTK("Task SP = %p\n", taskCB->stackPointer);
|
||||
PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
|
||||
PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
|
||||
} else if (excInfo->phase == OS_EXC_IN_HWI) {
|
||||
PRINTK("Exception occur in interrupt phase!\n");
|
||||
} else {
|
||||
PRINTK("Exception occur in system init phase!\n");
|
||||
}
|
||||
}
|
||||
|
||||
STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
PRINTK("Exception reg dump:\n");
|
||||
PRINTK("PC = 0x%x\n", excInfo->context->uwPC);
|
||||
PRINTK("LR = 0x%x\n", excInfo->context->uwLR);
|
||||
PRINTK("SP = 0x%x\n", excInfo->context->uwSP);
|
||||
PRINTK("R0 = 0x%x\n", excInfo->context->uwR0);
|
||||
PRINTK("R1 = 0x%x\n", excInfo->context->uwR1);
|
||||
PRINTK("R2 = 0x%x\n", excInfo->context->uwR2);
|
||||
PRINTK("R3 = 0x%x\n", excInfo->context->uwR3);
|
||||
PRINTK("R4 = 0x%x\n", excInfo->context->uwR4);
|
||||
PRINTK("R5 = 0x%x\n", excInfo->context->uwR5);
|
||||
PRINTK("R6 = 0x%x\n", excInfo->context->uwR6);
|
||||
PRINTK("R7 = 0x%x\n", excInfo->context->uwR7);
|
||||
PRINTK("R8 = 0x%x\n", excInfo->context->uwR8);
|
||||
PRINTK("R9 = 0x%x\n", excInfo->context->uwR9);
|
||||
PRINTK("R10 = 0x%x\n", excInfo->context->uwR10);
|
||||
PRINTK("R11 = 0x%x\n", excInfo->context->uwR11);
|
||||
PRINTK("R12 = 0x%x\n", excInfo->context->uwR12);
|
||||
PRINTK("PriMask = 0x%x\n", excInfo->context->uwPriMask);
|
||||
PRINTK("xPSR = 0x%x\n", excInfo->context->uwxPSR);
|
||||
}
|
||||
|
||||
#if (LOSCFG_KERNEL_BACKTRACE == 1)
|
||||
STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
|
||||
UINT32 index;
|
||||
|
||||
OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
|
||||
|
||||
PRINTK("----- backtrace start -----\n");
|
||||
for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
|
||||
if (LR[index] == 0) {
|
||||
break;
|
||||
}
|
||||
PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
|
||||
}
|
||||
PRINTK("----- backtrace end -----\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
STATIC VOID OsExcMemPoolCheckInfo(VOID)
|
||||
{
|
||||
PRINTK("\r\nmemory pools check:\n");
|
||||
#if (LOSCFG_PLATFORM_EXC == 1)
|
||||
MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
|
||||
UINT32 errCnt;
|
||||
UINT32 i;
|
||||
|
||||
(VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
|
||||
|
||||
errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
|
||||
if (errCnt < OS_SYS_MEM_NUM) {
|
||||
errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
|
||||
}
|
||||
|
||||
if (errCnt == 0) {
|
||||
PRINTK("all memory pool check passed!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < errCnt; i++) {
|
||||
PRINTK("pool num = %d\n", i);
|
||||
PRINTK("pool type = %d\n", memExcInfo[i].type);
|
||||
PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
|
||||
PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
|
||||
PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
|
||||
PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
|
||||
PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
|
||||
PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
|
||||
PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
|
||||
}
|
||||
#endif
|
||||
UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
|
||||
if (ret == LOS_OK) {
|
||||
PRINTK("system heap memcheck over, all passed!\n");
|
||||
}
|
||||
|
||||
PRINTK("memory pool check end!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
|
||||
{
|
||||
#if (LOSCFG_KERNEL_PRINTF != 0)
|
||||
PRINTK("*************Exception Information**************\n");
|
||||
OsExcTypeInfo(excInfo);
|
||||
OsExcCurTaskInfo(excInfo);
|
||||
OsExcRegInfo(excInfo);
|
||||
#if (LOSCFG_KERNEL_BACKTRACE == 1)
|
||||
OsExcBackTraceInfo(excInfo);
|
||||
#endif
|
||||
OsGetAllTskInfo();
|
||||
OsExcNvicDump();
|
||||
OsExcMemPoolCheckInfo();
|
||||
#endif
|
||||
}
|
||||
|
||||
LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
|
||||
{
|
||||
UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
|
||||
g_intCount++;
|
||||
g_excInfo.nestCnt++;
|
||||
|
||||
g_excInfo.type = excType & OS_NULL_SHORT;
|
||||
|
||||
if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
|
||||
g_excInfo.faultAddr = faultAddr;
|
||||
} else {
|
||||
g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
|
||||
}
|
||||
if (g_losTask.runTask != NULL) {
|
||||
if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
|
||||
g_excInfo.phase = OS_EXC_IN_HWI;
|
||||
g_excInfo.thrdPid = pid;
|
||||
} else {
|
||||
g_excInfo.phase = OS_EXC_IN_TASK;
|
||||
g_excInfo.thrdPid = g_losTask.runTask->taskID;
|
||||
}
|
||||
} else {
|
||||
g_excInfo.phase = OS_EXC_IN_INIT;
|
||||
g_excInfo.thrdPid = OS_NULL_INT;
|
||||
}
|
||||
if (excType & OS_EXC_FLAG_NO_FLOAT) {
|
||||
g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
|
||||
} else {
|
||||
g_excInfo.context = excBufAddr;
|
||||
}
|
||||
|
||||
OsDoExcHook(EXC_INTERRUPT);
|
||||
OsExcInfoDisplay(&g_excInfo);
|
||||
ArchSysExit();
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HalHwiInit
|
||||
Description : initialization of the hardware interrupt
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
|
||||
{
|
||||
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
|
||||
UINT32 index;
|
||||
g_hwiForm[0] = 0; /* [0] Top of Stack */
|
||||
g_hwiForm[1] = (HWI_PROC_FUNC)Reset_Handler; /* [1] reset */
|
||||
for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
|
||||
g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
|
||||
}
|
||||
/* Exception handler register */
|
||||
g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcNMI;
|
||||
g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcHardFault;
|
||||
g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault;
|
||||
g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcBusFault;
|
||||
g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcUsageFault;
|
||||
g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalSVCHandler;
|
||||
g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalPendSV;
|
||||
g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)SysTick_Handler;
|
||||
|
||||
/* Interrupt vector table location */
|
||||
SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
|
||||
#endif
|
||||
#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
|
||||
NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
|
||||
#endif
|
||||
|
||||
/* Enable USGFAULT, BUSFAULT, MEMFAULT */
|
||||
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
|
||||
/* Enable DIV 0 and unaligned exception */
|
||||
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_timer.h"
|
||||
#include "los_config.h"
|
||||
#include "los_tick.h"
|
||||
#include "los_arch_interrupt.h"
|
||||
#include "los_debug.h"
|
||||
|
||||
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
|
||||
STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
|
||||
STATIC UINT64 SysTickCycleGet(UINT32 *period);
|
||||
STATIC VOID SysTickLock(VOID);
|
||||
STATIC VOID SysTickUnlock(VOID);
|
||||
|
||||
STATIC ArchTickTimer g_archTickTimer = {
|
||||
.freq = 0,
|
||||
.irqNum = SysTick_IRQn,
|
||||
.periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
|
||||
.init = SysTickStart,
|
||||
.getCycle = SysTickCycleGet,
|
||||
.reload = SysTickReload,
|
||||
.lock = SysTickLock,
|
||||
.unlock = SysTickUnlock,
|
||||
.tickHandler = NULL,
|
||||
};
|
||||
|
||||
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
|
||||
{
|
||||
UINT32 ret;
|
||||
ArchTickTimer *tick = &g_archTickTimer;
|
||||
|
||||
tick->freq = OS_SYS_CLOCK;
|
||||
|
||||
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
OsSetVector(tick->irqNum, handler, NULL);
|
||||
#else
|
||||
OsSetVector(tick->irqNum, handler);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
|
||||
if (ret == 1) {
|
||||
return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
|
||||
}
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
|
||||
{
|
||||
if (nextResponseTime > g_archTickTimer.periodMax) {
|
||||
nextResponseTime = g_archTickTimer.periodMax;
|
||||
}
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
NVIC_ClearPendingIRQ(SysTick_IRQn);
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
|
||||
return nextResponseTime;
|
||||
}
|
||||
|
||||
STATIC UINT64 SysTickCycleGet(UINT32 *period)
|
||||
{
|
||||
UINT32 hwCycle = 0;
|
||||
UINTPTR intSave = LOS_IntLock();
|
||||
UINT32 val = SysTick->VAL;
|
||||
*period = SysTick->LOAD;
|
||||
if (val != 0) {
|
||||
hwCycle = *period - val;
|
||||
}
|
||||
LOS_IntRestore(intSave);
|
||||
return (UINT64)hwCycle;
|
||||
}
|
||||
|
||||
STATIC VOID SysTickLock(VOID)
|
||||
{
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
STATIC VOID SysTickUnlock(VOID)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
ArchTickTimer *ArchSysTickTimerGet(VOID)
|
||||
{
|
||||
return &g_archTickTimer;
|
||||
}
|
||||
|
||||
UINT32 ArchEnterSleep(VOID)
|
||||
{
|
||||
__DSB();
|
||||
__WFI();
|
||||
__ISB();
|
||||
return LOS_OK;
|
||||
}
|
|
@ -0,0 +1,46 @@
|
|||
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without modification,
|
||||
# are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
# conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
# of conditions and the following disclaimer in the documentation and/or other materials
|
||||
# provided with the distribution.
|
||||
#
|
||||
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
# to endorse or promote products derived from this software without specific prior written
|
||||
# permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
import("//kernel/liteos_m/liteos.gni")
|
||||
|
||||
module_name = "arch"
|
||||
kernel_module(module_name) {
|
||||
sources = [
|
||||
"los_context.c",
|
||||
"los_dispatch.S",
|
||||
"los_exc.S",
|
||||
"los_interrupt.c",
|
||||
"los_timer.c",
|
||||
]
|
||||
configs += [ "$LITEOSTOPDIR:warn_config" ]
|
||||
}
|
||||
|
||||
config("public") {
|
||||
include_dirs = [ "." ]
|
||||
}
|
|
@ -0,0 +1,296 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_ARCH_ATOMIC_H
|
||||
#define _LOS_ARCH_ATOMIC_H
|
||||
|
||||
#include "los_compiler.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
|
||||
{
|
||||
INT32 val;
|
||||
|
||||
asm volatile("ldrex %0, [%1]\n"
|
||||
: "=&r"(val)
|
||||
: "r"(v)
|
||||
: "cc");
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
|
||||
{
|
||||
UINT32 status;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %0, [%1]\n"
|
||||
"strex %0, %2, [%1]\n"
|
||||
: "=&r"(status)
|
||||
: "r"(v), "r"(setVal)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
}
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
|
||||
{
|
||||
INT32 val;
|
||||
UINT32 status;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %1, [%2]\n"
|
||||
"add %1, %1, %3\n"
|
||||
"strex %0, %1, [%2]"
|
||||
: "=&r"(status), "=&r"(val)
|
||||
: "r"(v), "r"(addVal)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
|
||||
{
|
||||
INT32 val;
|
||||
UINT32 status;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %1, [%2]\n"
|
||||
"sub %1, %1, %3\n"
|
||||
"strex %0, %1, [%2]"
|
||||
: "=&r"(status), "=&r"(val)
|
||||
: "r"(v), "r"(subVal)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
|
||||
{
|
||||
(VOID)ArchAtomicAdd(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
|
||||
{
|
||||
(VOID)ArchAtomicSub(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
|
||||
{
|
||||
return ArchAtomicAdd(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
|
||||
{
|
||||
return ArchAtomicSub(v, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @ingroup los_arch_atomic
|
||||
* @brief Atomic exchange for 32-bit variable.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to implement the atomic exchange for 32-bit variable
|
||||
* and return the previous value of the atomic variable.
|
||||
* @attention
|
||||
* <ul>The pointer v must not be NULL.</ul>
|
||||
*
|
||||
* @param v [IN] The variable pointer.
|
||||
* @param val [IN] The exchange value.
|
||||
*
|
||||
* @retval #INT32 The previous value of the atomic variable
|
||||
* @par Dependency:
|
||||
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see
|
||||
*/
|
||||
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
|
||||
{
|
||||
INT32 prevVal = 0;
|
||||
UINT32 status = 0;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %0, [%2]\n"
|
||||
"strex %1, %3, [%2]"
|
||||
: "=&r"(prevVal), "=&r"(status)
|
||||
: "r"(v), "r"(val)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
|
||||
return prevVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @ingroup los_arch_atomic
|
||||
* @brief Atomic exchange for 32-bit variable with compare.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
|
||||
* @attention
|
||||
* <ul>The pointer v must not be NULL.</ul>
|
||||
*
|
||||
* @param v [IN] The variable pointer.
|
||||
* @param val [IN] The new value.
|
||||
* @param oldVal [IN] The old value.
|
||||
*
|
||||
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
|
||||
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see
|
||||
*/
|
||||
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
|
||||
{
|
||||
INT32 prevVal = 0;
|
||||
UINT32 status = 0;
|
||||
|
||||
do {
|
||||
asm volatile("ldrex %0, [%2]\n"
|
||||
"mov %1, #0\n"
|
||||
"cmp %0, %3\n"
|
||||
"bne 1f\n"
|
||||
"strex %1, %4, [%2]\n"
|
||||
"1:"
|
||||
: "=&r"(prevVal), "=&r"(status)
|
||||
: "r"(v), "r"(oldVal), "r"(val)
|
||||
: "cc");
|
||||
} while (status != 0);
|
||||
|
||||
return prevVal != oldVal;
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
|
||||
{
|
||||
INT64 val;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
val = *v;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
|
||||
{
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
*v = setVal;
|
||||
LOS_IntRestore(intSave);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
|
||||
{
|
||||
INT64 val;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
*v += addVal;
|
||||
val = *v;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
|
||||
{
|
||||
INT64 val;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
*v -= subVal;
|
||||
val = *v;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
|
||||
{
|
||||
(VOID)ArchAtomic64Add(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
|
||||
{
|
||||
return ArchAtomic64Add(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
|
||||
{
|
||||
(VOID)ArchAtomic64Sub(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
|
||||
{
|
||||
return ArchAtomic64Sub(v, 1);
|
||||
}
|
||||
|
||||
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
|
||||
{
|
||||
INT64 prevVal;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
prevVal = *v;
|
||||
*v = val;
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return prevVal;
|
||||
}
|
||||
|
||||
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
|
||||
{
|
||||
INT64 prevVal;
|
||||
UINT32 intSave;
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
prevVal = *v;
|
||||
if (prevVal == oldVal) {
|
||||
*v = val;
|
||||
}
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return prevVal != oldVal;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_ARCH_ATOMIC_H */
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_ARCH_CONTEXT_H
|
||||
#define _LOS_ARCH_CONTEXT_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_compiler.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef struct TagTskContext {
|
||||
UINT32 secureContext;
|
||||
UINT32 stackLmit;
|
||||
UINT32 excReturn;
|
||||
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined(__FPU_USED) && (__FPU_USED == 1U)))
|
||||
UINT32 S16;
|
||||
UINT32 S17;
|
||||
UINT32 S18;
|
||||
UINT32 S19;
|
||||
UINT32 S20;
|
||||
UINT32 S21;
|
||||
UINT32 S22;
|
||||
UINT32 S23;
|
||||
UINT32 S24;
|
||||
UINT32 S25;
|
||||
UINT32 S26;
|
||||
UINT32 S27;
|
||||
UINT32 S28;
|
||||
UINT32 S29;
|
||||
UINT32 S30;
|
||||
UINT32 S31;
|
||||
#endif
|
||||
UINT32 uwR4;
|
||||
UINT32 uwR5;
|
||||
UINT32 uwR6;
|
||||
UINT32 uwR7;
|
||||
UINT32 uwR8;
|
||||
UINT32 uwR9;
|
||||
UINT32 uwR10;
|
||||
UINT32 uwR11;
|
||||
UINT32 uwPriMask;
|
||||
UINT32 uwR0;
|
||||
UINT32 uwR1;
|
||||
UINT32 uwR2;
|
||||
UINT32 uwR3;
|
||||
UINT32 uwR12;
|
||||
UINT32 uwLR;
|
||||
UINT32 uwPC;
|
||||
UINT32 uwxPSR;
|
||||
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined(__FPU_USED) && (__FPU_USED == 1U)))
|
||||
UINT32 S0;
|
||||
UINT32 S1;
|
||||
UINT32 S2;
|
||||
UINT32 S3;
|
||||
UINT32 S4;
|
||||
UINT32 S5;
|
||||
UINT32 S6;
|
||||
UINT32 S7;
|
||||
UINT32 S8;
|
||||
UINT32 S9;
|
||||
UINT32 S10;
|
||||
UINT32 S11;
|
||||
UINT32 S12;
|
||||
UINT32 S13;
|
||||
UINT32 S14;
|
||||
UINT32 S15;
|
||||
UINT32 FPSCR;
|
||||
UINT32 NO_NAME;
|
||||
#endif
|
||||
} TaskContext;
|
||||
|
||||
/**
|
||||
* @ingroup los_config
|
||||
* @brief: Task start running function.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to start a task.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param: None.
|
||||
*
|
||||
* @retval None.
|
||||
*
|
||||
* @par Dependency:
|
||||
* <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalStartToRun(VOID);
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_ARCH_CONTEXT_H */
|
||||
|
|
@ -0,0 +1,684 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_EXC_H
|
||||
#define _LOS_EXC_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_compiler.h"
|
||||
#include "los_interrupt.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Maximum number of used hardware interrupts.
|
||||
*/
|
||||
#ifndef OS_HWI_MAX_NUM
|
||||
#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
|
||||
#endif
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Highest priority of a hardware interrupt.
|
||||
*/
|
||||
#ifndef OS_HWI_PRIO_HIGHEST
|
||||
#define OS_HWI_PRIO_HIGHEST 0
|
||||
#endif
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Lowest priority of a hardware interrupt.
|
||||
*/
|
||||
#ifndef OS_HWI_PRIO_LOWEST
|
||||
#define OS_HWI_PRIO_LOWEST 7
|
||||
#endif
|
||||
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Define the type of a hardware interrupt vector table function.
|
||||
*/
|
||||
typedef VOID (**HWI_VECTOR_FUNC)(void);
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Count of interrupts.
|
||||
*/
|
||||
extern UINT32 g_intCount;
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Count of M-Core system interrupt vector.
|
||||
*/
|
||||
#define OS_SYS_VECTOR_CNT 16
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Count of M-Core interrupt vector.
|
||||
*/
|
||||
#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* AIRCR register priority group parameter .
|
||||
*/
|
||||
#define OS_NVIC_AIRCR_PRIGROUP 7
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Boot interrupt vector table.
|
||||
*/
|
||||
extern UINT32 _BootVectors[];
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Invalid interrupt number.
|
||||
*
|
||||
* Value: 0x02000900
|
||||
*
|
||||
* Solution: Ensure that the interrupt number is valid.
|
||||
* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
|
||||
*/
|
||||
#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Null hardware interrupt handling function.
|
||||
*
|
||||
* Value: 0x02000901
|
||||
*
|
||||
* Solution: Pass in a valid non-null hardware interrupt handling function.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
|
||||
*
|
||||
* Value: 0x02000902
|
||||
*
|
||||
* Solution: Increase the configured maximum number of supported hardware interrupts.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
|
||||
*
|
||||
* Value: 0x02000903
|
||||
*
|
||||
* Solution: Expand the configured memory.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: The interrupt has already been created.
|
||||
*
|
||||
* Value: 0x02000904
|
||||
*
|
||||
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Invalid interrupt priority.
|
||||
*
|
||||
* Value: 0x02000905
|
||||
*
|
||||
* Solution: Ensure that the interrupt priority is valid.
|
||||
* The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
|
||||
*/
|
||||
#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: Incorrect interrupt creation mode.
|
||||
*
|
||||
* Value: 0x02000906
|
||||
*
|
||||
* Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
|
||||
* OS_HWI_MODE_FAST of which the value can be 0 or 1.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
|
||||
*
|
||||
* Value: 0x02000907
|
||||
*
|
||||
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
|
||||
*/
|
||||
#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* SysTick control and status register.
|
||||
*/
|
||||
#define OS_SYSTICK_CONTROL_REG 0xE000E010
|
||||
|
||||
/* *
|
||||
* @ingroup los_hw
|
||||
* SysTick current value register.
|
||||
*/
|
||||
#define OS_SYSTICK_CURRENT_REG 0xE000E018
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt Priority-Level Registers.
|
||||
*/
|
||||
#define OS_NVIC_PRI_BASE 0xE000E400
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt enable register for 0-31.
|
||||
*/
|
||||
#define OS_NVIC_SETENA_BASE 0xE000E100
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* interrupt pending register.
|
||||
*/
|
||||
#define OS_NVIC_SETPEND_BASE 0xE000E200
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt active register.
|
||||
*/
|
||||
#define OS_NVIC_INT_ACT_BASE 0xE000E300
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt disable register for 0-31.
|
||||
*/
|
||||
#define OS_NVIC_CLRENA_BASE 0xE000E180
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt control and status register.
|
||||
*/
|
||||
#define OS_NVIC_INT_CTRL 0xE000ED04
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Vector table offset register.
|
||||
*/
|
||||
#define OS_NVIC_VTOR 0xE000ED08
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Application interrupt and reset control register
|
||||
*/
|
||||
#define OS_NVIC_AIRCR 0xE000ED0C
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* System exception priority register.
|
||||
*/
|
||||
#define OS_NVIC_EXCPRI_BASE 0xE000ED18
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 1 :reset.
|
||||
*/
|
||||
#define OS_EXC_RESET 1
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 2 :Non-Maskable Interrupt.
|
||||
*/
|
||||
#define OS_EXC_NMI 2
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 3 :(hard)fault.
|
||||
*/
|
||||
#define OS_EXC_HARD_FAULT 3
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 4 :MemManage fault.
|
||||
*/
|
||||
#define OS_EXC_MPU_FAULT 4
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 5 :Bus fault.
|
||||
*/
|
||||
#define OS_EXC_BUS_FAULT 5
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 6 :Usage fault.
|
||||
*/
|
||||
#define OS_EXC_USAGE_FAULT 6
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 11 :SVCall.
|
||||
*/
|
||||
#define OS_EXC_SVC_CALL 11
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 12 :Debug monitor.
|
||||
*/
|
||||
#define OS_EXC_DBG_MONITOR 12
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 14 :PendSV.
|
||||
*/
|
||||
#define OS_EXC_PEND_SV 14
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Interrupt No. 15 :SysTick.
|
||||
*/
|
||||
#define OS_EXC_SYS_TICK 15
|
||||
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
|
||||
#else
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
|
||||
#endif
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* @brief: Hardware interrupt entry function.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used as all hardware interrupt handling function entry.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalInterrupt(VOID);
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* @brief: Default vector handling function.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to configure interrupt for null function.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li
|
||||
></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalHwiDefaultHandler(VOID);
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* @brief: Reset the vector table.
|
||||
*
|
||||
* @par Description:
|
||||
* This API is used to reset the vector table.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID Reset_Handler(VOID);
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* @brief: Pended System Call.
|
||||
*
|
||||
* @par Description:
|
||||
* PendSV can be pended and is useful for an OS to pend an exception
|
||||
* so that an action can be performed after other important tasks are completed.
|
||||
*
|
||||
* @attention:
|
||||
* <ul><li>None.</li></ul>
|
||||
*
|
||||
* @param:None.
|
||||
*
|
||||
* @retval:None.
|
||||
* @par Dependency:
|
||||
* <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
|
||||
* @see None.
|
||||
*/
|
||||
extern VOID HalPendSV(VOID);
|
||||
|
||||
|
||||
#define OS_EXC_IN_INIT 0
|
||||
#define OS_EXC_IN_TASK 1
|
||||
#define OS_EXC_IN_HWI 2
|
||||
|
||||
#define OS_EXC_MAX_BUF_LEN 25
|
||||
#define OS_EXC_MAX_NEST_DEPTH 1
|
||||
|
||||
#define OS_NVIC_SHCSR 0xE000ED24
|
||||
#define OS_NVIC_CCR 0xE000ED14
|
||||
|
||||
#define OS_NVIC_INT_ENABLE_SIZE 0x20
|
||||
#define OS_NVIC_INT_PRI_SIZE 0xF0
|
||||
#define OS_NVIC_EXCPRI_SIZE 0xC
|
||||
#define OS_NVIC_INT_CTRL_SIZE 4
|
||||
#define OS_NVIC_SHCSR_SIZE 4
|
||||
|
||||
#define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE
|
||||
#define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE
|
||||
|
||||
#define OS_EXC_FLAG_NO_FLOAT 0x10000000
|
||||
#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
|
||||
#define OS_EXC_FLAG_IN_HWI 0x02
|
||||
|
||||
#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
|
||||
|
||||
#define OS_EXC_EVENT 0x00000001
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* the struct of register files
|
||||
*
|
||||
* description: the register files that saved when exception triggered
|
||||
*
|
||||
* notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
|
||||
*/
|
||||
typedef struct TagExcContext {
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
UINT32 S16;
|
||||
UINT32 S17;
|
||||
UINT32 S18;
|
||||
UINT32 S19;
|
||||
UINT32 S20;
|
||||
UINT32 S21;
|
||||
UINT32 S22;
|
||||
UINT32 S23;
|
||||
UINT32 S24;
|
||||
UINT32 S25;
|
||||
UINT32 S26;
|
||||
UINT32 S27;
|
||||
UINT32 S28;
|
||||
UINT32 S29;
|
||||
UINT32 S30;
|
||||
UINT32 S31;
|
||||
#endif
|
||||
UINT32 uwR4;
|
||||
UINT32 uwR5;
|
||||
UINT32 uwR6;
|
||||
UINT32 uwR7;
|
||||
UINT32 uwR8;
|
||||
UINT32 uwR9;
|
||||
UINT32 uwR10;
|
||||
UINT32 uwR11;
|
||||
UINT32 uwPriMask;
|
||||
/* auto save */
|
||||
UINT32 uwSP;
|
||||
UINT32 uwR0;
|
||||
UINT32 uwR1;
|
||||
UINT32 uwR2;
|
||||
UINT32 uwR3;
|
||||
UINT32 uwR12;
|
||||
UINT32 uwLR;
|
||||
UINT32 uwPC;
|
||||
UINT32 uwxPSR;
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED) && (__FPU_USED== 1U)))
|
||||
UINT32 S0;
|
||||
UINT32 S1;
|
||||
UINT32 S2;
|
||||
UINT32 S3;
|
||||
UINT32 S4;
|
||||
UINT32 S5;
|
||||
UINT32 S6;
|
||||
UINT32 S7;
|
||||
UINT32 S8;
|
||||
UINT32 S9;
|
||||
UINT32 S10;
|
||||
UINT32 S11;
|
||||
UINT32 S12;
|
||||
UINT32 S13;
|
||||
UINT32 S14;
|
||||
UINT32 S15;
|
||||
UINT32 FPSCR;
|
||||
UINT32 NO_NAME;
|
||||
#endif
|
||||
}EXC_CONTEXT_S;
|
||||
|
||||
typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
|
||||
VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
|
||||
|
||||
VOID HalExcNMI(VOID);
|
||||
VOID HalExcHardFault(VOID);
|
||||
VOID HalExcMemFault(VOID);
|
||||
VOID HalExcBusFault(VOID);
|
||||
VOID HalExcUsageFault(VOID);
|
||||
VOID HalSVCHandler(VOID);
|
||||
VOID HalHwiInit(VOID);
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the bus status register was being pushed.
|
||||
*/
|
||||
#define OS_EXC_BF_STKERR 1
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the bus status register was out of the stack.
|
||||
*/
|
||||
#define OS_EXC_BF_UNSTKERR 2
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Bus status register imprecise data access violation.
|
||||
*/
|
||||
#define OS_EXC_BF_IMPRECISERR 3
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Bus status register exact data access violation.
|
||||
*/
|
||||
#define OS_EXC_BF_PRECISERR 4
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Bus status register access violation while pointing.
|
||||
*/
|
||||
#define OS_EXC_BF_IBUSERR 5
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the memory management status register was being pushed.
|
||||
*/
|
||||
#define OS_EXC_MF_MSTKERR 6
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
|
||||
*/
|
||||
#define OS_EXC_MF_MUNSTKERR 7
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Memory management status register data access violation.
|
||||
*/
|
||||
#define OS_EXC_MF_DACCVIOL 8
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Memory management status register access violation.
|
||||
*/
|
||||
#define OS_EXC_MF_IACCVIOL 9
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
|
||||
*/
|
||||
#define OS_EXC_UF_DIVBYZERO 10
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Usage error, error caused by unaligned access.
|
||||
*/
|
||||
#define OS_EXC_UF_UNALIGNED 11
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
|
||||
*/
|
||||
#define OS_EXC_UF_NOCP 12
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
|
||||
*/
|
||||
#define OS_EXC_UF_INVPC 13
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
|
||||
*/
|
||||
#define OS_EXC_UF_INVSTATE 14
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
|
||||
*/
|
||||
#define OS_EXC_UF_UNDEFINSTR 15
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: NMI
|
||||
*/
|
||||
|
||||
#define OS_EXC_CAUSE_NMI 16
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: hard fault
|
||||
*/
|
||||
#define OS_EXC_CAUSE_HARDFAULT 17
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: The task handler exits.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_TASK_EXIT 18
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: A fatal error.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_FATAL_ERR 19
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: Hard Fault caused by a debug event.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_DEBUGEVT 20
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
|
||||
*/
|
||||
#define OS_EXC_CAUSE_VECTBL 21
|
||||
|
||||
/**
|
||||
* @ingroup los_exc
|
||||
* Exception information structure
|
||||
*
|
||||
* Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
|
||||
*
|
||||
*/
|
||||
typedef struct TagExcInfo {
|
||||
/**< Exception occurrence phase: 0 means that an exception occurs in initialization,
|
||||
* 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
|
||||
UINT16 phase;
|
||||
/**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
|
||||
UINT16 type;
|
||||
/**< If the exact address access error indicates the wrong access address when the exception occurred */
|
||||
UINT32 faultAddr;
|
||||
/**< An exception occurs in an interrupt, indicating the interrupt number.
|
||||
* An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
|
||||
UINT32 thrdPid;
|
||||
/**< Number of nested exceptions. Currently only registered hook functions are supported
|
||||
* when an exception is entered for the first time */
|
||||
UINT16 nestCnt;
|
||||
/**< reserve */
|
||||
UINT16 reserved;
|
||||
/**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
|
||||
EXC_CONTEXT_S *context;
|
||||
} ExcInfo;
|
||||
|
||||
extern UINT32 g_curNestCount;
|
||||
extern UINT32 g_intCount;
|
||||
extern UINT8 g_uwExcTbl[32];
|
||||
extern ExcInfo g_excInfo;
|
||||
|
||||
#define MAX_INT_INFO_SIZE (8 + 0x164)
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_EXC_H */
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_ARCH_TIMER_H
|
||||
#define _LOS_ARCH_TIMER_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_compiler.h"
|
||||
#include "los_timer.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _LOS_ARCH_TIMER_H */
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_context.h"
|
||||
#include "securec.h"
|
||||
#include "los_arch_context.h"
|
||||
#include "los_arch_interrupt.h"
|
||||
#include "los_task.h"
|
||||
#include "los_sched.h"
|
||||
#include "los_interrupt.h"
|
||||
#include "los_debug.h"
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchInit
|
||||
Description : arch init function
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
|
||||
{
|
||||
HalHwiInit();
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchSysExit
|
||||
Description : Task exit function
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
|
||||
{
|
||||
LOS_IntLock();
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchTskStackInit
|
||||
Description : Task stack initialization function
|
||||
Input : taskID --- TaskID
|
||||
stackSize --- Total size of the stack
|
||||
topStack --- Top of task's stack
|
||||
Output : None
|
||||
Return : Context pointer
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
|
||||
{
|
||||
TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
|
||||
|
||||
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined(__FPU_USED) && (__FPU_USED == 1U)))
|
||||
context->S16 = 0xAA000010;
|
||||
context->S17 = 0xAA000011;
|
||||
context->S18 = 0xAA000012;
|
||||
context->S19 = 0xAA000013;
|
||||
context->S20 = 0xAA000014;
|
||||
context->S21 = 0xAA000015;
|
||||
context->S22 = 0xAA000016;
|
||||
context->S23 = 0xAA000017;
|
||||
context->S24 = 0xAA000018;
|
||||
context->S25 = 0xAA000019;
|
||||
context->S26 = 0xAA00001A;
|
||||
context->S27 = 0xAA00001B;
|
||||
context->S28 = 0xAA00001C;
|
||||
context->S29 = 0xAA00001D;
|
||||
context->S30 = 0xAA00001E;
|
||||
context->S31 = 0xAA00001F;
|
||||
context->S0 = 0xAA000000;
|
||||
context->S1 = 0xAA000001;
|
||||
context->S2 = 0xAA000002;
|
||||
context->S3 = 0xAA000003;
|
||||
context->S4 = 0xAA000004;
|
||||
context->S5 = 0xAA000005;
|
||||
context->S6 = 0xAA000006;
|
||||
context->S7 = 0xAA000007;
|
||||
context->S8 = 0xAA000008;
|
||||
context->S9 = 0xAA000009;
|
||||
context->S10 = 0xAA00000A;
|
||||
context->S11 = 0xAA00000B;
|
||||
context->S12 = 0xAA00000C;
|
||||
context->S13 = 0xAA00000D;
|
||||
context->S14 = 0xAA00000E;
|
||||
context->S15 = 0xAA00000F;
|
||||
context->FPSCR = 0x00000000;
|
||||
context->NO_NAME = 0xAA000011;
|
||||
#endif
|
||||
|
||||
context->secureContext = 0UL;
|
||||
context->stackLmit = (UINT32)topStack;
|
||||
context->excReturn = 0xFFFFFFBC;
|
||||
|
||||
context->uwR4 = 0x04040404L;
|
||||
context->uwR5 = 0x05050505L;
|
||||
context->uwR6 = 0x06060606L;
|
||||
context->uwR7 = 0x07070707L;
|
||||
context->uwR8 = 0x08080808L;
|
||||
context->uwR9 = 0x09090909L;
|
||||
context->uwR10 = 0x10101010L;
|
||||
context->uwR11 = 0x11111111L;
|
||||
context->uwPriMask = 0;
|
||||
context->uwR0 = taskID;
|
||||
context->uwR1 = 0x01010101L;
|
||||
context->uwR2 = 0x02020202L;
|
||||
context->uwR3 = 0x03030303L;
|
||||
context->uwR12 = 0x12121212L;
|
||||
context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
|
||||
context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
|
||||
context->uwxPSR = 0x01000000L;
|
||||
|
||||
return (VOID *)context;
|
||||
}
|
||||
|
||||
VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
|
||||
{
|
||||
TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
|
||||
(VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
|
||||
|
||||
context->uwR0 = param;
|
||||
context->uwPC = sigHandler;
|
||||
context->stackLimit = (UINT32)stackTop;
|
||||
context->excReturn = 0xFFFFFFBC;
|
||||
context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
|
||||
|
||||
return (VOID *)context;
|
||||
}
|
||||
|
||||
LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
|
||||
{
|
||||
(VOID)LOS_IntLock();
|
||||
OsSchedStart();
|
||||
HalStartToRun();
|
||||
return LOS_OK; /* never return */
|
||||
}
|
|
@ -0,0 +1,237 @@
|
|||
;
|
||||
; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without modification,
|
||||
; are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
; conditions and the following disclaimer.
|
||||
;
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
; of conditions and the following disclaimer in the documentation and/or other materials
|
||||
; provided with the distribution.
|
||||
;
|
||||
; 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without specific prior written
|
||||
; permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
|
||||
PRESERVE8
|
||||
|
||||
EXPORT ArchIntLock
|
||||
EXPORT ArchIntUnLock
|
||||
EXPORT ArchIntRestore
|
||||
EXPORT ArchTaskSchedule
|
||||
EXPORT HalPendSV
|
||||
EXPORT HalSVCHandler
|
||||
EXPORT HalStartFirstTask
|
||||
EXPORT HalSVCStartSchedule
|
||||
EXPORT HalSVCSecureContextAlloc
|
||||
EXPORT HalSVCSecureContextFree
|
||||
IMPORT OsSignalTaskContextRestore
|
||||
IMPORT OsSchedTaskSwitch
|
||||
IMPORT g_losTask
|
||||
|
||||
EXTERN HalSecureSVCHandler
|
||||
EXTERN HalSecureContextSave
|
||||
EXTERN HalSecureContextLoad
|
||||
EXTERN g_secureContext
|
||||
|
||||
OS_FPU_CPACR EQU 0xE000ED88
|
||||
OS_FPU_CPACR_ENABLE EQU 0x00F00000
|
||||
OS_NVIC_INT_CTRL EQU 0xE000ED04
|
||||
OS_NVIC_SYSPRI2 EQU 0xE000ED20
|
||||
OS_NVIC_PENDSV_PRI EQU 0xF0F00000
|
||||
OS_NVIC_PENDSVSET EQU 0x10000000
|
||||
OS_TASK_STATUS_RUNNING EQU 0x0010
|
||||
|
||||
SECTION .text:CODE(2)
|
||||
THUMB
|
||||
REQUIRE8
|
||||
|
||||
MACRO SIGNAL_CONTEXT_RESTORE
|
||||
PUSH {R12, LR}
|
||||
BLX OsSignalTaskContextRestore
|
||||
POP {R12, LR}
|
||||
CMP R0, #0
|
||||
MOV R1, R0
|
||||
BNE SignalContextRestore
|
||||
ENDM
|
||||
|
||||
HalStartFirstTask
|
||||
MOV R0, #2
|
||||
MSR CONTROL, R0
|
||||
|
||||
LDR R1, =g_losTask
|
||||
LDR R0, [R1, #4]
|
||||
|
||||
LDR R12, [R0] /* Get the stack pointer of the current task. */
|
||||
LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 = excReturn.*/
|
||||
LDR R4, =g_secureContext
|
||||
STR R1, [R4] /* Set the secureContext to g_secureContext handler. */
|
||||
MSR PSPLIM, R2 /* Set the stackLmit for the PSPLIM about current task. */
|
||||
ISB
|
||||
|
||||
LDR.W R1, =OS_FPU_CPACR
|
||||
LDR R1, [R1]
|
||||
AND R1, R1, #OS_FPU_CPACR_ENABLE
|
||||
CMP R1, #OS_FPU_CPACR_ENABLE
|
||||
BNE __DisabledFPU1
|
||||
ADD R12, R12, #64
|
||||
VPUSH S0;
|
||||
VPOP S0;
|
||||
|
||||
__DisabledFPU1
|
||||
ADD R12, R12, #36
|
||||
MSR PSP, R12
|
||||
CPSIE I
|
||||
BX R3
|
||||
|
||||
ArchIntLock
|
||||
MRS R0, PRIMASK
|
||||
CPSID I
|
||||
BX LR
|
||||
|
||||
ArchIntUnLock
|
||||
MRS R0, PRIMASK
|
||||
CPSIE I
|
||||
BX LR
|
||||
|
||||
ArchIntRestore
|
||||
MSR PRIMASK, R0
|
||||
BX LR
|
||||
|
||||
ArchTaskSchedule
|
||||
LDR R0, =OS_NVIC_INT_CTRL
|
||||
LDR R1, =OS_NVIC_PENDSVSET
|
||||
STR R1, [R0]
|
||||
DSB
|
||||
ISB
|
||||
BX LR
|
||||
|
||||
HalPendSV
|
||||
MRS R12, PRIMASK
|
||||
CPSID I
|
||||
|
||||
HalTaskSwitch
|
||||
SIGNAL_CONTEXT_RESTORE
|
||||
|
||||
PUSH {R12, LR}
|
||||
BLX OsSchedTaskSwitch
|
||||
POP {R12, LR}
|
||||
CMP R0, #0
|
||||
MOV R0, LR
|
||||
BNE TaskContextSwitch
|
||||
MSR PRIMASK, R12
|
||||
BX LR
|
||||
|
||||
TaskContextSwitch
|
||||
MOV LR, R0
|
||||
MRS R0, PSP
|
||||
|
||||
LDR R2, =g_secureContext
|
||||
LDR R1, [R2]
|
||||
CBZ R1, __SaveNSContext /* If the g_secureContext is NULL, so no secure context to save. */
|
||||
|
||||
PUSH {R0-R1, R12, R14} /* Store registers, include LR, PRIMASK. */
|
||||
BL HalSecureContextSave /* Store the secure context to g_secureContext->curStackPointer. */
|
||||
POP {R0-R3}
|
||||
MOV LR, R3
|
||||
MOV R12, R2 /* R2 = PRIMASK. */
|
||||
|
||||
__SaveNSContext
|
||||
STMFD R0!, {R4-R12}
|
||||
LDR.W R3, =OS_FPU_CPACR
|
||||
LDR R3, [R3]
|
||||
AND R3, R3, #OS_FPU_CPACR_ENABLE
|
||||
CMP R3, #OS_FPU_CPACR_ENABLE
|
||||
BNE __DisabledFPU2
|
||||
VSTMDB R0!, {D8-D15}
|
||||
|
||||
__DisabledFPU2
|
||||
LDR R5, =g_losTask
|
||||
LDR R6, [R5] /* Get the stackPointer handler of the current task. */
|
||||
SUBS R0, R0, #12
|
||||
STR R0, [R6] /* Save the new top of stack in TCB. */
|
||||
MRS R2, PSPLIM
|
||||
MOV R3, LR
|
||||
STMIA R0!, {R1, R2-R3} /* Store g_secureContext, PSPLIM and LR on the stack of current task. */
|
||||
|
||||
LDR R0, [R5, #4]
|
||||
STR R0, [R5]
|
||||
LDR R1, [R0]
|
||||
|
||||
SignalContextRestore
|
||||
LDMIA R1!, {R0, R2-R3} /* Restore secureContext, PSPLIM and LR from the current task stack. */
|
||||
MSR PSPLIM, R2
|
||||
MOV LR, R3
|
||||
LDR R2, =g_secureContext
|
||||
STR R0, [R2] /* Set the secureContext of the new task to g_secureContext. */
|
||||
CBZ R0, __RestoreNSContext /* If there is no secure context for the new task, so restore from the non-secure context. */
|
||||
PUSH {R1, R3}
|
||||
BL HalSecureContextLoad /* Restore the secure context. */
|
||||
POP {R1, R3}
|
||||
MOV LR, R3
|
||||
|
||||
__RestoreNSContext
|
||||
LDR.W R3, =OS_FPU_CPACR
|
||||
LDR R3, [R3]
|
||||
AND R3, R3, #OS_FPU_CPACR_ENABLE
|
||||
CMP R3, #OS_FPU_CPACR_ENABLE
|
||||
BNE __DisabledFPU3
|
||||
VLDMIA R1!, {D8-D15}
|
||||
|
||||
__DisabledFPU3
|
||||
LDMFD R1!, {R4-R12}
|
||||
MSR PSP, R1
|
||||
|
||||
MSR PRIMASK, R12
|
||||
BX LR
|
||||
|
||||
HalSVCStartSchedule
|
||||
LDR R4, =OS_NVIC_SYSPRI2
|
||||
LDR R5, =OS_NVIC_PENDSV_PRI
|
||||
STR R5, [R4]
|
||||
CPSIE I
|
||||
DSB
|
||||
ISB
|
||||
SVC 2
|
||||
|
||||
HalSVCSecureContextAlloc
|
||||
SVC 0
|
||||
BX LR
|
||||
|
||||
HalSVCSecureContextFree
|
||||
SVC 1
|
||||
BX LR
|
||||
|
||||
HalSVCHandler
|
||||
TST LR, #0x04
|
||||
ITE EQ
|
||||
MRSEQ R1, MSP
|
||||
MRSNE R1, PSP
|
||||
LDR R0, [R1, #24]
|
||||
LDRB R0, [R0, #-2] /* Get the SVC number. */
|
||||
|
||||
PUSH {LR}
|
||||
MOV R2, R1 /* Get the stack for R2. */
|
||||
LDMFD R2!, {R1} /* Get the input arg for HalSecureSVCHandler. */
|
||||
STMFD R2!, {R1}
|
||||
BL HalSecureSVCHandler
|
||||
POP {LR}
|
||||
BX LR
|
||||
|
||||
END
|
|
@ -0,0 +1,274 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
PRESERVE8
|
||||
SECTION .text:CODE(2)
|
||||
THUMB
|
||||
|
||||
EXPORT HalExcNMI
|
||||
EXPORT HalExcHardFault
|
||||
EXPORT HalExcMemFault
|
||||
EXPORT HalExcBusFault
|
||||
EXPORT HalExcUsageFault
|
||||
|
||||
IMPORT HalExcHandleEntry
|
||||
IMPORT g_uwExcTbl
|
||||
IMPORT g_taskScheduled
|
||||
|
||||
OS_FLG_BGD_ACTIVE EQU 0x0002
|
||||
|
||||
OS_EXC_CAUSE_NMI EQU 16
|
||||
OS_EXC_CAUSE_HARDFAULT EQU 17
|
||||
|
||||
HF_DEBUGEVT EQU 20
|
||||
HF_VECTBL EQU 21
|
||||
|
||||
FLAG_ADDR_VALID EQU 0x10000
|
||||
FLAG_HWI_ACTIVE EQU 0x20000
|
||||
FLAG_NO_FLOAT EQU 0x10000000
|
||||
|
||||
OS_NVIC_FSR EQU 0xE000ED28 ;include BusFault/MemFault/UsageFault State Register
|
||||
OS_NVIC_HFSR EQU 0xE000ED2C ;HardFault State Register
|
||||
OS_NVIC_BFAR EQU 0xE000ED38
|
||||
OS_NVIC_MMAR EQU 0xE000ED34
|
||||
OS_NVIC_ACT_BASE EQU 0xE000E300
|
||||
OS_NVIC_SHCSRS EQU 0xE000ED24
|
||||
OS_NVIC_SHCSR_MASK EQU 0xC00
|
||||
|
||||
HalExcNMI
|
||||
MOV R0, #OS_EXC_CAUSE_NMI
|
||||
MOV R1, #0
|
||||
B osExcDispatch
|
||||
|
||||
HalExcHardFault
|
||||
MOV R0, #OS_EXC_CAUSE_HARDFAULT
|
||||
LDR R2, =OS_NVIC_HFSR
|
||||
LDR R2, [R2]
|
||||
|
||||
MOV R1, #HF_DEBUGEVT
|
||||
ORR R0, R0, R1, LSL #0x8
|
||||
TST R2, #0x80000000
|
||||
BNE osExcDispatch ; DEBUGEVT
|
||||
|
||||
AND R0, R0 , #0x000000FF
|
||||
MOV R1, #HF_VECTBL
|
||||
ORR R0, R0, R1, LSL #0x8
|
||||
TST R2, #0x00000002
|
||||
BNE osExcDispatch ; VECTBL
|
||||
|
||||
;if not DEBUGEVT and VECTBL then is FORCED
|
||||
AND R0, R0, #0x000000FF
|
||||
|
||||
LDR R2, =OS_NVIC_FSR
|
||||
LDR R2, [R2]
|
||||
|
||||
TST R2, #0x8000 ; BFARVALID
|
||||
BNE _HFBusFault ; BusFault
|
||||
|
||||
TST R2, #0x80 ; MMARVALID
|
||||
BNE _HFMemFault ; MemFault
|
||||
|
||||
MOV R12,#0
|
||||
B osHFExcCommonBMU
|
||||
|
||||
_HFBusFault
|
||||
LDR R1, =OS_NVIC_BFAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
B osHFExcCommonBMU
|
||||
|
||||
_HFMemFault
|
||||
LDR R1, =OS_NVIC_MMAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
|
||||
osHFExcCommonBMU
|
||||
CLZ R2, R2
|
||||
LDR R3, =g_uwExcTbl
|
||||
ADD R3, R3, R2
|
||||
LDRB R2, [R3]
|
||||
ORR R0, R0, R2, LSL #0x8
|
||||
ORR R0, R0 ,R12
|
||||
B osExcDispatch
|
||||
|
||||
HalExcBusFault
|
||||
LDR R0, =OS_NVIC_FSR
|
||||
LDR R0, [R0]
|
||||
|
||||
TST R0, #0x8000 ; BFARVALID
|
||||
BEQ _ExcBusNoADDR
|
||||
LDR R1, =OS_NVIC_BFAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
AND R0, R0, #0x1F00
|
||||
|
||||
B osExcCommonBMU
|
||||
|
||||
_ExcBusNoADDR
|
||||
MOV R12,#0
|
||||
B osExcCommonBMU
|
||||
|
||||
HalExcMemFault
|
||||
LDR R0, =OS_NVIC_FSR
|
||||
LDR R0, [R0]
|
||||
|
||||
TST R0, #0x80 ; MMARVALID
|
||||
BEQ _ExcMemNoADDR
|
||||
LDR R1, =OS_NVIC_MMAR
|
||||
LDR R1, [R1]
|
||||
MOV R12, #FLAG_ADDR_VALID
|
||||
AND R0, R0, #0x1B
|
||||
|
||||
B osExcCommonBMU
|
||||
|
||||
_ExcMemNoADDR
|
||||
MOV R12,#0
|
||||
B osExcCommonBMU
|
||||
|
||||
HalExcUsageFault
|
||||
LDR R0, =OS_NVIC_FSR
|
||||
LDR R0, [R0]
|
||||
|
||||
MOV R1, #0x030F
|
||||
LSL R1, R1, #16
|
||||
AND R0, R0, R1
|
||||
MOV R12, #0
|
||||
|
||||
osExcCommonBMU
|
||||
CLZ R0, R0
|
||||
LDR R3, =g_uwExcTbl
|
||||
ADD R3, R3, R0
|
||||
LDRB R0, [R3]
|
||||
ORR R0, R0, R12
|
||||
|
||||
; R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid), R1 -- EXCADDR
|
||||
osExcDispatch
|
||||
LDR R2, =OS_NVIC_ACT_BASE
|
||||
MOV R12, #8 ; R12 is hwi check loop counter
|
||||
|
||||
_hwiActiveCheck
|
||||
LDR R3, [R2] ; R3 store active hwi register when exc
|
||||
CMP R3, #0
|
||||
BEQ _hwiActiveCheckNext
|
||||
|
||||
; exc occurred in IRQ
|
||||
ORR R0, R0, #FLAG_HWI_ACTIVE
|
||||
RBIT R2, R3
|
||||
CLZ R2, R2
|
||||
AND R12, R12, #1
|
||||
ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as pid
|
||||
|
||||
_ExcInMSP
|
||||
CMP LR, #0xFFFFFFE9
|
||||
BNE _NoFloatInMsp
|
||||
ADD R3, R13, #104
|
||||
PUSH {R3}
|
||||
MRS R12, PRIMASK ; store message-->exc: disable int?
|
||||
PUSH {R4-R12} ; store message-->exc: {R4-R12}
|
||||
VPUSH {D8-D15}
|
||||
B _handleEntry
|
||||
|
||||
_NoFloatInMsp
|
||||
ADD R3, R13, #32
|
||||
PUSH {R3} ; save IRQ SP ; store message-->exc: MSP(R13)
|
||||
|
||||
MRS R12, PRIMASK ; store message-->exc: disable int?
|
||||
PUSH {R4-R12} ; store message-->exc: {R4-R12}
|
||||
ORR R0, R0, #FLAG_NO_FLOAT
|
||||
B _handleEntry
|
||||
|
||||
_hwiActiveCheckNext
|
||||
ADD R2, R2, #4 ; next NVIC ACT ADDR
|
||||
SUBS R12, R12, #1
|
||||
BNE _hwiActiveCheck
|
||||
|
||||
;/*NMI interrupt excption*/
|
||||
LDR R2, =OS_NVIC_SHCSRS
|
||||
LDRH R2,[R2]
|
||||
LDR R3,=OS_NVIC_SHCSR_MASK
|
||||
AND R2, R2,R3
|
||||
CMP R2,#0
|
||||
BNE _ExcInMSP
|
||||
; exc occurred in Task or Init or exc
|
||||
; reserved for register info from task stack
|
||||
|
||||
LDR R2, =g_taskScheduled
|
||||
LDR R2, [R2]
|
||||
TST R2, #1 ; OS_FLG_BGD_ACTIVE
|
||||
BEQ _ExcInMSP ; if exc occurred in Init then branch
|
||||
|
||||
|
||||
CMP LR, #0xFFFFFFED ;auto push floating registers
|
||||
BNE _NoFloatInPsp
|
||||
|
||||
; exc occurred in Task
|
||||
MOV R2, R13
|
||||
SUB R13, #96 ; add 8 Bytes reg(for STMFD)
|
||||
|
||||
MRS R3, PSP
|
||||
ADD R12, R3, #104
|
||||
PUSH {R12} ; save task SP
|
||||
|
||||
MRS R12, PRIMASK
|
||||
PUSH {R4-R12}
|
||||
VPUSH {D8-D15}
|
||||
|
||||
; copy auto saved task register
|
||||
|
||||
LDMFD R3!, {R4-R11} ; R4-R11 store PSP reg(auto push when exc in task)
|
||||
VLDMIA R3!, {D8-D15}
|
||||
VSTMDB R2!, {D8-D15}
|
||||
STMFD R2!, {R4-R11}
|
||||
B _handleEntry
|
||||
|
||||
_NoFloatInPsp
|
||||
MOV R2, R13 ;no auto push floating registers
|
||||
SUB R13, #32 ; add 8 Bytes reg(for STMFD)
|
||||
|
||||
MRS R3, PSP
|
||||
ADD R12, R3, #32
|
||||
PUSH {R12} ; save task SP
|
||||
|
||||
MRS R12, PRIMASK
|
||||
PUSH {R4-R12}
|
||||
|
||||
LDMFD R3, {R4-R11} ; R4-R11 store PSP reg(auto push when exc in task)
|
||||
STMFD R2!, {R4-R11}
|
||||
ORR R0, R0, #FLAG_NO_FLOAT
|
||||
|
||||
_handleEntry
|
||||
MOV R3, R13 ; R13:the 4th param
|
||||
CPSID I
|
||||
CPSID F
|
||||
B HalExcHandleEntry
|
||||
|
||||
NOP
|
||||
END
|
|
@ -0,0 +1,654 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_interrupt.h"
|
||||
#include "securec.h"
|
||||
#include <stdarg.h>
|
||||
#include "los_arch_interrupt.h"
|
||||
#include "los_context.h"
|
||||
#include "los_debug.h"
|
||||
#include "los_hook.h"
|
||||
#include "los_task.h"
|
||||
#include "los_sched.h"
|
||||
#include "los_memory.h"
|
||||
#include "los_membox.h"
|
||||
#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
|
||||
#include "los_cpup.h"
|
||||
#endif
|
||||
|
||||
/*lint -save -e40 -e522 -e533*/
|
||||
UINT32 g_intCount = 0;
|
||||
|
||||
/*lint -restore*/
|
||||
#pragma location = ".data.vector"
|
||||
#pragma data_alignment = LOSCFG_ARCH_HWI_VECTOR_ALIGN
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* hardware interrupt form mapping handling function array.
|
||||
*/
|
||||
STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
|
||||
|
||||
#if (LOSCFG_DEBUG_TOOLS == 1)
|
||||
STATIC UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM] = {0};
|
||||
STATIC CHAR *g_hwiFormName[OS_HWI_MAX_NUM] = {0};
|
||||
|
||||
UINT32 OsGetHwiFormCnt(UINT32 index)
|
||||
{
|
||||
return g_hwiFormCnt[index];
|
||||
}
|
||||
|
||||
CHAR *OsGetHwiFormName(UINT32 index)
|
||||
{
|
||||
return g_hwiFormName[index];
|
||||
}
|
||||
|
||||
BOOL OsGetHwiCreated(UINT32 index)
|
||||
{
|
||||
if (g_hwiForm[index] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
|
||||
typedef struct {
|
||||
HWI_PROC_FUNC pfnHandler;
|
||||
VOID *pParm;
|
||||
} HWI_HANDLER_FUNC;
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* hardware interrupt handler form mapping handling function array.
|
||||
*/
|
||||
STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
|
||||
{
|
||||
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
|
||||
g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
|
||||
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
|
||||
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* hardware interrupt handler form mapping handling function array.
|
||||
*/
|
||||
STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
|
||||
|
||||
/* *
|
||||
* @ingroup los_hwi
|
||||
* Set interrupt vector table.
|
||||
*/
|
||||
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
|
||||
{
|
||||
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
|
||||
g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
|
||||
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
WEAK VOID SysTick_Handler(VOID)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HwiNumGet
|
||||
Description : Get an interrupt number
|
||||
Input : None
|
||||
Output : None
|
||||
Return : Interrupt Indexes number
|
||||
**************************************************************************** */
|
||||
STATIC UINT32 HwiNumGet(VOID)
|
||||
{
|
||||
return __get_IPSR();
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_EnableIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_DisableIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
if (priority > OS_HWI_PRIO_LOWEST) {
|
||||
return OS_ERRNO_HWI_PRIO_INVALID;
|
||||
}
|
||||
|
||||
NVIC_SetPriority((IRQn_Type)hwiNum, priority);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
|
||||
{
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
HwiControllerOps g_archHwiOps = {
|
||||
.enableIrq = HwiUnmask,
|
||||
.disableIrq = HwiMask,
|
||||
.setIrqPriority = HwiSetPriority,
|
||||
.getCurIrqNum = HwiNumGet,
|
||||
.triggerIrq = HwiPending,
|
||||
.clearIrq = HwiClear,
|
||||
};
|
||||
|
||||
inline UINT32 ArchIsIntActive(VOID)
|
||||
{
|
||||
return (g_intCount > 0);
|
||||
}
|
||||
/* ****************************************************************************
|
||||
Function : HalHwiDefaultHandler
|
||||
Description : default handler of the hardware interrupt
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
/*lint -e529*/
|
||||
LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
|
||||
{
|
||||
PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
WEAK VOID HalPreInterruptHandler(UINT32 arg)
|
||||
{
|
||||
(VOID)arg;
|
||||
return;
|
||||
}
|
||||
|
||||
WEAK VOID HalAftInterruptHandler(UINT32 arg)
|
||||
{
|
||||
(VOID)arg;
|
||||
return;
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HalInterrupt
|
||||
Description : Hardware interrupt entry function
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
|
||||
{
|
||||
UINT32 hwiIndex;
|
||||
UINT32 intSave;
|
||||
|
||||
#if (LOSCFG_KERNEL_RUNSTOP == 1)
|
||||
SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
|
||||
#endif
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
|
||||
g_intCount++;
|
||||
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
hwiIndex = HwiNumGet();
|
||||
|
||||
OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
|
||||
#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
|
||||
OsCpupIrqStart(hwiIndex);
|
||||
#endif
|
||||
|
||||
HalPreInterruptHandler(hwiIndex);
|
||||
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
|
||||
g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
|
||||
}
|
||||
#else
|
||||
if (g_hwiHandlerForm[hwiIndex] != 0) {
|
||||
g_hwiHandlerForm[hwiIndex]();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (LOSCFG_DEBUG_TOOLS == 1)
|
||||
++g_hwiFormCnt[hwiIndex];
|
||||
#endif
|
||||
|
||||
HalAftInterruptHandler(hwiIndex);
|
||||
|
||||
#if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
|
||||
OsCpupIrqEnd(hwiIndex);
|
||||
#endif
|
||||
|
||||
OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
g_intCount--;
|
||||
LOS_IntRestore(intSave);
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchHwiCreate
|
||||
Description : create hardware interrupt
|
||||
Input : hwiNum --- hwi num to create
|
||||
hwiPrio --- priority of the hwi
|
||||
hwiMode --- unused
|
||||
hwiHandler --- hwi handler
|
||||
irqParam --- param of the hwi handler
|
||||
Output : None
|
||||
Return : LOS_OK on success or error code on failure
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
|
||||
HWI_PRIOR_T hwiPrio,
|
||||
HWI_MODE_T hwiMode,
|
||||
HWI_PROC_FUNC hwiHandler,
|
||||
HwiIrqParam *irqParam)
|
||||
{
|
||||
(VOID)hwiMode;
|
||||
UINTPTR intSave;
|
||||
|
||||
if (hwiHandler == NULL) {
|
||||
return OS_ERRNO_HWI_PROC_FUNC_NULL;
|
||||
}
|
||||
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
|
||||
return OS_ERRNO_HWI_ALREADY_CREATED;
|
||||
}
|
||||
|
||||
if (hwiPrio > OS_HWI_PRIO_LOWEST) {
|
||||
return OS_ERRNO_HWI_PRIO_INVALID;
|
||||
}
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
if (irqParam != NULL) {
|
||||
OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
|
||||
} else {
|
||||
OsSetVector(hwiNum, hwiHandler, NULL);
|
||||
}
|
||||
#else
|
||||
(VOID)irqParam;
|
||||
OsSetVector(hwiNum, hwiHandler);
|
||||
#endif
|
||||
|
||||
#if (LOSCFG_DEBUG_TOOLS == 1)
|
||||
if ((irqParam != NULL) && (irqParam->pName != NULL)) {
|
||||
g_hwiFormName[hwiNum + OS_SYS_VECTOR_CNT] = (CHAR *)irqParam->pName;
|
||||
}
|
||||
g_hwiFormCnt[hwiNum + OS_SYS_VECTOR_CNT] = 0;
|
||||
#endif
|
||||
|
||||
HwiUnmask((IRQn_Type)hwiNum);
|
||||
HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
|
||||
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : ArchHwiDelete
|
||||
Description : Delete hardware interrupt
|
||||
Input : hwiNum --- hwi num to delete
|
||||
irqParam --- param of the hwi handler
|
||||
Output : None
|
||||
Return : LOS_OK on success or error code on failure
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
|
||||
{
|
||||
(VOID)irqParam;
|
||||
UINT32 intSave;
|
||||
|
||||
if (hwiNum >= OS_HWI_MAX_NUM) {
|
||||
return OS_ERRNO_HWI_NUM_INVALID;
|
||||
}
|
||||
|
||||
NVIC_DisableIRQ((IRQn_Type)hwiNum);
|
||||
|
||||
intSave = LOS_IntLock();
|
||||
|
||||
g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
|
||||
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
#define FAULT_STATUS_REG_BIT 32
|
||||
#define USGFAULT (1 << 18)
|
||||
#define BUSFAULT (1 << 17)
|
||||
#define MEMFAULT (1 << 16)
|
||||
#define DIV0FAULT (1 << 4)
|
||||
#define HARDFAULT_IRQN (-13)
|
||||
|
||||
ExcInfo g_excInfo = {0};
|
||||
|
||||
UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
|
||||
0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
|
||||
0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
|
||||
0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
|
||||
0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
|
||||
};
|
||||
|
||||
#if (LOSCFG_KERNEL_PRINTF != 0)
|
||||
STATIC VOID OsExcNvicDump(VOID)
|
||||
{
|
||||
#define OS_NR_NVIC_EXC_DUMP_TYPES 7
|
||||
UINT32 *base = NULL;
|
||||
UINT32 len, i, j;
|
||||
UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
|
||||
OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
|
||||
OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
|
||||
};
|
||||
UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
|
||||
OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
|
||||
OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
|
||||
OS_NVIC_INT_CTRL_SIZE
|
||||
};
|
||||
CHAR strRgEnable[] = "enable";
|
||||
CHAR strRgPending[] = "pending";
|
||||
CHAR strRgActive[] = "active";
|
||||
CHAR strRgPriority[] = "priority";
|
||||
CHAR strRgException[] = "exception";
|
||||
CHAR strRgShcsr[] = "shcsr";
|
||||
CHAR strRgIntCtrl[] = "control";
|
||||
CHAR *strRgs[] = {
|
||||
strRgEnable, strRgPending, strRgActive, strRgPriority,
|
||||
strRgException, strRgShcsr, strRgIntCtrl
|
||||
};
|
||||
|
||||
PRINTK("\r\nOS exception NVIC dump:\n");
|
||||
for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
|
||||
base = (UINT32 *)rgNvicBases[i];
|
||||
len = rgNvicLens[i];
|
||||
PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
|
||||
len = (len >> 2); /* 2: Gets the next register offset */
|
||||
for (j = 0; j < len; j++) {
|
||||
PRINTK("0x%x ", *(base + j));
|
||||
if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
|
||||
PRINTK("\n");
|
||||
}
|
||||
}
|
||||
PRINTK("\n");
|
||||
}
|
||||
}
|
||||
|
||||
STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
|
||||
|
||||
PRINTK("Type = %d\n", excInfo->type);
|
||||
PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
|
||||
PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
|
||||
PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
|
||||
}
|
||||
|
||||
STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
PRINTK("Current task info:\n");
|
||||
if (excInfo->phase == OS_EXC_IN_TASK) {
|
||||
LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
|
||||
PRINTK("Task name = %s\n", taskCB->taskName);
|
||||
PRINTK("Task ID = %d\n", taskCB->taskID);
|
||||
PRINTK("Task SP = %p\n", taskCB->stackPointer);
|
||||
PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
|
||||
PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
|
||||
} else if (excInfo->phase == OS_EXC_IN_HWI) {
|
||||
PRINTK("Exception occur in interrupt phase!\n");
|
||||
} else {
|
||||
PRINTK("Exception occur in system init phase!\n");
|
||||
}
|
||||
}
|
||||
|
||||
STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
PRINTK("Exception reg dump:\n");
|
||||
PRINTK("PC = 0x%x\n", excInfo->context->uwPC);
|
||||
PRINTK("LR = 0x%x\n", excInfo->context->uwLR);
|
||||
PRINTK("SP = 0x%x\n", excInfo->context->uwSP);
|
||||
PRINTK("R0 = 0x%x\n", excInfo->context->uwR0);
|
||||
PRINTK("R1 = 0x%x\n", excInfo->context->uwR1);
|
||||
PRINTK("R2 = 0x%x\n", excInfo->context->uwR2);
|
||||
PRINTK("R3 = 0x%x\n", excInfo->context->uwR3);
|
||||
PRINTK("R4 = 0x%x\n", excInfo->context->uwR4);
|
||||
PRINTK("R5 = 0x%x\n", excInfo->context->uwR5);
|
||||
PRINTK("R6 = 0x%x\n", excInfo->context->uwR6);
|
||||
PRINTK("R7 = 0x%x\n", excInfo->context->uwR7);
|
||||
PRINTK("R8 = 0x%x\n", excInfo->context->uwR8);
|
||||
PRINTK("R9 = 0x%x\n", excInfo->context->uwR9);
|
||||
PRINTK("R10 = 0x%x\n", excInfo->context->uwR10);
|
||||
PRINTK("R11 = 0x%x\n", excInfo->context->uwR11);
|
||||
PRINTK("R12 = 0x%x\n", excInfo->context->uwR12);
|
||||
PRINTK("PriMask = 0x%x\n", excInfo->context->uwPriMask);
|
||||
PRINTK("xPSR = 0x%x\n", excInfo->context->uwxPSR);
|
||||
}
|
||||
|
||||
#if (LOSCFG_KERNEL_BACKTRACE == 1)
|
||||
STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
|
||||
{
|
||||
UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
|
||||
UINT32 index;
|
||||
|
||||
OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
|
||||
|
||||
PRINTK("----- backtrace start -----\n");
|
||||
for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
|
||||
if (LR[index] == 0) {
|
||||
break;
|
||||
}
|
||||
PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
|
||||
}
|
||||
PRINTK("----- backtrace end -----\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
STATIC VOID OsExcMemPoolCheckInfo(VOID)
|
||||
{
|
||||
PRINTK("\r\nmemory pools check:\n");
|
||||
#if (LOSCFG_PLATFORM_EXC == 1)
|
||||
MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
|
||||
UINT32 errCnt;
|
||||
UINT32 i;
|
||||
|
||||
(VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
|
||||
|
||||
errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
|
||||
if (errCnt < OS_SYS_MEM_NUM) {
|
||||
errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
|
||||
}
|
||||
|
||||
if (errCnt == 0) {
|
||||
PRINTK("all memory pool check passed!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < errCnt; i++) {
|
||||
PRINTK("pool num = %d\n", i);
|
||||
PRINTK("pool type = %d\n", memExcInfo[i].type);
|
||||
PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
|
||||
PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
|
||||
PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
|
||||
PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
|
||||
PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
|
||||
PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
|
||||
PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
|
||||
}
|
||||
#endif
|
||||
UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
|
||||
if (ret == LOS_OK) {
|
||||
PRINTK("system heap memcheck over, all passed!\n");
|
||||
}
|
||||
|
||||
PRINTK("memory pool check end!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
|
||||
{
|
||||
#if (LOSCFG_KERNEL_PRINTF != 0)
|
||||
PRINTK("*************Exception Information**************\n");
|
||||
OsExcTypeInfo(excInfo);
|
||||
OsExcCurTaskInfo(excInfo);
|
||||
OsExcRegInfo(excInfo);
|
||||
#if (LOSCFG_KERNEL_BACKTRACE == 1)
|
||||
OsExcBackTraceInfo(excInfo);
|
||||
#endif
|
||||
OsGetAllTskInfo();
|
||||
OsExcNvicDump();
|
||||
OsExcMemPoolCheckInfo();
|
||||
#endif
|
||||
}
|
||||
|
||||
LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
|
||||
{
|
||||
UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
|
||||
g_intCount++;
|
||||
g_excInfo.nestCnt++;
|
||||
|
||||
g_excInfo.type = excType & OS_NULL_SHORT;
|
||||
|
||||
if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
|
||||
g_excInfo.faultAddr = faultAddr;
|
||||
} else {
|
||||
g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
|
||||
}
|
||||
if (g_losTask.runTask != NULL) {
|
||||
if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
|
||||
g_excInfo.phase = OS_EXC_IN_HWI;
|
||||
g_excInfo.thrdPid = pid;
|
||||
} else {
|
||||
g_excInfo.phase = OS_EXC_IN_TASK;
|
||||
g_excInfo.thrdPid = g_losTask.runTask->taskID;
|
||||
}
|
||||
} else {
|
||||
g_excInfo.phase = OS_EXC_IN_INIT;
|
||||
g_excInfo.thrdPid = OS_NULL_INT;
|
||||
}
|
||||
if (excType & OS_EXC_FLAG_NO_FLOAT) {
|
||||
g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
|
||||
} else {
|
||||
g_excInfo.context = excBufAddr;
|
||||
}
|
||||
|
||||
OsDoExcHook(EXC_INTERRUPT);
|
||||
OsExcInfoDisplay(&g_excInfo);
|
||||
ArchSysExit();
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HalHwiInit
|
||||
Description : initialization of the hardware interrupt
|
||||
Input : None
|
||||
Output : None
|
||||
Return : None
|
||||
**************************************************************************** */
|
||||
LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
|
||||
{
|
||||
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
|
||||
UINT32 index;
|
||||
g_hwiForm[0] = 0; /* [0] Top of Stack */
|
||||
g_hwiForm[1] = (HWI_PROC_FUNC)Reset_Handler; /* [1] reset */
|
||||
for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
|
||||
g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
|
||||
}
|
||||
/* Exception handler register */
|
||||
g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcNMI;
|
||||
g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcHardFault;
|
||||
g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault;
|
||||
g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcBusFault;
|
||||
g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcUsageFault;
|
||||
g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalSVCHandler;
|
||||
g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalPendSV;
|
||||
g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)SysTick_Handler;
|
||||
|
||||
/* Interrupt vector table location */
|
||||
SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
|
||||
#endif
|
||||
#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
|
||||
NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
|
||||
#endif
|
||||
|
||||
/* Enable USGFAULT, BUSFAULT, MEMFAULT */
|
||||
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
|
||||
/* Enable DIV 0 and unaligned exception */
|
||||
*(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_timer.h"
|
||||
#include "los_config.h"
|
||||
#include "los_tick.h"
|
||||
#include "los_arch_interrupt.h"
|
||||
#include "los_debug.h"
|
||||
|
||||
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
|
||||
STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
|
||||
STATIC UINT64 SysTickCycleGet(UINT32 *period);
|
||||
STATIC VOID SysTickLock(VOID);
|
||||
STATIC VOID SysTickUnlock(VOID);
|
||||
|
||||
STATIC ArchTickTimer g_archTickTimer = {
|
||||
.freq = 0,
|
||||
.irqNum = SysTick_IRQn,
|
||||
.periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
|
||||
.init = SysTickStart,
|
||||
.getCycle = SysTickCycleGet,
|
||||
.reload = SysTickReload,
|
||||
.lock = SysTickLock,
|
||||
.unlock = SysTickUnlock,
|
||||
.tickHandler = NULL,
|
||||
};
|
||||
|
||||
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
|
||||
{
|
||||
UINT32 ret;
|
||||
ArchTickTimer *tick = &g_archTickTimer;
|
||||
|
||||
tick->freq = OS_SYS_CLOCK;
|
||||
|
||||
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
|
||||
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
|
||||
OsSetVector(tick->irqNum, handler, NULL);
|
||||
#else
|
||||
OsSetVector(tick->irqNum, handler);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
|
||||
if (ret == 1) {
|
||||
return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
|
||||
}
|
||||
|
||||
return LOS_OK;
|
||||
}
|
||||
|
||||
STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
|
||||
{
|
||||
if (nextResponseTime > g_archTickTimer.periodMax) {
|
||||
nextResponseTime = g_archTickTimer.periodMax;
|
||||
}
|
||||
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
NVIC_ClearPendingIRQ(SysTick_IRQn);
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
|
||||
return nextResponseTime;
|
||||
}
|
||||
|
||||
STATIC UINT64 SysTickCycleGet(UINT32 *period)
|
||||
{
|
||||
UINT32 hwCycle = 0;
|
||||
UINTPTR intSave = LOS_IntLock();
|
||||
UINT32 val = SysTick->VAL;
|
||||
*period = SysTick->LOAD;
|
||||
if (val != 0) {
|
||||
hwCycle = *period - val;
|
||||
}
|
||||
LOS_IntRestore(intSave);
|
||||
return (UINT64)hwCycle;
|
||||
}
|
||||
|
||||
STATIC VOID SysTickLock(VOID)
|
||||
{
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
STATIC VOID SysTickUnlock(VOID)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
ArchTickTimer *ArchSysTickTimerGet(VOID)
|
||||
{
|
||||
return &g_archTickTimer;
|
||||
}
|
||||
|
||||
UINT32 ArchEnterSleep(VOID)
|
||||
{
|
||||
__DSB();
|
||||
__WFI();
|
||||
__ISB();
|
||||
|
||||
return LOS_OK;
|
||||
}
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_trustzone.h"
|
||||
#include "los_secure_macros.h"
|
||||
#include "los_secure_context.h"
|
||||
#include "los_debug.h"
|
||||
#include "los_arch_context.h"
|
||||
#include "los_interrupt.h"
|
||||
|
||||
OsSecureContext *g_secureContext = NULL;
|
||||
|
||||
VOID HalSecureSVCHandler(UINT32 svcID, UINTPTR arg)
|
||||
{
|
||||
switch (svcID) {
|
||||
case OS_SVC_START_SCHEDULE:
|
||||
HalSecureContextInit();
|
||||
HalStartFirstTask();
|
||||
break;
|
||||
case OS_SVC_ALLOCATE_SECURE_CONTEXT:
|
||||
g_secureContext = HalSecureContextAlloc(arg);
|
||||
LOS_ASSERT(g_secureContext != NULL);
|
||||
HalSecureContextLoad(g_secureContext);
|
||||
break;
|
||||
case OS_SVC_FREE_SECURE_CONTEXT:
|
||||
HalSecureContextFree(g_secureContext);
|
||||
break;
|
||||
default:
|
||||
PRINT_ERR("Incorrect svc id = %u\n", svcID);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
VOID HalStartToRun(VOID)
|
||||
{
|
||||
HalSVCStartSchedule();
|
||||
}
|
||||
|
||||
VOID LOS_SecureContextAlloc(UINT32 secureStackSize)
|
||||
{
|
||||
if (secureStackSize == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
LOS_ASSERT((__get_IPSR() == 0) && (__get_PRIMASK() == 0));
|
||||
secureStackSize = LOS_Align(secureStackSize, sizeof(UINTPTR));
|
||||
HalSVCSecureContextAlloc(secureStackSize);
|
||||
}
|
||||
|
||||
VOID LOS_SecureContextFree(VOID)
|
||||
{
|
||||
HalSVCSecureContextFree();
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_TRUSTZONE_H
|
||||
#define _LOS_TRUSTZONE_H
|
||||
|
||||
#include "los_config.h"
|
||||
#include "los_task.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
extern VOID LOS_SecureContextAlloc(UINT32 secureStackSize);
|
||||
extern VOID LOS_SecureContextFree(VOID);
|
||||
|
||||
extern VOID HalStartFirstTask(VOID);
|
||||
extern VOID HalSVCStartSchedule(VOID);
|
||||
extern VOID HalSVCSecureContextAlloc(UINT32 secureStackSize);
|
||||
extern VOID HalSVCSecureContextFree(VOID);
|
||||
extern VOID HalSVCHandler(VOID);
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_secure_context.h"
|
||||
#include "los_secure_macros.h"
|
||||
#include "los_secure_heap.h"
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureContextInit(VOID)
|
||||
{
|
||||
UINT32 ipsr;
|
||||
|
||||
OS_IPSR_READ(ipsr);
|
||||
if (!ipsr) {
|
||||
return;
|
||||
}
|
||||
|
||||
HalSecureContextInitAsm();
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY OsSecureContext *HalSecureContextAlloc(UINT32 size)
|
||||
{
|
||||
OsSecureContext *secureContext = NULL;
|
||||
UINT32 ipsr;
|
||||
|
||||
OS_IPSR_READ(ipsr);
|
||||
if (!ipsr) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
secureContext = HalSecureMalloc(sizeof(OsSecureContext));
|
||||
if (secureContext == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
secureContext->stackLimit = HalSecureMalloc(size);
|
||||
if (secureContext->stackLimit == NULL) {
|
||||
HalSecureFree(secureContext);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
secureContext->stackStart = secureContext->stackLimit + size;
|
||||
secureContext->curStackPointer = secureContext->stackStart;
|
||||
|
||||
return secureContext;
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureContextFree(OsSecureContext *secureContext)
|
||||
{
|
||||
UINT32 ipsr;
|
||||
|
||||
OS_IPSR_READ(ipsr);
|
||||
if (!ipsr) {
|
||||
return;
|
||||
}
|
||||
|
||||
HalSecureFree(secureContext->stackLimit);
|
||||
secureContext->stackLimit = NULL;
|
||||
HalSecureFree(secureContext);
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureContextLoad(OsSecureContext *secureContext)
|
||||
{
|
||||
HalSecureContextLoadAsm(secureContext);
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureContextSave(OsSecureContext *secureContext)
|
||||
{
|
||||
HalSecureContextSaveAsm(secureContext);
|
||||
}
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_SECURE_CONTEXT_H
|
||||
#define _LOS_SECURE_CONTEXT_H
|
||||
|
||||
#include "los_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef struct {
|
||||
UINT8 *curStackPointer;
|
||||
UINT8 *stackLimit;
|
||||
UINT8 *stackStart;
|
||||
} OsSecureContext;
|
||||
|
||||
extern VOID HalSecureContextInit(VOID);
|
||||
extern OsSecureContext *HalSecureContextAlloc(UINT32 size);
|
||||
extern VOID HalSecureContextFree(OsSecureContext *secureContext);
|
||||
extern VOID HalSecureContextLoad(OsSecureContext *secureContext);
|
||||
extern VOID HalSecureContextSave(OsSecureContext *secureContext);
|
||||
|
||||
extern VOID HalSecureContextInitAsm(VOID);
|
||||
extern VOID HalSecureContextLoadAsm(OsSecureContext *secureContext);
|
||||
extern VOID HalSecureContextSaveAsm(OsSecureContext *secureContext);
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
PRESERVE8
|
||||
|
||||
EXPORT HalSecureContextInitAsm
|
||||
EXPORT HalSecureContextLoadAsm
|
||||
EXPORT HalSecureContextSaveAsm
|
||||
|
||||
OS_SECURE_SCB_AIRCR EQU 0xE000ED0C
|
||||
|
||||
SECTION .text:CODE(2)
|
||||
THUMB
|
||||
REQUIRE8
|
||||
|
||||
HalSecureContextInitAsm
|
||||
LDR R0, =OS_SECURE_SCB_AIRCR
|
||||
LDR R1, [R0]
|
||||
|
||||
MOV R2, #0xFFFF
|
||||
LSL R2, R2, #16
|
||||
BIC R1, R1, R2
|
||||
MOV R2, #0x05FA
|
||||
LSL R2, R2, #16
|
||||
ORR R1, R1, R2
|
||||
|
||||
BIC R1, R1, #0x4000
|
||||
MOV R2, #0x4000
|
||||
ORR R1, R1, R2
|
||||
STR R1, [R0]
|
||||
|
||||
MOV R0, #0
|
||||
MSR PSPLIM, R0
|
||||
MSR PSP, R0
|
||||
MOV R0, #2
|
||||
MSR CONTROL, R0
|
||||
BX LR
|
||||
|
||||
HalSecureContextLoadAsm
|
||||
MRS R1, IPSR
|
||||
CBZ R1, __ThreadMode
|
||||
|
||||
LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext->stackLimit. */
|
||||
MSR PSPLIM, R2 /* Restore PSPLIM. */
|
||||
MSR PSP, R1 /* Restore PSP. */
|
||||
BX LR
|
||||
|
||||
HalSecureContextSaveAsm
|
||||
MRS R0, IPSR
|
||||
CBZ R0, __ThreadMode
|
||||
|
||||
MRS R0, PSP
|
||||
STR R0, [R1] /* g_secureContext->curStackPointer = R0. */
|
||||
MOV R0, #0
|
||||
MSR PSPLIM, R0 /* No PSPLIM for the current task. */
|
||||
MSR PSP, R0 /* No secure stack for the current task. */
|
||||
|
||||
__ThreadMode
|
||||
BX LR
|
||||
|
||||
END
|
|
@ -0,0 +1,230 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "los_secure_heap.h"
|
||||
#include "los_secure_macros.h"
|
||||
#include "los_config.h"
|
||||
#include "los_list.h"
|
||||
|
||||
#pragma data_alignment = 0x4
|
||||
STATIC UINT8 g_secureHeap[LOSCFG_SECURE_HEAP_SIZE] = {0};
|
||||
STATIC LOS_DL_LIST g_secureHeapFreeList = {NULL, NULL};
|
||||
|
||||
struct OsSecureHeapNode {
|
||||
LOS_DL_LIST freeNode;
|
||||
struct OsSecureHeapNode *preNode;
|
||||
UINT32 size : 24;
|
||||
UINT32 used : 8;
|
||||
};
|
||||
|
||||
#define OS_SECURE_HEAP_NODE_HEAD_SIZE sizeof(struct OsSecureHeapNode)
|
||||
#define OS_SECURE_HEAP_ALIGN_SIZE sizeof(UINTPTR)
|
||||
|
||||
#define OS_SECURE_HEAP_NODE_USED 1
|
||||
#define OS_SECURE_HEAP_NODE_FREE 0
|
||||
|
||||
#define OS_SECURE_HEAP_FIRST_NODE ((struct OsSecureHeapNode *)g_secureHeap)
|
||||
#define OS_SECURE_HEAP_NEXT_NODE(node) \
|
||||
((struct OsSecureHeapNode *)((UINT8 *)(node) + (node)->size))
|
||||
#define OS_SECURE_HEAP_END_NODE \
|
||||
((struct OsSecureHeapNode *)((UINT8 *)g_secureHeap + LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE))
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapListInit(LOS_DL_LIST *head)
|
||||
{
|
||||
head->pstPrev = head;
|
||||
head->pstNext = head;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapListDelete(LOS_DL_LIST *node)
|
||||
{
|
||||
node->pstNext->pstPrev = node->pstPrev;
|
||||
node->pstPrev->pstNext = node->pstNext;
|
||||
node->pstNext = NULL;
|
||||
node->pstPrev = NULL;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapListAdd(LOS_DL_LIST *listNode, LOS_DL_LIST *node)
|
||||
{
|
||||
node->pstNext = listNode->pstNext;
|
||||
node->pstPrev = listNode;
|
||||
listNode->pstNext->pstPrev = node;
|
||||
listNode->pstNext = node;
|
||||
}
|
||||
|
||||
STATIC struct OsSecureHeapNode *OsSecureHeapFindSuitableFreeBlock(UINT32 allocSize)
|
||||
{
|
||||
LOS_DL_LIST *listNodeHead = &g_secureHeapFreeList;
|
||||
struct OsSecureHeapNode *tmpNode = NULL;
|
||||
|
||||
LOS_DL_LIST_FOR_EACH_ENTRY(tmpNode, listNodeHead, struct OsSecureHeapNode, freeNode) {
|
||||
if (tmpNode->size >= allocSize) {
|
||||
return tmpNode;
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapClearNode(struct OsSecureHeapNode *node)
|
||||
{
|
||||
node->preNode = NULL;
|
||||
node->size = 0;
|
||||
node->used = 0;
|
||||
node->freeNode.pstPrev = NULL;
|
||||
node->freeNode.pstNext = NULL;
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapMergeNode(struct OsSecureHeapNode *node)
|
||||
{
|
||||
struct OsSecureHeapNode *nextNode = NULL;
|
||||
|
||||
node->preNode->size += node->size;
|
||||
nextNode = (struct OsSecureHeapNode *)((UINTPTR)node + node->size);
|
||||
nextNode->preNode = node->preNode;
|
||||
OsSecureHeapClearNode(node);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapSplitNode(struct OsSecureHeapNode *allocNode, UINT32 allocSize)
|
||||
{
|
||||
struct OsSecureHeapNode *newFreeNode = NULL;
|
||||
struct OsSecureHeapNode *nextNode = NULL;
|
||||
|
||||
newFreeNode = (struct OsSecureHeapNode *)((UINT8 *)allocNode + allocSize);
|
||||
newFreeNode->preNode = allocNode;
|
||||
newFreeNode->size = allocNode->size - allocSize;
|
||||
newFreeNode->used = OS_SECURE_HEAP_NODE_FREE;
|
||||
allocNode->size = allocSize;
|
||||
nextNode = OS_SECURE_HEAP_NEXT_NODE(newFreeNode);
|
||||
nextNode->preNode = newFreeNode;
|
||||
if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
|
||||
OsSecureHeapListDelete(&nextNode->freeNode);
|
||||
OsSecureHeapMergeNode(nextNode);
|
||||
}
|
||||
|
||||
OsSecureHeapListAdd(&g_secureHeapFreeList, &newFreeNode->freeNode);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapFreeNode(struct OsSecureHeapNode *node)
|
||||
{
|
||||
struct OsSecureHeapNode *nextNode = NULL;
|
||||
|
||||
if ((node->preNode != NULL) && (node->preNode->used == OS_SECURE_HEAP_NODE_FREE)) {
|
||||
struct OsSecureHeapNode *preNode = node->preNode;
|
||||
OsSecureHeapMergeNode(node);
|
||||
nextNode = OS_SECURE_HEAP_NEXT_NODE(preNode);
|
||||
if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
|
||||
OsSecureHeapListDelete(&nextNode->freeNode);
|
||||
OsSecureHeapMergeNode(nextNode);
|
||||
}
|
||||
|
||||
OsSecureHeapListDelete(&preNode->freeNode);
|
||||
preNode->used = OS_SECURE_HEAP_NODE_FREE;
|
||||
OsSecureHeapListAdd(&g_secureHeapFreeList, &preNode->freeNode);
|
||||
} else {
|
||||
nextNode = OS_SECURE_HEAP_NEXT_NODE(node);
|
||||
if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
|
||||
OsSecureHeapListDelete(&nextNode->freeNode);
|
||||
OsSecureHeapMergeNode(nextNode);
|
||||
}
|
||||
|
||||
node->used = OS_SECURE_HEAP_NODE_FREE;
|
||||
OsSecureHeapListAdd(&g_secureHeapFreeList, &node->freeNode);
|
||||
}
|
||||
}
|
||||
|
||||
STATIC INLINE VOID *OsSecureHeapAllocNode(UINT32 size)
|
||||
{
|
||||
struct OsSecureHeapNode *allocNode = NULL;
|
||||
UINT32 allocSize;
|
||||
|
||||
allocSize = LOS_Align(size + OS_SECURE_HEAP_NODE_HEAD_SIZE, OS_SECURE_HEAP_ALIGN_SIZE);
|
||||
allocNode = OsSecureHeapFindSuitableFreeBlock(allocSize);
|
||||
if (allocNode == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
if ((allocSize + OS_SECURE_HEAP_NODE_HEAD_SIZE + OS_SECURE_HEAP_ALIGN_SIZE) <= allocNode->size) {
|
||||
OsSecureHeapSplitNode(allocNode, allocSize);
|
||||
}
|
||||
OsSecureHeapListDelete(&allocNode->freeNode);
|
||||
allocNode->used = OS_SECURE_HEAP_NODE_USED;
|
||||
|
||||
return (allocNode + 1);
|
||||
}
|
||||
|
||||
STATIC INLINE VOID OsSecureHeapInit(VOID)
|
||||
{
|
||||
struct OsSecureHeapNode *newNode = NULL;
|
||||
struct OsSecureHeapNode *endNode = NULL;
|
||||
|
||||
newNode = OS_SECURE_HEAP_FIRST_NODE;
|
||||
newNode->size = LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE;
|
||||
newNode->preNode = OS_SECURE_HEAP_END_NODE;
|
||||
newNode->used = OS_SECURE_HEAP_NODE_FREE;
|
||||
|
||||
OsSecureHeapListInit(&g_secureHeapFreeList);
|
||||
OsSecureHeapListAdd(&g_secureHeapFreeList, &newNode->freeNode);
|
||||
|
||||
endNode = OS_SECURE_HEAP_END_NODE;
|
||||
endNode->preNode = newNode;
|
||||
endNode->size = OS_SECURE_HEAP_NODE_HEAD_SIZE;
|
||||
endNode->used = OS_SECURE_HEAP_NODE_USED;
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID *HalSecureMalloc(UINT32 size)
|
||||
{
|
||||
if (size == 0) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if ((g_secureHeapFreeList.pstPrev == NULL) &&
|
||||
(g_secureHeapFreeList.pstNext == NULL)) {
|
||||
OsSecureHeapInit();
|
||||
}
|
||||
|
||||
return OsSecureHeapAllocNode(size);
|
||||
}
|
||||
|
||||
OS_CMSE_NS_ENTRY VOID HalSecureFree(VOID *ptr)
|
||||
{
|
||||
struct OsSecureHeapNode *node = NULL;
|
||||
|
||||
if (ptr == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
node = (struct OsSecureHeapNode *)((UINTPTR)ptr - OS_SECURE_HEAP_NODE_HEAD_SIZE);
|
||||
if (node->used != OS_SECURE_HEAP_NODE_USED) {
|
||||
return;
|
||||
}
|
||||
|
||||
OsSecureHeapFreeNode(node);
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_SECURE_HEAP_H
|
||||
#define _LOS_SECURE_HEAP_H
|
||||
|
||||
#include "los_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
VOID *HalSecureMalloc(UINT32 size);
|
||||
VOID HalSecureFree(VOID *ptr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
|
||||
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
* conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
||||
* of conditions and the following disclaimer in the documentation and/or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LOS_SECURE_MACROS_H
|
||||
#define _LOS_SECURE_MACROS_H
|
||||
|
||||
#include "los_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define OS_CMSE_NS_ENTRY __attribute__((cmse_nonsecure_entry))
|
||||
#define OS_CMSE_NS_CALL __attribute__((cmse_nonsecure_call))
|
||||
#define OS_IPSR_READ(ipsr) __asm volatile("MRS %0, IPSR" : "=r" (ipsr))
|
||||
|
||||
#define OS_SVC_ALLOCATE_SECURE_CONTEXT 0
|
||||
#define OS_SVC_FREE_SECURE_CONTEXT 1
|
||||
#define OS_SVC_START_SCHEDULE 2
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue