!604 fix: 修复任务栈对齐问题及补充posix和cmsis测试用例

Merge pull request !604 from zhushengle/test

.gitee/ISSUE_TEMPLATE.zh-CN.md

@@ -7,7 +7,5 @@
 
 
 ### 报错信息
-
-
-
-
+    
+    

.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md

@@ -10,6 +10,12 @@
 ### 测试用例（新增、改动、可能影响的功能）
 
 
-
+### 是否需要同步至release（如：3.0LTS ... ）分支？
+
+必须选择一项（在MarkDown模式下用[x]替换[ ]即可勾选对应选项）:
+- [ ] 是，需要同步的分支：
+- [ ] 否
+
+理由：
 
 

.gitignore

@@ -1 +1,21 @@
 test
+*.si4project
+tags
+cscope.*
+*.swp
+/**/*_iar/project/
+!los_demo.eww
+!los_demo.ewp
+!los_demo.ewd
+!los_demo.ewt
+!los_demo.dep
+!*.icf
+targets/cortex-m7_nucleo_f767zi_gcc/build
+*.o
+*.d
+*.su
+
+# Menuconfig temp files
+/config.h
+/.config
+/.config.old

BUILD.gn

@@ -1,42 +1,309 @@
-# Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
-# Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without modification,
-# are permitted provided that the following conditions are met:
-#
-# 1. Redistributions of source code must retain the above copyright notice, this list of
-#    conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright notice, this list
-#    of conditions and the following disclaimer in the documentation and/or other materials
-#    provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its contributors may be used
-#    to endorse or promote products derived from this software without specific prior written
-#    permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
-# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import("//build/lite/config/subsystem/lite_subsystem.gni")
-
-lite_subsystem("kernel") {
-    subsystem_components = [
-        "//kernel/liteos_m/arch",
-        "//kernel/liteos_m/components",
-        "//kernel/liteos_m/kernel",
-    ]
-
-    if (LOSCFG_TEST) {
-        subsystem_components += [ "//kernel/liteos_m/test" ]
-    }
-}
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//build/lite/config/component/lite_component.gni")
+
+LITEOS_MENUCONFIG_H = rebase_path("$root_out_dir/config.h")
+
+declare_args() {
+  liteos_name = "OHOS_Image"
+  liteos_kernel_only = false
+}
+
+import("liteos.gni")
+
+liteos_arch_cflags = []
+if (defined(LOSCFG_ARCH_ARM)) {
+  mcpu = LOSCFG_ARCH_CPU
+  if (defined(LOSCFG_ARCH_ARM_AARCH64) && defined(LOSCFG_ARCH_FPU_DISABLE)) {
+    mcpu += "+nofp"
+  }
+  liteos_arch_cflags += [ "-mcpu=$mcpu" ]
+  if (defined(LOSCFG_ARCH_ARM_AARCH32) && defined(LOSCFG_ARCH_FPU)) {
+    liteos_arch_cflags += [ "-mfpu=$LOSCFG_ARCH_FPU" ]
+  }
+}
+
+cc = "$ohos_current_cc_command " + string_join(" ", liteos_arch_cflags)
+if (ohos_build_compiler == "clang") {
+  cc += " --target=$target_triple"
+}
+
+config("arch_config") {
+  cflags = liteos_arch_cflags
+  asmflags = cflags
+  ldflags = cflags
+  if (defined(LOSCFG_ARCH_ARM_AARCH32)) {
+    if (!defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+      cflags += [ "-mthumb-interwork" ]
+    }
+  }
+  if (defined(LOSCFG_THUMB)) {
+    cflags += [ "-mthumb" ]
+    if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+      cflags += [ "-mimplicit-it=thumb" ]
+    } else {
+      cflags += [ "-Wa,-mimplicit-it=thumb" ]
+    }
+  }
+}
+
+config("stdinc_config") {
+  std_include = exec_script("//build/lite/run_shell_cmd.py",
+                            [ "$cc -print-file-name=include" ],
+                            "trim string")
+  cflags = [
+    "-isystem",
+    std_include,
+  ]
+  cflags += [ "-nostdinc" ]
+  asmflags = cflags
+  if (defined(LOSCFG_LIBC_NEWLIB)) {
+    cflags -= [ "-nostdinc" ]
+  }
+}
+
+config("ssp_config") {
+  cflags = []
+  if (defined(LOSCFG_CC_STACKPROTECTOR_ALL)) {
+    cflags += [ "-fstack-protector-all" ]
+  } else if (defined(LOSCFG_CC_STACKPROTECTOR_STRONG)) {
+    cflags += [ "-fstack-protector-strong" ]
+  } else if (defined(LOSCFG_CC_STACKPROTECTOR)) {
+    cflags += [
+      "-fstack-protector",
+      "--param",
+      "ssp-buffer-size=4",
+    ]
+  } else {
+    cflags += [ "-fno-stack-protector" ]
+  }
+  asmflags = cflags
+}
+
+config("optimize_config") {
+  cflags = []
+  if (defined(LOSCFG_COMPILE_DEBUG)) {
+    cflags += [
+      "-g",
+      "-gdwarf-2",
+    ]
+    optimization_cflag = "-O0"
+  }
+  if (defined(LOSCFG_COMPILE_OPTIMIZE)) {
+    optimization_cflag = "-O2"
+  }
+  if (defined(LOSCFG_COMPILE_OPTIMIZE_SIZE)) {
+    if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+      optimization_cflag = "-Oz"
+    } else {
+      optimization_cflag = "-Os"
+    }
+  }
+  if (defined(LOSCFG_COMPILE_LTO)) {
+    if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+      cflags += [ "-flto=thin" ]
+    } else {
+      #cflags += [ "-flto" ]
+    }
+  }
+  cflags += [ optimization_cflag ]
+  asmflags = cflags
+}
+
+config("kconfig_config") {
+  cflags = [
+    "-imacros",
+    "$LITEOS_MENUCONFIG_H",
+  ]
+  asmflags = cflags
+  cflags_cc = cflags
+}
+
+config("warn_config") {
+  cflags = [
+    "-Wall",
+    "-Werror",
+    "-Wpointer-arith",
+    "-Wstrict-prototypes",
+    "-Winvalid-pch",
+    "-Wno-address-of-packed-member",
+  ]
+  asmflags = cflags
+}
+
+config("dialect_config") {
+  cflags_c = [ "-std=c99" ]
+  cflags_cc = [ "-std=c++11" ]
+}
+
+config("misc_config") {
+  defines = [ "__LITEOS__" ]
+  defines += [ "__LITEOS_M__" ]
+  if (!defined(LOSCFG_DEBUG_VERSION)) {
+    defines += [ "NDEBUG" ]
+  }
+
+  cflags = [
+    "-fno-pic",
+    "-fno-builtin",
+    "-fms-extensions",
+    "-fno-strict-aliasing",
+    "-fno-common",
+    "-fsigned-char",
+    "-ffunction-sections",
+    "-fdata-sections",
+    "-fno-exceptions",
+    "-fno-omit-frame-pointer",
+  ]
+
+  if (!defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+    cflags += [ "-fno-aggressive-loop-optimizations" ]
+  }
+
+  asmflags = cflags
+  asmflags += [ "-DCLZ=CLZ" ]
+}
+
+config("los_config") {
+  configs = [
+    #":arch_config",
+    ":kconfig_config",
+
+    ":stdinc_config",
+    ":dialect_config",
+    ":optimize_config",
+    ":ssp_config",
+
+    #":warn_config",
+    ":misc_config",
+  ]
+}
+
+cmd = "if [ -f $device_path/BUILD.gn ]; then echo true; else echo false; fi"
+HAVE_DEVICE_SDK = exec_script("//build/lite/run_shell_cmd.py", [ cmd ], "value")
+
+# board and soc decoupling feature, device_path should contains board
+BOARD_SOC_FEATURE = device_path != string_replace(device_path, "/board/", "")
+
+config("public") {
+  configs = [
+    "arch:public",
+    "kernel:public",
+    "kal:public",
+    "components:public",
+    "utils:public",
+  ]
+
+  if (BOARD_SOC_FEATURE) {
+    configs += [ "//device/board/$device_company:public" ]
+    configs += [ "//device/soc/$LOSCFG_SOC_COMPANY:public" ]
+  } else {
+    if (HAVE_DEVICE_SDK) {
+      configs += [ "$device_path:public" ]
+    }
+  }
+}
+
+group("modules") {
+  deps = [
+    "arch",
+    "components",
+    "kal",
+    "kernel",
+    "testsuites",
+    "utils",
+    HDFTOPDIR,
+  ]
+
+  if (BOARD_SOC_FEATURE) {
+    deps += [ "//device/board/$device_company" ]
+    deps += [ "//device/soc/$LOSCFG_SOC_COMPANY" ]
+  } else {
+    if (HAVE_DEVICE_SDK) {
+      deps += [ device_path ]
+    }
+  }
+}
+
+# when HAVE_DEVICE_SDK is not reached, gn raises an error. so we just use it as
+# not needed
+not_needed([ "HAVE_DEVICE_SDK" ])
+
+static_library("libkernel") {
+  deps = [ ":modules" ]
+  complete_static_lib = false
+}
+
+group("kernel") {
+  deps = [ ":libkernel" ]
+}
+
+group("liteos_m") {
+}
+
+executable("liteos") {
+  configs += [
+    ":public",
+    ":los_config",
+  ]
+
+  ldflags = [
+    "-static",
+    "-Wl,--gc-sections",
+    "-Wl,-Map=$liteos_name.map",
+  ]
+
+  output_dir = target_out_dir
+
+  if (liteos_kernel_only) {
+    deps = [ ":kernel" ]
+  } else {
+    deps = [ "//build/lite:ohos" ]
+  }
+}
+
+copy("copy_liteos") {
+  deps = [ ":liteos" ]
+  sources = [ "$target_out_dir/unstripped/bin/liteos" ]
+  outputs = [ "$root_out_dir/$liteos_name" ]
+}
+
+build_ext_component("build_kernel_image") {
+  deps = [ ":copy_liteos" ]
+  exec_path = rebase_path(root_out_dir)
+
+  objcopy = "${compile_prefix}objcopy$toolchain_cmd_suffix"
+  objdump = "${compile_prefix}objdump$toolchain_cmd_suffix"
+
+  command = "$objcopy -O binary $liteos_name $liteos_name.bin"
+  command +=
+      " && sh -c '$objdump -t $liteos_name | sort >$liteos_name.sym.sorted'"
+  command += " && sh -c '$objdump -d $liteos_name >$liteos_name.asm'"
+}

Kconfig

@@ -0,0 +1,667 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+mainmenu "Huawei LiteOS Configuration"
+
+menu "Compiler"
+choice
+    prompt "Compiler type"
+    default COMPILER_GCC
+    help
+      Choose compiler type.
+
+config COMPILER_GCC
+    bool "GCC"
+
+config CROSS_COMPILE
+    string "GCC cross-compile toolchain prefix"
+    depends on COMPILER_GCC
+    default "arm-none-eabi-" if ARCH_ARM_AARCH32
+
+config COMPILER_CLANG_LLVM
+    bool "Clang"
+
+config LLVM_TARGET
+    string "Clang LLVM target"
+    depends on COMPILER_CLANG_LLVM
+    default "arm-liteos-ohos" if ARCH_ARM_AARCH32
+
+endchoice
+
+config COMPILE_DEBUG
+    bool "Enable debug options"
+    default n
+    help
+      Answer Y to add -g option in compile command.
+
+config COMPILE_OPTIMIZE
+    bool "Enable code optimization options"
+    default y
+    help
+      Answer Y to add optimization options for efficient code.
+      The final binary size will be smaller and execute faster.
+      But the debugging experience may be worst somehow.
+
+config COMPILE_OPTIMIZE_SIZE
+    bool "Enable code size optimization options" if COMPILE_OPTIMIZE
+    default y
+    help
+      Answer Y to add optimization options for small code size.
+      The final binary size will be smaller.
+      But the compile time may be a bit longer.
+
+config COMPILE_LTO
+    bool "Enable link time optimization (LTO)" if COMPILE_OPTIMIZE_SIZE
+    default y
+    help
+      Answer Y to add lto options for more smaller code size.
+      The final binary size will be smaller.
+      But the compile time may be much longer.
+
+endmenu
+
+menu "Platform"
+
+######################### config options of bsp #####################
+config PLATFORM
+    string
+    default "virt"            if PLATFORM_QEMU_ARM_VIRT_CM7 || PLATFORM_QEMU_ARM_VIRT_CM4 || PLATFORM_QEMU_ARM_VIRT_CM55 || PRODUCT_QEMU_RISCV32_VIRT || PLATFORM_QEMU_CSKY_SMARTL || PLATFORM_QEMU_XTENSA_ESP32
+
+config PRODUCT_NAME
+    string
+    default "arm_virt" if PRODUCT_QEMU_ARM
+    default "arm_mps2_an386" if PRODUCT_QEMU_ARM_MPS2_AN386
+    default "arm_mps3_an547" if PRODUCT_QEMU_ARM_MPS3_AN547
+    default "riscv32_virt" if PRODUCT_QEMU_RISCV32_VIRT
+    default "csky_smartl_e802" if PRODUCT_QEMU_CSKY_SMARTL_E802
+    default "xtensa_esp32" if PRODUCT_QEMU_XTENSA_ESP32
+
+config DEVICE_COMPANY
+    string
+    default "qemu" if PLATFORM_QEMU_ARM_VIRT_CM7 || PLATFORM_QEMU_ARM_VIRT_CM4 || PLATFORM_QEMU_ARM_VIRT_CM55 || PRODUCT_QEMU_RISCV32_VIRT || PLATFORM_QEMU_CSKY_SMARTL || PLATFORM_QEMU_XTENSA_ESP32
+
+choice
+    prompt "Chip"
+    default PLATFORM_QEMU_ARM_VIRT_CM7
+    help
+      Qemu ARM Virt variants (based on different CPU types):
+       - qemu_arm_virt_cm7
+       - qemu_arm_virt_cm4
+       - qemu_riscv32_virt
+       - qemu_csky_smartl
+       - qemu_xtensa_esp32
+
+config PLATFORM_QEMU_ARM_VIRT_CM7
+    bool "qemu_arm_virt_cm7"
+    select ARCH_CORTEX_M7
+    help
+        QEMU ARM Virtual Platform using Cortex-M7 CPU.
+
+config PLATFORM_QEMU_ARM_VIRT_CM4
+    bool "qemu_arm_virt_cm4"
+    select ARCH_CORTEX_M4
+    help
+        QEMU ARM Virtual Platform using Cortex-M4 CPU.
+
+config PLATFORM_QEMU_ARM_VIRT_CM55
+    bool "qemu_arm_virt_cm55"
+    select ARCH_CORTEX_M55
+    help
+        QEMU ARM Virtual Platform using Cortex-M55 CPU.
+
+config PLATFORM_QEMU_RISCV32_VIRT
+    bool "qemu_riscv32_virt"
+    select ARCH_RISCV32
+    help
+        QEMU RISCV Virtual Platform using riscv32 CPU.
+
+config PLATFORM_QEMU_CSKY_SMARTL
+    bool "qemu_csky_smartl"
+    select ARCH_CSKY
+    help
+        QEMU SmartL Virtual Platform using csky CPU.
+
+config PLATFORM_QEMU_XTENSA_ESP32
+    bool "qemu_xtensa_esp32"
+    select ARCH_XTENSA
+    help
+        QEMU ESP32 Virtual Platform using xtensa CPU.
+
+endchoice
+
+choice
+    prompt "Product"
+    help
+      Select your target board.
+
+config PRODUCT_QEMU_ARM
+    bool "arm_virt" if PLATFORM_QEMU_ARM_VIRT_CM7
+
+config PRODUCT_QEMU_ARM_MPS2_AN386
+    bool "arm_mps2_an386" if PLATFORM_QEMU_ARM_VIRT_CM4
+
+config PRODUCT_QEMU_ARM_MPS3_AN547
+    bool "arm_mps3_an547" if PLATFORM_QEMU_ARM_VIRT_CM55
+
+config PRODUCT_QEMU_RISCV32_VIRT
+    bool "riscv32_virt" if PLATFORM_QEMU_RISCV32_VIRT
+
+config PRODUCT_QEMU_CSKY_SMARTL_E802
+    bool "csky_smartl_e802" if PLATFORM_QEMU_CSKY_SMARTL
+
+config PRODUCT_QEMU_XTENSA_ESP32
+    bool "xtensa_esp32" if PLATFORM_QEMU_XTENSA_ESP32
+
+endchoice
+
+
+######################### config options of cpu arch ################
+source "arch/Kconfig"
+
+# Device Kconfig import
+osource "$(DEVICE_PATH)/Kconfig"
+
+config SOC_COMPANY
+    string "SoC company name to locate soc build path"
+    help
+      This option specifies the SoC company name, used to locate the build path for soc. This option is set by the
+      SoC's Kconfig file, and should be exactly the same with SoC company path, and the user should generally avoid
+       modifying it via the menu configuration.
+
+orsource "../../device/board/*/Kconfig.liteos_m.shields"
+
+orsource "../../device/board/$(BOARD_COMPANY)/Kconfig.liteos_m.defconfig.boards"
+
+choice
+    prompt "Board Selection"
+
+orsource "../../device/board/$(BOARD_COMPANY)/Kconfig.liteos_m.boards"
+
+endchoice
+
+orsource "../../device/soc/*/Kconfig.liteos_m.defconfig"
+
+choice
+    prompt "SoC Series Selection"
+
+orsource "../../device/soc/*/Kconfig.liteos_m.series"
+
+endchoice
+
+orsource "../../device/soc/*/Kconfig.liteos_m.soc"
+
+config QUICK_START
+    bool "Enable QUICK_START"
+    default n
+    depends on DRIVERS && FS_VFS
+    help
+      Answer Y to enable LiteOS support quick start.
+endmenu
+
+######################### config options of kernel #####################
+menu "Kernel"
+
+######################### config options of extended #####################
+
+config KERNEL_EXTKERNEL
+    bool "Enable Extend Kernel"
+    default y
+    help
+      This option will enable extend Kernel of LiteOS.  Extend kernel include
+      cppsupport, cpup, etc. You can select one or some
+      of them.
+
+config KERNEL_BACKTRACE
+    bool "Enable Backtrace"
+    default n
+    depends on KERNEL_EXTKERNEL
+    help
+      If you wish to build LiteOS with support for backtrace.
+
+choice
+    prompt "Select Backtrace Type"
+    depends on KERNEL_BACKTRACE
+
+config BACKTRACE_TYPE_1
+    bool "1: Call stack analysis for cortex-m series by scanning the stack"
+    depends on ARCH_ARM && !ARCH_ARM9
+
+config BACKTRACE_TYPE_2
+    bool "2: Call stack analysis for risc-v by using frame pointer"
+    depends on ARCH_RISCV
+
+config BACKTRACE_TYPE_3
+    bool "3: Call stack analysis for risc-v by scanning the stack"
+    depends on ARCH_RISCV
+
+config BACKTRACE_TYPE_4
+    bool "4: Call stack analysis for xtensa by scanning the stack"
+    depends on ARCH_XTENSA
+
+config BACKTRACE_TYPE_5
+    bool "5: Call stack analysis for c-sky by scanning the stack"
+    depends on ARCH_CSKY
+
+config BACKTRACE_TYPE_6
+    bool "6: Call stack analysis for arm9 by scanning the stack"
+    depends on ARCH_ARM9
+
+endchoice
+
+config BACKTRACE_TYPE
+    int
+    default 0 if ! KERNEL_BACKTRACE
+    default 1 if BACKTRACE_TYPE_1
+    default 2 if BACKTRACE_TYPE_2
+    default 3 if BACKTRACE_TYPE_3
+    default 4 if BACKTRACE_TYPE_4
+    default 5 if BACKTRACE_TYPE_5
+    default 6 if BACKTRACE_TYPE_6
+
+config BACKTRACE_DEPTH
+    int "Backtrace depth"
+    default 15
+    depends on KERNEL_BACKTRACE
+
+config KERNEL_CPPSUPPORT
+    bool "Enable C++ Support"
+    default n
+    depends on KERNEL_EXTKERNEL
+    help
+      If you wish to build LiteOS with support for C++.
+
+rsource "components/signal/Kconfig"
+
+config BASE_CORE_CPUP
+    bool
+    default n
+
+config KERNEL_CPUP
+    bool "Enable Cpup"
+    default n
+    depends on KERNEL_EXTKERNEL
+    select BASE_CORE_CPUP
+    help
+      If you wish to build LiteOS with support for cpup.
+
+config CPUP_INCLUDE_IRQ
+    bool "Enable Cpup include irq"
+    default y
+    depends on KERNEL_CPUP
+    help
+      If you wish to include irq usage for cpup.
+
+config DYNLINK
+    bool "Enable Dynamic Link Feature"
+    default n
+    depends on KERNEL_EXTKERNEL && ARCH_ARM
+    help
+      If you wish to build LiteOS with support for dynamic link.
+
+config KERNEL_PM
+    bool "Enable Power Management"
+    default n
+    depends on KERNEL_EXTKERNEL
+    help
+      Configuration item for low power frame tailoring.
+      If you wish to build LiteOS with support for power management.
+
+config KERNEL_PM_TASK_PTIORITY
+    int "Power Management Task Priority"
+    default 1
+    range 1 31
+    depends on KERNEL_PM
+    help
+      Configuration item for priority of low-power task.
+
+config KERNEL_PM_TASK_STACKSIZE
+    int "Power Management Task Stack Size"
+    default 1024
+    depends on KERNEL_PM
+    help
+      Configuration item for stack size of low-power task.
+
+config KERNEL_PM_DEBUG
+    bool "Power Management Debug"
+    default n
+    depends on KERNEL_PM
+    help
+      Configuration item for low power frame debug tailoring.
+
+config DEBUG_HOOK
+    bool
+    default n
+
+config PLATFORM_EXC
+    bool "Enable Hook Feature"
+    default n
+    depends on KERNEL_EXTKERNEL
+    select DEBUG_HOOK
+
+config KERNEL_LMK
+    bool "Enable Low Memory Killer"
+    default n
+    depends on KERNEL_EXTKERNEL
+    help
+      Configuration item for low momery killer tailoring.
+      If you wish to build LiteOS with support for low memory killer.
+
+config KERNEL_LMK_DEBUG
+    bool "Low Memory Killer Debug"
+    default n
+    depends on KERNEL_LMK
+    help
+      Configuration item forlow memory killer debug tailoring.
+
+######################### config options of trace #########################
+source "components/trace/Kconfig"
+
+######################### config options of lms #########################
+source "components/lms/Kconfig"
+
+endmenu
+
+######################### config options of lib ########################
+menu "Lib"
+config LIB_LIBC
+    bool "Enable Libc"
+    default y
+    help
+      Answer Y to enable libc for full code.
+
+endmenu
+
+
+######################### config options of compatibility ##############
+menu "Compat"
+
+rsource "kal/Kconfig"
+
+endmenu
+
+######################## config options of filesystem ##################
+menu "FileSystem"
+
+rsource "components/fs/Kconfig"
+
+endmenu
+
+######################## config options of net ############################
+menu "Net"
+config NET_LWIP
+    bool "Enable Lwip"
+    default n
+    select NET_LWIP_SACK
+
+    help
+      Answer Y to enable LiteOS support lwip.
+
+config NET_LWIP_SACK
+    bool
+    default n
+
+endmenu
+
+######################## config options of debug ########################
+menu "Debug"
+config GDB
+    bool "Enable gdb functions"
+    default n
+    help
+      Answer Y to enable gdb functions.
+
+config PLATFORM_ADAPT
+    bool "Enable Os_adapt"
+    default y
+    help
+      Answer Y to add os_adapt.c to LiteOS.
+
+config ENABLE_OOM_LOOP_TASK
+    bool "Enable Oom loop task"
+    default n
+    depends on KERNEL_VM
+    help
+      Answer Y to enable oom loop kthread to check system out of memory.
+
+config DO_ALIGN
+    bool "Enable do align for hi3518e"
+    default y
+    depends on PLATFORM_HI3518EV200
+    help
+      Answer Y to enable do align for hi3518e.
+
+
+config ENABLE_MAGICKEY
+    bool "Enable MAGIC KEY"
+    default y
+    help
+      Answer Y to enable LiteOS Magic key.
+        ctrl + r : Magic key check switch;
+        ctrl + z : Show all magic op key;
+        ctrl + t : Show task information;
+        ctrl + p : System panic;
+        ctrl + e : Check system memory pool.
+
+config THUMB
+    bool "Enable Thumb"
+    default n
+    depends on ARCH_ARM
+    help
+      Answer Y to build thumb version.  This will make LiteOS smaller.
+
+config PLATFORM_DVFS
+    bool "Enable Dvfs"
+    default n
+    depends on  COMPAT_LINUXKPI
+    help
+      Answer Y to enable LiteOS support dynamic voltage and frequency scaling feature for
+      low power consumption.
+
+config SAVE_EXCINFO
+    bool "Enable Saving Exception Information"
+    default n
+    help
+      Answer Y to enable LiteOS support saving exception information to storage medium.
+
+config DEBUG_VERSION
+    bool "Enable a Debug Version"
+    default y
+    help
+      If you do not select this option that means you enable a release version for LiteOS.
+      It also means you do not want to use debug modules, like shell,telnet,tftp,nfs and
+      memory check, etc.
+      If you select this option that means you enable a debug version for LiteOS.
+      That means you want a opposite behaviour compared to release version.
+
+config DEBUG_KERNEL
+    bool "Enable Debug LiteOS Kernel Resource"
+    default n
+    depends on DEBUG_VERSION
+    help
+      If you select this option that means you enable debugging kernel resource.
+      It also means you want to get queue, mutex, semaphore, memory debug information.
+      That means you want a opposite behaviour compared to release version.
+
+config DEBUG_QUEUE
+    bool "Enable Queue Debugging"
+    default n
+    depends on DEBUG_KERNEL
+    help
+      Answer Y to enable debug queue.
+
+config DEBUG_DEADLOCK
+    bool "Enable Mutex Deadlock Debugging"
+    default n
+    depends on DEBUG_KERNEL
+    help
+      Answer Y to enable debug mutex deadlock.
+
+config DEBUG_SEMAPHORE
+    bool "Enable Semaphore Debugging"
+    default n
+    depends on DEBUG_KERNEL
+    help
+      Answer Y to enable debug semaphore.
+
+source "components/shell/Kconfig"
+config NET_LWIP_SACK_TFTP
+    bool "Enable Tftp"
+    default y
+    depends on SHELL && NET_LWIP_SACK && DEBUG_VERSION
+    help
+      Answer Y to enable LiteOS support tftp cmd and tftp tool.
+osource "net/telnet/Kconfig"
+config SCHED_DEBUG
+    bool "Enable sched debug Feature"
+    default n
+    depends on DEBUG_VERSION
+    help
+      If you wish to build LiteOS with support for sched debug.
+
+config USER_INIT_DEBUG
+    bool "Enable user init Debug"
+    default n
+    depends on DEBUG_VERSION
+
+config SHELL_CMD_DEBUG
+    bool "Enable shell cmd Debug"
+    default n
+    depends on DEBUG_VERSION && SHELL
+
+config USB_DEBUG
+    bool "Enable USB Debug"
+    default n
+    depends on SHELL && DRIVERS_USB && DEBUG_VERSION
+    help
+      Answer Y to enable LiteOS support usb debug.
+      use shell command to open the specified debug level print.
+config MEM_DEBUG
+    bool "Enable MEM Debug"
+    default n
+    depends on DEBUG_VERSION
+    help
+      Answer Y to enable LiteOS support mem debug.
+
+config MEM_LEAKCHECK
+    bool "Enable Function call stack of Mem operation recorded"
+    default n
+    depends on DEBUG_VERSION && MEM_DEBUG
+    select KERNEL_BACKTRACE
+    help
+      Answer Y to enable record the LR of Function call stack of Mem operation, it can check the mem leak through the infomations of mem node.
+config BASE_MEM_NODE_INTEGRITY_CHECK
+    bool "Enable integrity check or not"
+    default n
+    depends on DEBUG_VERSION && MEM_DEBUG
+config MEM_WATERLINE
+    bool "Enable memory pool waterline or not"
+    default n
+    depends on DEBUG_VERSION && MEM_DEBUG
+
+config VM_OVERLAP_CHECK
+    bool "Enable VM overlap check or not"
+    default n
+    depends on DEBUG_VERSION && MEM_DEBUG
+    help
+      Answer Y to enable vm overlap check.
+
+endmenu
+
+######################## config options os drivers ########################
+menu "Driver"
+source "drivers/Kconfig"
+endmenu
+
+######################## config options os security #######################
+menu "Security"
+osource "security/Kconfig"
+config SECURE_TRUSTZONE
+    bool "Enable ARM TrustZone"
+    default n
+    depends on ARCH_ARM
+config SECURE_HEAP_SIZE
+    int "TrustZone Heap Size (bytes)"
+    default 2048
+    depends on SECURE_TRUSTZONE
+config SECURE_STACK_DEFAULT_SIZE
+    int "TrustZone Stack Size (bytes)"
+    default 512
+    depends on SECURE_TRUSTZONE
+    help
+      The secure stack must be allocated before the task calls non-secure functions.
+endmenu
+
+menu "Test"
+config TEST
+    bool
+    default n
+config KERNEL_TEST
+    bool "Enable Kernel Test"
+    default n
+    select TEST
+config KERNEL_TEST_FULL
+    bool "Full Kernel Test"
+    default n
+    depends on KERNEL_TEST
+endmenu
+
+menu "Stack Smashing Protector (SSP) Compiler Feature"
+
+choice
+    prompt "Enable stack buffer overflow detection"
+    default  CC_STACKPROTECTOR_STRONG
+    ---help---
+    This option turns on the -fstack-protector GCC feature. This
+    feature puts, at the beginning of functions, a canary value on
+    the stack just before the return address, and validates
+    the value just before actually returning.  Stack based buffer
+    overflows (that need to overwrite this return address) now also
+    overwrite the canary, which gets detected and the attack is then
+    neutralized via a kernel panic.
+
+    This feature requires gcc version 4.2 or above, or a distribution
+    gcc with the feature backported. Older versions are automatically
+    detected and for those versions, this configuration option is
+    ignored. (and a warning is printed during bootup)
+
+config CC_NO_STACKPROTECTOR
+    bool "-fno-stack-protector"
+
+config CC_STACKPROTECTOR
+    bool "-fstack-protector"
+
+config CC_STACKPROTECTOR_STRONG
+    bool "-fstack-protector-strong"
+
+config CC_STACKPROTECTOR_ALL
+    bool "-fstack-protector-all"
+
+endchoice
+
+endmenu

LICENSE

@@ -0,0 +1,28 @@
+Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+   conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+   of conditions and the following disclaimer in the documentation and/or other materials
+   provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be used
+   to endorse or promote products derived from this software without specific prior written
+   permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Makefile

@@ -0,0 +1,122 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+LITEOSTOPDIR := $(realpath $(dir $(lastword $(MAKEFILE_LIST))))
+export LITEOSTOPDIR
+
+LITEOS_TARGET = liteos
+HIDE := @
+KCONFIG_CMDS := $(notdir $(wildcard $(dir $(shell which menuconfig))*config))
+
+ohos_kernel ?= liteos_m
+$(foreach line,$(shell hb env | sed 's/\[OHOS INFO\]/ohos/g;s/ /_/g;s/:_/=/g' || true),$(eval $(line)))
+ifneq ($(ohos_kernel),liteos_m)
+$(error The selected product ($(ohos_product)) is not a liteos_m kernel type product)
+endif
+
+ifeq ($(PRODUCT_PATH),)
+PRODUCT_PATH:=$(ohos_product_path)
+endif
+
+ifeq ($(DEVICE_PATH),)
+DEVICE_PATH:=$(ohos_device_path)
+endif
+
+ifeq ($(BOARD_COMPANY),)
+BOARD_COMPANY:=$(ohos_device_company)
+endif
+
+ifeq ($(TEE:1=y),y)
+tee = _tee
+endif
+ifeq ($(RELEASE:1=y),y)
+CONFIG ?= $(PRODUCT_PATH)/kernel_configs/release$(tee).config
+else
+CONFIG ?= $(PRODUCT_PATH)/kernel_configs/debug$(tee).config
+endif
+
+KCONFIG_CONFIG ?= $(CONFIG)
+LITEOS_MENUCONFIG_H ?= $(LITEOSTOPDIR)/config.h
+LITEOS_CONFIG_FILE ?= $(LITEOSTOPDIR)/.config
+
+# export los_config.mk related environment variables
+export LITEOS_MENUCONFIG_H
+export LITEOS_CONFIG_FILE
+export BOARD_COMPANY
+export DEVICE_PATH
+export PRODUCT_PATH
+
+# export kconfig related environment variables
+export CONFIG_=LOSCFG_
+export srctree=$(LITEOSTOPDIR)
+
+-include $(LITEOS_CONFIG_FILE)
+
+define HELP =
+Usage: make [TARGET]... [PARAMETER=VALUE]...
+
+Targets:
+    help:       display this help and exit
+    clean:      clean compiled objects
+    cleanall:   clean all build outputs
+    all:        do build (Default target)
+    update_config:  update product kernel config (use menuconfig)
+    xxconfig:   invoke xxconfig command of kconfiglib (xxconfig is one of $(KCONFIG_CMDS))
+
+Parameters:
+    TEE:        boolean value(1 or y for true), enable tee
+    RELEASE:    boolean value(1 or y for true), build release version
+    CONFIG:     kernel config file to be use
+    args:       arguments for xxconfig command
+endef
+export HELP
+
+all:
+	$(HIDE)hb build -f --gn-args "liteos_kernel_only=true liteos_name=\"$(LITEOS_TARGET)\""
+
+help:
+	$(HIDE)echo "$$HELP"
+
+$(filter-out menuconfig,$(KCONFIG_CMDS)):
+	$(HIDE)$@ $(args)
+
+$(LITEOS_CONFIG_FILE): $(KCONFIG_CONFIG)
+	$(HIDE)env KCONFIG_CONFIG=$< genconfig --config-out $@ --header-path $(LITEOS_MENUCONFIG_H)
+
+update_config menuconfig:
+	$(HIDE)test -f "$(CONFIG)" && cp -v "$(CONFIG)" .config && menuconfig $(args) && savedefconfig --out "$(CONFIG)"
+
+clean:
+	$(HIDE)hb clean
+	$(HIDE)echo "clean $(LOSCFG_PLATFORM) finish"
+
+cleanall: clean
+	$(HIDE)echo "clean all done"
+
+.PHONY: all clean cleanall help update_config $(KCONFIG_CMDS) $(KCONFIG_CONFIG)

NOTICE

@@ -0,0 +1,8 @@
+1、In kernel/liteos_m/targets/cortex-m4_stm32f429ig_fire-challenger_iar directory, the files including main.c,
+target_config.h, dprintf.c, board/iar_stm32f429ig_fire-challenger.c and board/iar_stm32f429ig_fire-challenger.h,
+are under the terms of the licence: kernel/liteos_m/LICENSE file,
+and other files are under the terms of the licence: kernel/liteos_m/targets/cortex-m4_stm32f429ig_fire-challenger_iar/LICENSE.pdf file.
+
+2、In kernel/liteos_m/targets/cortex-m7_nucleo_f767zi_gcc directory, the files including target_config.h,
+Core/Inc/task_sample.h and Core/Src/task_sample.c, are under the terms of the licence: kernel/liteos_m/LICENSE file,
+and other files are under the terms of the licence: kernel/liteos_m/targets/cortex-m7_nucleo_f767zi_gcc/LICENSE.pdf file.

OAT.xml

@@ -0,0 +1,86 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Copyright (c) 2021 Huawei Device Co., Ltd.
+
+     Licensed under the Apache License, Version 2.0 (the "License");
+     you may not use this file except in compliance with the License.
+     You may obtain a copy of the License at
+
+          http://www.apache.org/licenses/LICENSE-2.0
+
+     Unless required by applicable law or agreed to in writing, software
+     distributed under the License is distributed on an "AS IS" BASIS,
+     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+     See the License for the specific language governing permissions and
+     limitations under the License.
+
+    This is the configuration file template for OpenHarmony OSS Audit Tool, please copy it to your project root dir and modify it refer to OpenHarmony/tools_oat/README.
+
+-->
+
+<configuration>
+    <oatconfig>
+        <licensefile></licensefile>
+        <policylist>
+            <policy name="projectPolicy" desc="">
+                <policyitem type="copyright" name="Huawei Technologies Co., Ltd. All rights reserved." path=".*" desc="original liteos copyright"/>
+                <policyitem type="license" name="BSD-3-Clause" path=".*" desc="Liteos kernel use bsd3 license"/>
+                <policyitem type="license" name="BSD-3-Clause" path=".*" desc="Liteos kernel use bsd3 license"/>
+            </policy>
+        </policylist>
+        <filefilterlist>
+            <filefilter name="defaultFilter" desc="文件属于FreeBSD仓库软连接，本仓库屏蔽告警，在FreeBSD仓库进行处理">
+                <filteritem type="filepath" name="arch/risc-v/nuclei/gcc/nmsis/Library/.*" desc="文件属于三方芯片的二进制代码，属于社区贡献，不用提供额外的说明"/>
+                <filteritem type="filepath" name="targets/riscv_nuclei_demo_soc_gcc/.*" desc="文件属于nuclei三方芯片的源代码，文件头说明跟随liteos_m/LICENSE，不用额外说明"/>
+                <filteritem type="filepath" name="targets/riscv_nuclei_gd32vf103_soc_gcc/.*" desc="文件属于nuclei三方芯片的源代码，文件头说明跟随liteos_m/LICENSE，不用额外说明"/>
+                <filteritem type="filepath" name="NOTICE" desc="NOTICE文件"/>
+                <filteritem type="filepath" name="arch/risc-v/nuclei" desc="该文件的license为apache 2.0符合"/>
+            </filefilter>
+            <filefilter name="defaultFilter" desc="Files not to check">
+                <!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
+            </filefilter>
+            <filefilter name="defaultPolicyFilter" desc="Filters for compatibility，license header policies">
+                <!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
+            </filefilter>
+            <filefilter name="copyrightPolicyFilter" desc="Filters for copyright header policies">
+                <!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
+            </filefilter>
+            <filefilter name="licenseFileNamePolicyFilter" desc="Filters for LICENSE file policies">
+                <!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
+            </filefilter>
+            <filefilter name="readmeFileNamePolicyFilter" desc="Filters for README file policies">
+                <!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
+            </filefilter>
+            <filefilter name="readmeOpenSourcefileNamePolicyFilter" desc="Filters for README.OpenSource file policies">
+                <!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
+            </filefilter>
+            <filefilter name="binaryFileTypePolicyFilter" desc="Filters for binary file policies">
+                <!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
+                <!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
+            </filefilter>
+
+        </filefilterlist>
+        <licensematcherlist>
+            <!--licensematcher name="uvwxyz License" desc="If the scanning result is InvalidLicense, you can define matching rules here. Note that quotation marks must be escaped.">
+                <licensetext name="
+                    uvwxyz license textA xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+                " desc=""/>
+                <licensetext name="
+                    uvwxyz license textB xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+                " desc=""/>
+            </licensematcher-->
+        </licensematcherlist>
+    </oatconfig>
+</configuration>

README.md

@@ -0,0 +1,134 @@
+# LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a>
+
+-   [Introduction](#section11660541593)
+-   [Directory Structure](#section161941989596)
+-   [Constraints](#section119744591305)
+-   [Usage](#section3732185231214)
+-   [Contribution](#section1371123476307)
+-   [Repositories Involved](#section1371113476307)
+
+## Introduction<a name="section11660541593"></a>
+
+OpenHarmony LiteOS-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It features small footprint, low power consumption, and high performance. It has a simple code structure, including the minimum kernel function set, kernel abstraction layer, optional components, and project directory. The LiteOS-M kernel is divided into the hardware layer and hardware-irrelevant layers. The hardware layer provides a unified hardware abstraction layer (HAL) interface for easier hardware adaptation. A range of compilation toolchains can be used with different chip architectures to meet the expansion of diversified hardware and compilation toolchains in the Artificial Intelligence of Things (AIoT) field.
+**Figure1** shows the architecture of the LiteOS-M kernel.
+
+**Figure 1** Architecture of the OpenHarmony LiteOS-M kernel<a name="fig0865152210223"></a>
+
+![](figures/architecture-of-openharmony-the-liteos-cortex-m-kernel.png "OpenHarmony-LiteOS-M Kernel Architecture")
+
+## Directory Structure<a name="section161941989596"></a>
+
+The directory structure is as follows. For more details, see [arch_spec.md](arch_spec.md).
+
+```
+/kernel/liteos_m
+├── arch                 # Code of the kernel instruction architecture layer
+│   ├── arm              # Code of the ARM32 architecture
+│   │   ├── arm9         # Code of the ARM9 architecture
+│   │   ├── cortex-m3    # Code of the cortex-m3 architecture
+│   │   ├── cortex-m33   # Code of the cortex-m33 architecture
+│   │   ├── cortex-m4    # Code of the cortex-m4 architecture
+│   │   ├── cortex-m7    # Code of the cortex-m7 architecture
+│   │   └── include      # Arm architecture public header file directory
+│   ├── csky             # Code of the csky architecture
+│   │   └── v2           # Code of the csky v2 architecture
+│   ├── include          # APIs exposed externally
+│   ├── risc-v           # Code of the risc-v architecture
+│   │   ├── nuclei       # Code of the nuclei system technology risc-v architecture
+│   │   └── riscv32      # Code of the risc-v architecture
+│   └── xtensa           # Code of the xtensa architecture
+│       └── lx6          # Code of the lx6 xtensa architecture
+├── components           # Optional components
+│   ├── backtrace        # Backtrace support
+│   ├── cppsupport       # C++ support
+│   ├── cpup             # CPU percent (CPUP)
+│   ├── dynlink          # Dynamic loading and linking
+│   ├── exchook          # Exception hooks
+│   ├── fs               # File systems
+│   ├── lmk              # Low memory killer functions
+│   ├── lms              # Lite memory sanitizer functions
+│   ├── net              # Networking functions
+│   ├── power            # Power management
+│   ├── shell            # Shell function
+│   ├── fs               # File systems
+│   └── trace            # Trace tool
+├── drivers              # driver Kconfig
+├── kal                  # Kernel abstraction layer
+│   ├── cmsis            # CMSIS API support
+│   └── posix            # POSIX API support
+├── kernel               # Minimum kernel function set
+│   ├── include          # APIs exposed externally
+│   └── src              # Source code of the minimum kernel function set
+├── targets              # Board-level projects
+├── testsuites           # Kernel testsuites
+├── tools                # Kernel tools
+├── utils                # Common directory
+```
+
+## Constraints<a name="section119744591305"></a>
+
+OpenHarmony LiteOS-M supports only C and C++.
+
+Applicable architecture: See the directory structure for the arch layer.
+
+As for dynamic loading module, the shared library to be loaded needs signature verification or source restriction to ensure security.
+
+## Usage<a name="section3732185231214"></a>
+
+The OpenHarmony LiteOS-M kernel build system is a modular build system based on Generate Ninja (GN) and Ninja. It supports module-based configuration, tailoring, and assembling, and helps you build custom products. This document describes how to build a LiteOS-M project based on GN and Ninja. For details about the methods such as GCC+gn, IAR, and Keil MDK, visit the community websites.
+
+### Setting Up the Environment
+
+Before setting up the environment for a development board, you must set up the basic system environment for OpenHarmony first. The basic system environment includes the OpenHarmony build environment and development environment. For details, see [Setting Up Development Environment](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/quick-start/quickstart-lite-env-setup.md).
+
+### Obtaining the OpenHarmony Source Code
+
+For details about how to obtain the source code, see [Source Code Acquisition](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/get-code/sourcecode-acquire.md). This document assumes that the clone directory is `~/openHarmony` after the complete OpenHarmony repository code is obtained.
+
+### Example projects that are already supported
+
+Qemu simulator: `arm_mps2_an386、esp32、riscv32_virt、SmartL_E802`, For details about how to compile and run, see [qemu guide](https://gitee.com/openharmony/device_qemu)
+
+Bestechnic: `bes2600`, For details about how to compile and run, see [Bestechnic developer guide](https://gitee.com/openharmony/device_soc_bestechnic)
+
+### Community Porting Project Links
+
+The LiteOS-M kernel porting projects for specific development boards are provided by community developers. The following provides the links to these projects. If you have porting projects for more development boards, you can provide your links to share your projects.
+
+-   Cortex-M3:
+
+    - STM32F103 https://gitee.com/rtos_lover/stm32f103_simulator_keil
+
+        This repository provides the Keil project code for building the OpenHarmony LiteOS-M kernel based on the STM32F103 chip architecture. This code supports build in Keil MDK mode.
+
+-   Cortex-M4:
+
+    - STM32F429IGTb https://gitee.com/harylee/stm32f429ig_firechallenger
+
+        This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the STM32F429IGTb development board. The code supports build in Ninja, GCC, and IAR modes.
+
+-   Cortex-M7:
+
+    - Nucleo-F767ZI https://gitee.com/harylee/nucleo_f767zi
+
+        This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the Nucleo-F767ZI development board. The code supports build in Ninja, GCC, and IAR modes.
+
+## Contribution<a name="section1371123476307"></a>
+
+[How to involve](https://gitee.com/openharmony/docs/blob/HEAD/en/contribute/contribution.md)
+
+[Commit message spec](https://gitee.com/openharmony/kernel_liteos_m/wikis/Commit%20message%E8%A7%84%E8%8C%83)
+
+[Liteos-M kernel coding style guide](https://gitee.com/openharmony/kernel_liteos_m/wikis/OpenHarmony%E8%BD%BB%E5%86%85%E6%A0%B8%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83)
+
+How to contribute a chip based on Liteos-M kernel:
+
+[ Board-Level Directory Specifications](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-chip-board-overview.md)
+
+[Mini System SoC Porting Guide](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-minichip.md)
+
+## Repositories Involved<a name="section1371113476307"></a>
+
+[Kernel Subsystem](https://gitee.com/openharmony/docs/blob/HEAD/en/readme/kernel-subsystem.md)
+
+**kernel\_liteos\_m**

README_zh.md

@@ -0,0 +1,135 @@
+# LiteOS-M内核<a name="ZH-CN_TOPIC_0000001096757661"></a>
+
+-   [简介](#section11660541593)
+-   [目录](#section161941989596)
+-   [约束](#section119744591305)
+-   [使用说明](#section3732185231214)
+-   [贡献](#section1371123476307)
+-   [相关仓](#section1371113476307)
+
+## 简介<a name="section11660541593"></a>
+
+OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系统内核，具有小体积、低功耗、高性能的特点，其代码结构简单，主要包括内核最小功能集、内核抽象层、可选组件以及工程目录等，分为硬件相关层以及硬件无关层，硬件相关层提供统一的HAL（Hardware Abstraction Layer）接口，提升硬件易适配性，不同编译工具链和芯片架构的组合分类，满足AIoT类型丰富的硬件和编译工具链的拓展。其架构图如图1所示：
+
+**图 1**  OpenHarmony LiteOS-M核内核架构图<a name="fig0865152210223"></a>  
+![](figures/OpenHarmony-LiteOS-M核内核架构图.png "OpenHarmony-LiteOS-M核内核架构图")
+
+## 目录<a name="section161941989596"></a>
+
+目录结构如下，详细目录请参考[arch_spec_zh.md](arch_spec_zh.md)。
+
+```
+/kernel/liteos_m
+├── arch                 # 内核指令架构层目录
+│   ├── arm              # arm 架构代码
+│   │   ├── arm9         # arm9 架构代码
+│   │   ├── cortex-m3    # cortex-m3架构代码
+│   │   ├── cortex-m33   # cortex-m33架构代码
+│   │   ├── cortex-m4    # cortex-m4架构代码
+│   │   ├── cortex-m7    # cortex-m7架构代码
+│   │   └── include      # arm架构公共头文件目录
+│   ├── csky             # csky架构代码
+│   │   └── v2           # csky v2架构代码
+│   ├── include          # 架构层对外接口存放目录
+│   ├── risc-v           # risc-v 架构
+│   │   ├── nuclei       # 芯来科技risc-v架构代码
+│   │   └── riscv32      # risc-v官方通用架构代码
+│   └── xtensa           # xtensa 架构代码
+│       └── lx6          # xtensa lx6架构代码
+├── components           # 可选组件
+│   ├── backtrace        # 栈回溯功能
+│   ├── cppsupport       # C++支持
+│   ├── cpup             # CPUP功能
+│   ├── dynlink          # 动态加载与链接
+│   ├── exchook          # 异常钩子
+│   ├── fs               # 文件系统
+│   ├── lmk              # Low memory killer 机制
+│   ├── lms              # Lite memory sanitizer 机制
+│   ├── net              # Network功能
+│   ├── power            # 低功耗管理
+│   ├── shell            # shell功能
+│   └── trace            # trace 工具
+├── drivers              # 驱动框架Kconfig
+├── kal                  # 内核抽象层
+│   ├── cmsis            # cmsis标准接口支持
+│   └── posix            # posix标准接口支持
+├── kernel               # 内核最小功能集支持
+│   ├── include          # 对外接口存放目录
+│   └── src              # 内核最小功能集源码
+├── targets              # 板级工程目录
+├── testsuites           # 内核测试用例
+├── tools                # 内核工具
+├── utils                # 通用公共目录
+```
+
+## 约束<a name="section119744591305"></a>
+
+开发语言：C/C++；
+
+适用架构：详见目录结构arch层。
+
+动态加载模块：待加载的共享库需要验签或者限制来源，确保安全性。
+
+## 使用说明<a name="section3732185231214"></a>
+
+OpenHarmony
+LiteOS-M内核的编译构建系统是一个基于gn和ninja的组件化构建系统，支持按组件配置、裁剪和拼装，按需构建出定制化的产品。本文主要介绍如何基于gn和ninja编译LiteOS-M工程，GCC+gn、IAR、Keil MDK等编译方式可以参考社区爱好者贡献的站点。
+
+### 搭建系统基础环境
+
+在搭建各个开发板环境前，需要完成OpenHarmony系统基础环境搭建。系统基础环境主要是指OpenHarmony的编译环境和开发环境，详细介绍请参考官方站点[开发环境准备](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/quick-start/quickstart-lite-env-setup.md)。开发者需要根据环境搭建文档完成环境搭建。
+
+### 获取OpenHarmony源码
+
+详细的源码获取方式，请见[源码获取](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/get-code/sourcecode-acquire.md)。获取OpenHarmony完整仓代码后，假设克隆目录为`~/openHarmony`。
+
+### 已支持的示例工程
+
+Qemu模拟器: `arm_mps2_an386、esp32、riscv32_virt、SmartL_E802`, 编译运行详见: [Qemu指导](https://gitee.com/openharmony/device_qemu)
+
+恒玄科技: `bes2600`, 编译运行详见: [恒玄开发指导](https://gitee.com/openharmony/device_soc_bestechnic)
+
+### 社区移植工程链接
+
+LiteOS-M内核移植的具体开发板的工程由社区开发者提供，可以访问社区开发者代码仓获取。如果您移植支持了更多开发板，可以提供链接给我们进行社区分享。
+
+-   cortex-m3：
+
+    - STM32F103   https://gitee.com/rtos_lover/stm32f103_simulator_keil
+
+        该仓包含OpenHarmony LiteOS-M内核基于STM32F103芯片架构构建的Keil工程，支持Keil MDK方式进行编译。
+
+-   cortex-m4：
+
+    - 野火挑战者STM32F429IGTb   https://gitee.com/harylee/stm32f429ig_firechallenger
+
+        该仓包含OpenHarmony LiteOS-M内核移植支持`野火挑战者STM32F429IGTb`开发板的工程代码，支持Ninja、GCC、IAR等方式进行编译。
+
+-   cortex-m7：
+
+    - Nucleo-F767ZI   https://gitee.com/harylee/nucleo_f767zi
+
+        该仓包含OpenHarmony LiteOS-M内核移植支持`Nucleo-F767ZI`开发板的工程代码，支持Ninja、GCC、IAR等方式进行编译。
+
+## 贡献<a name="section1371123476307"></a>
+
+[如何贡献](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/contribute/%E5%8F%82%E4%B8%8E%E8%B4%A1%E7%8C%AE.md)
+
+[Commit message规范](https://gitee.com/openharmony/kernel_liteos_m/wikis/Commit%20message%E8%A7%84%E8%8C%83)
+
+[Liteos-M 内核编码规范](https://gitee.com/openharmony/kernel_liteos_m/wikis/OpenHarmony%E8%BD%BB%E5%86%85%E6%A0%B8%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83)
+
+如何基于Liteos-M内核贡献一款芯片:
+
+[板级目录规范](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/porting/porting-chip-board-overview.md)
+
+[轻量系统芯片移植指导](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/porting-minichip.md)
+
+[轻量系统芯片移植案例](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/porting-minichip-cases.md)
+
+## 相关仓<a name="section1371113476307"></a>
+
+[内核子系统](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/readme/%E5%86%85%E6%A0%B8%E5%AD%90%E7%B3%BB%E7%BB%9F.md)
+
+**kernel\_liteos\_m**
+

arch/BUILD.gn

@@ -1,50 +1,52 @@
-# Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
-# Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without modification,
-# are permitted provided that the following conditions are met:
-#
-# 1. Redistributions of source code must retain the above copyright notice, this list of
-#    conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright notice, this list
-#    of conditions and the following disclaimer in the documentation and/or other materials
-#    provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its contributors may be used
-#    to endorse or promote products derived from this software without specific prior written
-#    permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
-# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import("//build/lite/config/component/lite_component.gni")
-
-source_set("m4") {
-
-    sources = [
-        "arm/cortex-m/cortex-m4/los_dispatch_gcc.S",
-        "arm/cortex-m/cortex-m4/los_hw_exc_gcc.S",
-        "arm/cortex-m/cortex-m4/los_hw_sr_gcc.s",
-        "arm/cortex-m/cortex-m4/los_exc.c",
-        "arm/cortex-m/src/los_hw.c",
-        "arm/cortex-m/src/los_hw_tick.c",
-        "arm/cortex-m/src/los_hwi.c",
-    ]
-}
-
-lite_component("arch") {
-    features = [ 
-        ":m4"
-    ]
-
-}
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+config("arch_config") {
+  include_dirs = [ "include" ]
+}
+
+module_group("arch") {
+  modules = []
+  if ("$board_cpu" == "arm9" || "$board_cpu" == "cortex-m3" ||
+      "$board_cpu" == "cortex-m4" || "$board_cpu" == "cortex-m7" ||
+      "$board_cpu" == "cortex-m33" || "$board_cpu" == "cortex-m55") {
+    modules += [ "arm" ]
+  } else if ("$board_cpu" == "ck802" || "$board_cpu" == "e802") {
+    modules += [ "csky" ]
+  } else if ("$board_cpu" == "") {
+    if ("$board_arch" == "rv32imac" || "$board_arch" == "rv32imafdc") {
+      modules += [ "risc-v" ]
+    } else if ("$board" == "esp32") {
+      modules += [ "xtensa" ]
+    }
+  }
+  configs = [ ":arch_config" ]
+}

arch/Kconfig

@@ -0,0 +1,53 @@
+config ARCH_ARM
+   bool
+
+rsource "arm/Kconfig"
+
+config ARCH_CSKY
+   bool
+
+config ARCH_RISCV
+   bool
+
+config ARCH_RISCV32
+   bool
+   select ARCH_RISCV
+
+config ARCH_XTENSA
+   bool
+
+comment "Extra Configurations"
+
+config ARCH_FPU_DISABLE
+    bool "Disable Floating Pointer Unit"
+    default n
+    help
+      This option will bypass floating procedure in system.
+
+config ARCH_SECURE_MONITOR_MODE
+    bool "Run On Secure Monitor Mode"
+    default n
+    depends on ARCH_ARM_AARCH64
+    help
+      This option will make the system run on EL3.
+
+config ARCH_INTERRUPT_PREEMPTION
+    bool "Enable Interrupt Preemption"
+    default n
+    depends on ARCH_ARM_AARCH64
+    help
+      This option will support high priority interrupt preemption.
+
+config IRQ_USE_STANDALONE_STACK
+    bool "Use Interrupt Stack"
+    default y
+    depends on ARCH_ARM_AARCH64 || ARCH_ARM_AARCH32
+    help
+      This option will support using standalone interrupt stack.
+
+config ARCH_UNALIGNED_EXC
+    bool "Enable Unaligned Exception"
+    default y
+    depends on ARCH_ARM
+    help
+     This option will enable unaligned exception.

arch/arm/BUILD.gn

@@ -1,40 +1,39 @@
-# Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
-# Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without modification,
-# are permitted provided that the following conditions are met:
-#
-# 1. Redistributions of source code must retain the above copyright notice, this list of
-#    conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright notice, this list
-#    of conditions and the following disclaimer in the documentation and/or other materials
-#    provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its contributors may be used
-#    to endorse or promote products derived from this software without specific prior written
-#    permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
-# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-static_library("cpup") {
-
-    sources = [
-        "cpup/los_cpup.c",
-        "cppsupport/los_cppsupport.c"
-    ]
-
-    include_dirs = [
-        "include"
-    ]
-}
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+config("arm_config") {
+  include_dirs = [ "include" ]
+}
+
+module_group("arm") {
+  modules = [ "$board_cpu/gcc" ]
+  configs = [ ":arm_config" ]
+}

arch/arm/Kconfig

@@ -0,0 +1,117 @@
+# ARM Architecture
+
+#
+# ARM has 32-bit(Aarch32) and 64-bit(Aarch64) implementations
+#
+config ARCH_ARM_AARCH32
+    bool
+    select ARCH_ARM
+    help
+      32-bit ARM architecture implementations, Except the M-profile.
+      It is not limited to ARMv7-A but also ARMv7-R, ARMv8-A 32-bit and etc.
+
+#
+# Architecture Versions
+#
+config ARCH_ARM_V7M
+    bool
+
+config ARCH_ARM_V5TE
+    bool
+
+config ARCH_ARM_VER
+    string
+    default "armv7-m" if ARCH_ARM_V7M
+    default "armv5te" if ARCH_ARM_V5TE
+
+#
+# VFP Hardware
+#
+config ARCH_FPU_VFP_V3
+    bool
+    help
+      An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
+      VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support code.
+
+config ARCH_FPU_VFP_V4
+    bool
+    help
+      An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
+      VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support code.
+      VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to the features of VFPv3.
+
+config ARCH_FPU_VFP_D16
+    bool
+    depends on ARCH_ARM_AARCH32
+    help
+      VPU implemented with 16 doubleword registers (16 x 64-bit).
+
+config ARCH_FPU_VFP_D32
+    bool
+    depends on ARCH_ARM_AARCH32
+    help
+      VPU implemented with 32 doubleword registers (32 x 64-bit).
+
+config ARCH_FPU_VFP_NEON
+    bool
+    help
+      Advanced SIMD extension (NEON) support.
+
+config ARCH_FPU
+    string
+    default "vfpv3"       if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D32
+    default "vfpv3-d16"   if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D16
+    default "neon-vfpv4"  if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32 && ARCH_FPU_VFP_NEON
+    default "vfpv4"       if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32
+    default "vfpv4-d16"   if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D16
+
+#
+# Supported Processor Cores
+#
+config ARCH_CORTEX_M3
+    bool
+    select ARCH_ARM_V7M
+    select ARCH_ARM_AARCH32
+
+config ARCH_CORTEX_M4
+    bool
+    select ARCH_ARM_V7M
+    select ARCH_ARM_AARCH32
+
+config ARCH_CORTEX_M7
+    bool
+    select ARCH_ARM_V7M
+    select ARCH_ARM_AARCH32
+    select ARCH_FPU_VFP_V4
+    select ARCH_FPU_VFP_D32
+    select ARCH_FPU_VFP_NEON
+
+config ARCH_CORTEX_M33
+    bool
+    select ARCH_ARM_V7M
+    select ARCH_ARM_AARCH32
+    select ARCH_FPU_VFP_V4
+    select ARCH_FPU_VFP_D32
+    select ARCH_FPU_VFP_NEON
+
+config ARCH_CORTEX_M55
+    bool
+    select ARCH_ARM_V7M
+    select ARCH_ARM_AARCH32
+    select ARCH_FPU_VFP_V4
+    select ARCH_FPU_VFP_D32
+    select ARCH_FPU_VFP_NEON
+
+config ARCH_ARM9
+    bool
+    select ARCH_ARM_V5TE
+    select ARCH_ARM_AARCH32
+
+config ARCH_CPU
+    string
+    default "cortex-m3" if ARCH_CORTEX_M3
+    default "cortex-m4" if ARCH_CORTEX_M4
+    default "cortex-m7" if ARCH_CORTEX_M7
+    default "cortex-m33" if ARCH_CORTEX_M33
+    default "cortex-m55" if ARCH_CORTEX_M55
+    default "arm9" if ARCH_ARM9

arch/arm/arm9/gcc/BUILD.gn

@@ -1,53 +1,47 @@
-# Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
-# Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without modification,
-# are permitted provided that the following conditions are met:
-#
-# 1. Redistributions of source code must retain the above copyright notice, this list of
-#    conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright notice, this list
-#    of conditions and the following disclaimer in the documentation and/or other materials
-#    provided with the distribution.
-#
-# 3. Neither the name of the copyright holder nor the names of its contributors may be used
-#    to endorse or promote products derived from this software without specific prior written
-#    permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
-# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-static_library("base") {
-
-    sources = [
-        "core/los_priqueue.c",
-        "core/los_swtmr.c",
-        "core/los_sys.c",
-        "core/los_task.c",
-        "core/los_tick.c",
-        "core/los_timeslice.c",
-        "ipc/los_event.c",
-        "ipc/los_mux.c",
-        "ipc/los_queue.c",
-        "ipc/los_sem.c",
-        "mem/bestfit/los_membox.c",
-        "mem/bestfit/los_memcheck.c",
-        "mem/bestfit/los_memory.c",
-        "mem/bestfit/los_memstat.c",
-        "mem/bestfit/los_multipledlinkhead.c",
-        "mem/common/los_slab.c",
-        "mem/common/los_slabmem.c",
-        "misc/los_misc.c",
-        "om/los_err.c",
-    ]
-}
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_name = "arch"
+kernel_module(module_name) {
+  sources = [
+    "los_context.c",
+    "los_dispatch.S",
+    "los_exc.S",
+    "los_interrupt.c",
+    "los_timer.c",
+    "reset_vector.S",
+  ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
+}
+
+config("public") {
+  include_dirs = [ "." ]
+}

arch/arm/arm9/gcc/los_arch_atomic.h

@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    return *v;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicXchg32bits(Atomic *v, INT32 val)
+{
+    INT32 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(Atomic *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */
+

arch/arm/arm9/gcc/los_arch_context.h

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#define PSR_T_ARM      0x00000000U
+#define PSR_T_THUMB    0x00000020U
+#define PSR_MODE_SVC   0x00000013U
+#define PSR_MODE_SYS   0x0000001FU
+
+#define PSR_MODE_SVC_THUMB  (PSR_MODE_SVC | PSR_T_THUMB)
+#define PSR_MODE_SVC_ARM    (PSR_MODE_SVC | PSR_T_ARM)
+
+#define PSR_MODE_SYS_THUMB  (PSR_MODE_SYS | PSR_T_THUMB)
+#define PSR_MODE_SYS_ARM    (PSR_MODE_SYS | PSR_T_ARM)
+
+VOID OsTaskEntryArm(VOID);
+VOID OsTaskEntryThumb(VOID);
+
+typedef struct TagTskContext {
+    UINT32 spsr;
+    UINT32 r0;
+    UINT32 r1;
+    UINT32 r2;
+    UINT32 r3;
+    UINT32 r4;
+    UINT32 r5;
+    UINT32 r6;
+    UINT32 r7;
+    UINT32 r8;
+    UINT32 r9;
+    UINT32 r10;
+    UINT32 r11;
+    UINT32 r12;
+    UINT32 sp;
+    UINT32 lr;
+    UINT32 pc;
+} TaskContext;
+
+/**
+ * @ingroup  los_config
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);
+
+/**
+ * @ingroup los_arch_context
+ * @brief Wait for interrupt.
+ *
+ * @par Description:
+ * <ul>
+ * <li>This API is used to suspend execution until interrupt or a debug request occurs.</li>
+ * </ul>
+ * @attention None.
+ *
+ * @param None.
+ *
+ * @retval: None.
+ *
+ * @par Dependency:
+ * los_arch_context.h: the header file that contains the API declaration.
+ * @see None.
+ */
+extern VOID wfi(VOID);
+
+/**
+ * @ingroup los_arch_context
+ * @brief: mem fence function.
+ *
+ * @par Description:
+ * This API is used to fence for memory.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_context.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID dmb(VOID);
+
+/**
+ * @ingroup los_arch_context
+ * @brief: mem fence function.
+ *
+ * @par Description:
+ * This API is same as dmb, it just for adaptation.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_context.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID dsb(VOID);
+
+/**
+ * @ingroup los_arch_context
+ * @brief: instruction fence function.
+ *
+ * @par Description:
+ * This API is used to fence for instruction.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_context.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID isb(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */

arch/arm/arm9/gcc/los_arch_interrupt.h

@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_INTERRUPT_H
+#define _LOS_ARCH_INTERRUPT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST                   0
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST                    7
+#endif
+
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of arm9 system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT                     0
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of arm9 interrupt vector.
+ */
+#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a arm9 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a arm9 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li
+></ul>
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+#define OS_EXC_IN_INIT                      0
+#define OS_EXC_IN_TASK                      1
+#define OS_EXC_IN_HWI                       2
+
+#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
+#define OS_EXC_FLAG_IN_HWI                  0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
+ */
+typedef struct TagExcContext {
+    UINT32 spsr;
+    UINT32 r0;
+    UINT32 r1;
+    UINT32 r2;
+    UINT32 r3;
+    UINT32 r4;
+    UINT32 r5;
+    UINT32 r6;
+    UINT32 r7;
+    UINT32 r8;
+    UINT32 r9;
+    UINT32 r10;
+    UINT32 r11;
+    UINT32 r12;
+    UINT32 sp;
+    UINT32 lr;
+    UINT32 pc;
+} EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * exception types: undefined instruction exception.
+ */
+#define OS_EXCEPT_UNDEF_INSTR           1
+
+/**
+ * @ingroup los_exc
+ * exception types: software interrupt.
+ */
+#define OS_EXCEPT_SWI                   2
+
+/**
+ * @ingroup los_exc
+ * exception types: prefetch abort exception.
+ */
+#define OS_EXCEPT_PREFETCH_ABORT        3
+
+/**
+ * @ingroup los_exc
+ * exception types: data abort exception.
+ */
+#define OS_EXCEPT_DATA_ABORT            4
+
+/**
+ * @ingroup los_exc
+ * exception types: FIQ exception.
+ */
+#define OS_EXCEPT_FIQ                   5
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
+ *
+ */
+typedef struct TagExcInfo {
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    UINT16 phase;
+    /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+    UINT16 type;
+    /**< If the exact address access error indicates the wrong access address when the exception occurred */
+    UINT32 faultAddr;
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    UINT32 thrdPid;
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
+    UINT16 nestCnt;
+    /**< reserve */
+    UINT16 reserved;
+    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+    EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_intCount;
+extern ExcInfo g_excInfo;
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_INTERRUPT_H */

arch/arm/arm9/gcc/los_arch_timer.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */

arch/arm/arm9/gcc/los_context.c

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
+
+/* ****************************************************************************
+ Function    : ArchInit
+ Description : arch init function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+    HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function    : ArchSysExit
+ Description : Task exit function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+    LOS_IntLock();
+    while (1) {
+    }
+}
+
+/* ****************************************************************************
+ Function    : ArchTskStackInit
+ Description : Task stack initialization function
+ Input       : taskID     --- TaskID
+               stackSize  --- Total size of the stack
+               topStack    --- Top of task's stack
+ Output      : None
+ Return      : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
+
+    context->r0 = taskID;
+    context->r1 = 0x01010101L;
+    context->r2 = 0x02020202L;
+    context->r3 = 0x03030303L;
+    context->r4 = 0x04040404L;
+    context->r5 = 0x05050505L;
+    context->r6 = 0x06060606L;
+    context->r7 = 0x07070707L;
+    context->r8 = 0x08080808L;
+    context->r9 = 0x09090909L;
+    context->r10 = 0x10101010L;
+    context->r11 = 0x11111111L;
+    context->r12 = 0x12121212L;
+    context->sp = (UINTPTR)topStack + stackSize;
+    context->lr = (UINTPTR)ArchSysExit;
+
+    if ((UINTPTR)taskCB->taskEntry & 0x01) {
+        context->pc = (UINTPTR)OsTaskEntryThumb;
+        context->spsr = PSR_MODE_SYS_THUMB; /* thumb mode */
+    } else {
+        context->pc = (UINTPTR)OsTaskEntryArm;
+        context->spsr = PSR_MODE_SYS_ARM;   /* arm mode */
+    }
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+
+    return LOS_OK; /* never return */
+}
+
+LITE_OS_SEC_TEXT_INIT VOID ArchTaskSchedule(VOID)
+{
+    __asm__ __volatile__("swi 0");
+}
+
+LITE_OS_SEC_TEXT_INIT VOID dmb(VOID)
+{
+    __asm__ __volatile__("" : : : "memory");
+}
+
+LITE_OS_SEC_TEXT_INIT VOID dsb(VOID)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory");
+}
+
+LITE_OS_SEC_TEXT_INIT VOID isb(VOID)
+{
+    __asm__ __volatile__("" : : : "memory");
+}
+
+LITE_OS_SEC_TEXT_INIT VOID wfi(VOID)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c7, c0, 4" : : "r"(0) : "memory");
+}
+

arch/arm/arm9/gcc/los_dispatch.S

@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    .equ    OS_PSR_THUMB,       0x20
+    .equ    OS_PSR_INT_DIS,     0xC0
+    .equ    OS_PSR_FIQ_DIS,     0x40
+    .equ    OS_PSR_IRQ_DIS,     0x80
+    .equ    OS_PSR_MODE_MASK,   0x1F
+    .equ    OS_PSR_MODE_USR,    0x10
+    .equ    OS_PSR_MODE_FIQ,    0x11
+    .equ    OS_PSR_MODE_IRQ,    0x12
+    .equ    OS_PSR_MODE_SVC,    0x13
+    .equ    OS_PSR_MODE_ABT,    0x17
+    .equ    OS_PSR_MODE_UND,    0x1B
+    .equ    OS_PSR_MODE_SYS,    0x1F
+
+    .global HalStartToRun
+    .global OsTaskEntryArm
+    .global OsTaskEntryThumb
+    .global HalExceptSwiHdl
+    .global HalExceptFiqHdl
+    .global HalExceptIrqHdl
+
+    .extern OsTaskEntry
+    .extern OsSchedTaskSwitch
+    .extern HalInterrupt
+    .extern g_losTask
+
+    .code 32
+    .text
+
+.macro SAVE_CONTEXT
+    STMFD   SP!, {R0}
+
+    MRS     R0, SPSR
+    AND     R0, R0, #OS_PSR_MODE_SYS
+    CMP     R0, #OS_PSR_MODE_SYS
+    BNE     1f
+
+    STMFD   SP!, {SP}^
+    LDMFD   SP!, {R0}
+
+    STMFD   R0!, {LR}
+    MOV     LR, R0
+    LDMFD   SP!, {R0}
+
+    STMFD   LR, {R0-R14}^
+
+    SUB     LR, LR, #60
+    MRS     R0, SPSR
+    STMFD   LR!, {R0}
+
+    LDR     R1, =g_losTask
+    LDR     R1, [R1]
+    STR     LR, [R1]
+    B       2f
+
+1:
+    LDMFD   SP!, {R0}
+    STMFD   SP!, {R0-R12, LR}
+    MRS     R0, SPSR
+    STMFD   SP!, {R0}
+
+2:
+.endm
+
+.macro RETSORE_CONTEXT
+    MRS     R0, SPSR
+    AND     R0, R0, #OS_PSR_MODE_SYS
+    CMP     R0, #OS_PSR_MODE_SYS
+    BNE     3f
+
+    LDR     R1, =g_losTask
+    LDR     R1, [R1]
+    LDR     LR, [R1]
+
+    LDMFD   LR!, {R0}
+    MSR     SPSR_cxsf, R0
+    LDMFD   LR, {R0-R14}^
+    ADD     LR, LR, #60
+    LDMFD   LR!, {PC}^
+3:
+    LDMFD   SP!, {R0}
+    MSR     SPSR_cxsf, R0
+    LDMFD   SP!, {R0-R12, LR}
+    MOVS    PC, LR
+.endm
+
+.macro TASK_SWITCH
+    MRS     R0, CPSR
+    ORR     R0, R0, #OS_PSR_INT_DIS
+    MSR     CPSR, R0
+    BLX     OsSchedTaskSwitch
+    CMP     R0, #0
+    BEQ     4f
+
+    LDR     R0, =g_losTask
+    LDR     R1, [R0, #4]
+    STR     R1, [R0]
+
+4:
+.endm
+
+HalStartToRun:
+    LDR     R1, =g_losTask
+    LDR     R0, [R1, #4]
+    LDR     LR, [R0]
+
+    LDMFD   LR!, {R0}
+    MSR     SPSR_cxsf, R0
+
+    LDMFD   LR, {R0-R14}^
+    ADD     LR, LR, #60
+    LDMFD   LR!, {PC}^
+
+HalExceptSwiHdl:
+    SAVE_CONTEXT
+
+    TASK_SWITCH
+
+    RETSORE_CONTEXT
+
+HalExceptFiqHdl:
+    SUB     LR, LR, #4
+    SAVE_CONTEXT
+
+    BLX     HalInterrupt
+
+    RETSORE_CONTEXT
+
+HalExceptIrqHdl:
+    SUB     LR, LR, #4
+
+    SAVE_CONTEXT
+
+    BLX     HalInterrupt
+
+    RETSORE_CONTEXT
+
+OsTaskEntryArm:
+    STMFD   SP!, {LR}
+    BL      OsTaskEntry
+    LDMFD   SP!, {LR}
+    BX      LR
+
+    .code 16
+    .text
+OsTaskEntryThumb:
+    PUSH    {LR}
+    BL      OsTaskEntry
+    POP     {R0}
+    MOV     LR, R0
+    BX      LR
+

arch/arm/arm9/gcc/los_exc.S

@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    .equ OS_PSR_INT_DIS,    0xC0
+    .equ OS_PSR_FIQ_DIS,    0x40
+    .equ OS_PSR_IRQ_DIS,    0x80
+    .equ OS_PSR_MODE_MASK,  0x1F
+    .equ OS_PSR_MODE_USR,   0x10
+    .equ OS_PSR_MODE_FIQ,   0x11
+    .equ OS_PSR_MODE_IRQ,   0x12
+    .equ OS_PSR_MODE_SVC,   0x13
+    .equ OS_PSR_MODE_ABT,   0x17
+    .equ OS_PSR_MODE_UND,   0x1B
+    .equ OS_PSR_MODE_SYS,   0x1F
+
+    .equ OS_EXCEPT_RESET,           0x00
+    .equ OS_EXCEPT_UNDEF_INSTR,     0x01
+    .equ OS_EXCEPT_SWI,             0x02
+    .equ OS_EXCEPT_PREFETCH_ABORT,  0x03
+    .equ OS_EXCEPT_DATA_ABORT,      0x04
+    .equ OS_EXCEPT_FIQ,             0x05
+    .equ OS_EXCEPT_ADDR_ABORT,      0x06
+    .equ OS_EXCEPT_IRQ,             0x07
+
+    .global HalExceptAddrAbortHdl
+    .global HalExceptDataAbortHdl
+    .global HalExceptPrefetchAbortHdl
+    .global HalExceptUndefInstrHdl
+
+    .extern HalExcHandleEntry
+    .extern __exc_stack_top
+
+    .code 32
+    .text
+
+HalExceptUndefInstrHdl:
+    STMFD   SP!, {R0-R5}
+    MOV     R0, #OS_EXCEPT_UNDEF_INSTR
+    B       _osExceptDispatch
+
+HalExceptPrefetchAbortHdl:
+    SUB     LR, LR, #4
+    STMFD   SP!, {R0-R5}
+
+    MOV     R0, #OS_EXCEPT_PREFETCH_ABORT
+
+    B       _osExceptDispatch
+
+HalExceptDataAbortHdl:
+    SUB     LR, LR, #4
+    STMFD   SP!, {R0-R5}
+
+    MOV     R0, #OS_EXCEPT_DATA_ABORT
+
+    B       _osExceptDispatch
+
+HalExceptAddrAbortHdl:
+    SUB     LR, LR, #8
+    STMFD   SP!, {R0-R5}
+
+    MOV     R0, #OS_EXCEPT_ADDR_ABORT
+
+    B       _osExceptDispatch
+
+_osExceptDispatch:
+    MRS     R1, SPSR
+    MOV     R2, LR
+    MOV     R4, SP
+    ADD     SP, SP, #(6 * 4)
+
+    MSR     CPSR_c, #(OS_PSR_INT_DIS | OS_PSR_MODE_SVC)
+    MOV     R3, SP
+    LDR     SP, =__exc_stack_top
+
+    STMFD   SP!, {R2}
+    STMFD   SP!, {LR}
+    STMFD   SP!, {R3}
+    STMFD   SP!, {R6-R12}
+    LDMFD   R4!, {R6-R12}
+    STMFD   SP!, {R6-R11}
+    STMFD   SP!, {R1}
+    MOV     R3, SP
+
+_osExceptionGetSP:
+    STMFD   SP!, {R1}
+    LDR     R2, =HalExcHandleEntry
+
+    MOV     LR, PC
+    BX      R2
+
+    LDMFD   SP!, {R1}
+    MOV     SP, R1
+
+    LDMFD   SP!, {R1}
+    MSR     CPSR, R1
+    LDMFD   SP!, {R0-R12}
+    ADD     SP, SP, #(4 * 2)
+    LDMFD   SP!, {LR}
+    SUB     SP, SP, #(4 * 3)
+    LDMFD   SP, {SP}
+    ADD     LR, LR, #4
+    MOV     PC, LR
+
+    .end

arch/arm/arm9/gcc/los_interrupt.c

@@ -0,0 +1,520 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "los_interrupt.h"
+#include <stdarg.h>
+#include "securec.h"
+#include "los_context.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+#include "los_reg.h"
+
+#define OS_INT_IRQ_ENABLE           (1U << 0)
+#define OS_INT_FIQ_ENABLE           (1U << 1)
+#define OS_INT_REG_BASE             0x00802040UL
+#define OS_INT_GLOBAL_ENABLE_ADDR   (OS_INT_REG_BASE + 4)
+#define OS_INT_ENABLE_ADDR          (OS_INT_REG_BASE)
+#define OS_INT_STATUS_ADDR          (OS_INT_REG_BASE + 12)
+
+#define OS_INSTR_SET_MASK           0x01000020U
+#define OS_ARM_INSTR_LEN            4
+#define OS_THUMB_INSTR_LEN          2
+
+UINT32 g_intCount = 0;
+ExcInfo g_excInfo = {0};
+
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+    HWI_PROC_FUNC pfnHandler;
+    VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+    }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+    }
+}
+#endif
+
+
+/* ****************************************************************************
+ Function    : HwiNumGet
+ Description : Get an interrupt number
+ Input       : None
+ Output      : None
+ Return      : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+    UINT32 status;
+
+    READ_UINT32(status, OS_INT_STATUS_ADDR);
+
+    return (31 - CLZ(status));
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    *((volatile UINT32 *)OS_INT_ENABLE_ADDR) |= (1U << (hwiNum));
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    *((volatile UINT32 *)OS_INT_ENABLE_ADDR) &= ~(1U << (hwiNum));
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .getCurIrqNum   = HwiNumGet,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+    return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function    : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+/*lint -e529*/
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+    while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+    UINT32 intSave;
+    UINT32 hwiIndex;
+
+    intSave = LOS_IntLock();
+    g_intCount++;
+    LOS_IntRestore(intSave);
+
+#if (LOSCFG_BASE_CORE_SCHED_SLEEP == 1)
+    OsSchedUpdateSleepTime();
+#endif
+
+    hwiIndex = HwiNumGet();
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+
+    HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+        g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+    }
+#else
+    if (g_hwiHandlerForm[hwiIndex] != 0) {
+        g_hwiHandlerForm[hwiIndex]();
+    }
+#endif
+
+    HalAftInterruptHandler(hwiIndex);
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+    intSave = LOS_IntLock();
+    g_intCount--;
+    LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiCreate
+ Description : create hardware interrupt
+ Input       : hwiNum   --- hwi num to create
+               hwiPrio  --- priority of the hwi
+               hwiMode  --- unused
+               hwiHandler  --- hwi handler
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T hwiMode,
+                                           HWI_PROC_FUNC hwiHandler,
+                                           HwiIrqParam *irqParam)
+{
+    (VOID)hwiMode;
+    UINT32 intSave;
+
+    if (hwiHandler == NULL) {
+        return OS_ERRNO_HWI_PROC_FUNC_NULL;
+    }
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return OS_ERRNO_HWI_ALREADY_CREATED;
+    }
+
+    intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (irqParam != NULL) {
+        OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+    } else {
+        OsSetVector(hwiNum, hwiHandler, NULL);
+    }
+#else
+    (VOID)irqParam;
+    OsSetVector(hwiNum, hwiHandler);
+#endif
+    HwiUnmask(hwiNum);
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input       : hwiNum   --- hwi num to delete
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+    (VOID)irqParam;
+    UINT32 intSave;
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    HwiMask(hwiNum);
+
+    intSave = LOS_IntLock();
+    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+    CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+    PRINTK("Type      = %d\n", excInfo->type);
+    PRINTK("ThrdPid   = %d\n", excInfo->thrdPid);
+    PRINTK("Phase     = %s\n", phaseStr[excInfo->phase]);
+    PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Current task info:\n");
+    if (excInfo->phase == OS_EXC_IN_TASK) {
+        LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+        PRINTK("Task name = %s\n", taskCB->taskName);
+        PRINTK("Task ID   = %d\n", taskCB->taskID);
+        PRINTK("Task SP   = 0x%x\n", taskCB->stackPointer);
+        PRINTK("Task ST   = 0x%x\n", taskCB->topOfStack);
+        PRINTK("Task SS   = 0x%x\n", taskCB->stackSize);
+    } else if (excInfo->phase == OS_EXC_IN_HWI) {
+        PRINTK("Exception occur in interrupt phase!\n");
+    } else {
+        PRINTK("Exception occur in system init phase!\n");
+    }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Exception reg dump:\n");
+    PRINTK("PC        = 0x%x\n", excInfo->context->pc);
+    PRINTK("LR        = 0x%x\n", excInfo->context->lr);
+    PRINTK("R0        = 0x%x\n", excInfo->context->r0);
+    PRINTK("R1        = 0x%x\n", excInfo->context->r1);
+    PRINTK("R2        = 0x%x\n", excInfo->context->r2);
+    PRINTK("R3        = 0x%x\n", excInfo->context->r3);
+    PRINTK("R4        = 0x%x\n", excInfo->context->r4);
+    PRINTK("R5        = 0x%x\n", excInfo->context->r5);
+    PRINTK("R6        = 0x%x\n", excInfo->context->r6);
+    PRINTK("R7        = 0x%x\n", excInfo->context->r7);
+    PRINTK("R8        = 0x%x\n", excInfo->context->r8);
+    PRINTK("R9        = 0x%x\n", excInfo->context->r9);
+    PRINTK("R10       = 0x%x\n", excInfo->context->r10);
+    PRINTK("R11       = 0x%x\n", excInfo->context->r11);
+    PRINTK("R12       = 0x%x\n", excInfo->context->r12);
+    PRINTK("xPSR      = 0x%x\n", excInfo->context->spsr);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+    UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+    UINT32 index;
+
+    OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->sp);
+
+    PRINTK("----- backtrace start -----\n");
+    for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+        if (LR[index] == 0) {
+            break;
+        }
+        PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
+    }
+    PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+    PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+    MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+    UINT32 errCnt;
+    UINT32 i;
+
+    (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+    errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+    if (errCnt < OS_SYS_MEM_NUM) {
+        errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+    }
+
+    if (errCnt == 0) {
+        PRINTK("all memory pool check passed!\n");
+        return;
+    }
+
+    for (i = 0; i < errCnt; i++) {
+        PRINTK("pool num    = %d\n", i);
+        PRINTK("pool type   = %d\n", memExcInfo[i].type);
+        PRINTK("pool addr   = 0x%x\n", memExcInfo[i].startAddr);
+        PRINTK("pool size   = 0x%x\n", memExcInfo[i].size);
+        PRINTK("pool free   = 0x%x\n", memExcInfo[i].free);
+        PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
+        PRINTK("pool error node addr  = 0x%x\n", memExcInfo[i].errorAddr);
+        PRINTK("pool error node len   = 0x%x\n", memExcInfo[i].errorLen);
+        PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
+    }
+#endif
+    UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+    if (ret == LOS_OK) {
+        PRINTK("system heap memcheck over, all passed!\n");
+    }
+
+    PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+    PRINTK("*************Exception Information**************\n");
+    OsExcTypeInfo(excInfo);
+    OsExcCurTaskInfo(excInfo);
+    OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+    OsExcBackTraceInfo(excInfo);
+#endif
+    OsGetAllTskInfo();
+    OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+    g_intCount++;
+    g_excInfo.nestCnt++;
+
+    g_excInfo.type = excType;
+
+    if ((excType == OS_EXCEPT_UNDEF_INSTR) || (excType == OS_EXCEPT_SWI)) {
+        if ((excBufAddr->spsr & OS_INSTR_SET_MASK) == 0) { /* Work status: ARM */
+            excBufAddr->pc -= OS_ARM_INSTR_LEN;
+        } else if ((excBufAddr->spsr & OS_INSTR_SET_MASK) == 0x20) { /* Work status: Thumb */
+            excBufAddr->pc -= OS_THUMB_INSTR_LEN;
+        }
+    }
+    g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+
+    if (g_losTask.runTask != NULL) {
+        g_excInfo.phase = OS_EXC_IN_TASK;
+        g_excInfo.thrdPid = g_losTask.runTask->taskID;
+    } else {
+        g_excInfo.phase = OS_EXC_IN_INIT;
+        g_excInfo.thrdPid = OS_NULL_INT;
+    }
+    g_excInfo.context = excBufAddr;
+
+    OsDoExcHook(EXC_INTERRUPT);
+    OsExcInfoDisplay(&g_excInfo);
+    ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function    : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    UINT32 reg;
+    UINT32 val;
+
+    for (val = OS_SYS_VECTOR_CNT; val < OS_VECTOR_CNT; val++) {
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+        g_hwiForm[val].pfnHook = HalHwiDefaultHandler;
+        g_hwiForm[val].uwParam = 0;
+#else
+        g_hwiForm[val] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+#endif
+    }
+
+    val = OS_INT_IRQ_ENABLE | OS_INT_FIQ_ENABLE;
+    READ_UINT32(reg, OS_INT_GLOBAL_ENABLE_ADDR);
+    reg |= val;
+    WRITE_UINT32(reg, OS_INT_GLOBAL_ENABLE_ADDR);
+#endif
+    return;
+}
+
+UINT32 ArchIntLock(VOID)
+{
+    UINT32 ret;
+    UINT32 temp;
+
+    __asm__ __volatile__("MRS %0, CPSR\n"
+                         "ORR %1, %0, #0xC0\n"
+                         "MSR CPSR_c, %1"
+                         : "=r"(ret), "=r"(temp)
+                         :
+                         : "memory");
+    return ret;
+}
+
+VOID ArchIntRestore(UINT32 intSave)
+{
+    __asm__ __volatile__("MSR CPSR_c, %0" : : "r"(intSave));
+}
+
+UINT32 ArchIntUnLock(VOID)
+{
+    UINT32 intSave;
+
+    __asm__ __volatile__("MRS %0, CPSR\n"
+                         "BIC %0, %0, #0xC0\n"
+                         "MSR CPSR_c, %0"
+                         : "=r"(intSave)
+                         :
+                         : "memory");
+    return intSave;
+}
+

arch/arm/arm9/gcc/los_timer.c

@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_reg.h"
+
+#define OS_TIMER_CLKDIV_POS     3
+#define OS_TIMER_CLKDIV_MASK    7
+#define OS_TIMER_INT_POS        7
+#define OS_TIMER_INT_MASK       7
+#define OS_TIMER_IRQ_NUM        8
+#define OS_TIMER_ENABLE         (1U << 0)
+#define OS_TIMER_32K_CLK_BIT    (1U << 21)
+#define OS_TIMER_CNT_READ_BIT   (1U << 0)
+
+#define OS_TIMER_REG_BASE           0x00802A40UL
+#define OS_TIMER_CLK_PWD_ADDR       0x00802008UL
+#define OS_TIMER_PERIOD_REG_ADDR    (OS_TIMER_REG_BASE)
+#define OS_TIMER_CTL_REG_ADDR       (OS_TIMER_REG_BASE + 12)
+#define OS_TIMER_READ_CTL_ADDR      (OS_TIMER_REG_BASE + 16)
+#define OS_TIMER_READ_VAL_ADDR      (OS_TIMER_REG_BASE + 20)
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = OS_TIMER_IRQ_NUM,
+    .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+    UINT32 intSave = LOS_IntLock();
+    UINT32 value;
+
+    ArchTickTimer *tick = &g_archTickTimer;
+    tick->freq = OS_SYS_CLOCK;
+
+    READ_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
+    value &= ~(OS_TIMER_32K_CLK_BIT);
+    WRITE_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
+
+    value = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX;
+    WRITE_UINT32(value, OS_TIMER_PERIOD_REG_ADDR);
+
+    READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
+    value &= ~(OS_TIMER_CLKDIV_MASK << OS_TIMER_CLKDIV_POS); // The default is 1, and the clock does not divide.
+    value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS); // Clearing interruption.
+    value |= 0x1 << OS_TIMER_INT_POS;
+    value |= OS_TIMER_ENABLE; // Enable timer.
+    WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
+
+    (VOID)ArchHwiCreate(OS_TIMER_IRQ_NUM, 0, 0, (HWI_PROC_FUNC)handler, 0);
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+STATIC VOID SysTickClockIrqClear(VOID)
+{
+    UINT32 mask = OS_TIMER_INT_MASK << OS_TIMER_INT_POS;
+    UINT32 status;
+
+    do {
+        WRITE_UINT32(mask, OS_TIMER_CTL_REG_ADDR);
+        READ_UINT32(status, OS_TIMER_CTL_REG_ADDR);
+    } while (status & mask);
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+    if (nextResponseTime > g_archTickTimer.periodMax) {
+        nextResponseTime = g_archTickTimer.periodMax;
+    }
+
+    SysTickLock();
+    WRITE_UINT32((UINT32)nextResponseTime, OS_TIMER_PERIOD_REG_ADDR);
+    SysTickClockIrqClear();
+    SysTickUnlock();
+    return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+    UINT32 val;
+
+    READ_UINT32(*period, OS_TIMER_PERIOD_REG_ADDR);
+
+    WRITE_UINT32(OS_TIMER_CNT_READ_BIT, OS_TIMER_READ_CTL_ADDR);
+    do {
+        READ_UINT32(val, OS_TIMER_READ_CTL_ADDR);
+    } while (val & OS_TIMER_CNT_READ_BIT); // Wait for the setting to take effect.
+
+    READ_UINT32(val, OS_TIMER_READ_VAL_ADDR);
+
+    return (UINT64)val;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+    UINT32 value;
+
+    READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
+    value &= ~OS_TIMER_ENABLE;
+    value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS);
+    value |= 0x1 << OS_TIMER_INT_POS;
+    WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+    UINT32 value;
+
+    READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
+    value |= OS_TIMER_ENABLE;
+    value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS);
+    value |= 0x1 << OS_TIMER_INT_POS;
+    WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+    dsb();
+    wfi();
+    isb();
+
+    return LOS_OK;
+}

arch/arm/arm9/gcc/reset_vector.S

@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    .equ CPSR_IRQ_DISABLE,  0x80
+    .equ CPSR_FIQ_DISABLE,  0x40
+    .equ CPSR_THUMB_ENABLE, 0x20
+    .equ CPSR_USER_MODE,    0x10
+    .equ CPSR_FIQ_MODE,     0x11
+    .equ CPSR_IRQ_MODE,     0x12
+    .equ CPSR_SVC_MODE,     0x13
+    .equ CPSR_ABT_MODE,     0x17
+    .equ CPSR_UNDEF_MODE,   0x1B
+
+    .global __exc_stack_top
+    .global __irq_stack_top
+    .global __fiq_stack_top
+    .global __svc_stack_top
+    .global __abt_stack_top
+    .global __undef_stack_top
+    .global __exc_stack
+    .global __irq_stack
+    .global __fiq_stack
+    .global __svc_stack
+    .global __abt_stack
+    .global __undef_stack
+    .global main
+
+    .extern HalExceptFiqHdl
+    .extern HalExceptAddrAbortHdl
+    .extern HalExceptDataAbortHdl
+    .extern HalExceptPrefetchAbortHdl
+    .extern HalExceptSwiHdl
+    .extern HalExceptUndefInstrHdl
+    .extern HalExceptIrqHdl
+    .extern _bss_start
+    .extern _bss_end
+
+    .code 32
+    .text
+
+    .section ".vectors", "ax"
+    .global _vector_start
+
+_vector_start:
+    B     HalResetVector
+    B     HalExceptUndefInstrHdl
+    B     HalExceptSwiHdl
+    B     HalExceptPrefetchAbortHdl
+    B     HalExceptDataAbortHdl
+    B     HalExceptAddrAbortHdl
+    B     HalExceptIrqHdl
+    B     HalExceptFiqHdl
+
+    .globl  HalResetVector
+    .section ".boot", "ax"
+
+HalResetVector:
+    MOV    R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_IRQ_MODE)
+    MSR    CPSR, R0
+    LDR    SP, =__irq_stack_top
+
+    MOV    R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_UNDEF_MODE)
+    MSR    CPSR, R0
+    LDR    SP, =__undef_stack_top
+
+    MOV    R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_ABT_MODE)
+    MSR    CPSR, R0
+    LDR    SP, =__abt_stack_top
+
+    MOV    R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_FIQ_MODE)
+    MSR    CPSR, R0
+    LDR    SP, =__fiq_stack_top
+
+    MOV    R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_SVC_MODE)
+    MSR    CPSR, R0
+    MSR    SPSR, R0
+    LDR    SP, =__svc_stack_top
+
+    BL     OsBssInit
+
+    B      main
+    B      .
+
+OsBssInit:
+    LDR     R0, =_bss_start
+    LDR     R1, =_bss_end
+
+    MOV     R3, R1
+    MOV     R4, R0
+    MOV     R2, #0
+1:  CMP     R4, R3
+    STRLO   R2, [R4], #4
+    BLO     1b
+    BX      LR
+
+    .section ".bss", "wa", %nobits
+    .align 3
+__undef_stack:
+    .space  32
+__undef_stack_top:
+
+__abt_stack:
+    .space  32
+__abt_stack_top:
+
+__irq_stack:
+    .space  1024
+__irq_stack_top:
+
+__fiq_stack:
+    .space  1024
+__fiq_stack_top:
+
+__svc_stack:
+    .space  1024
+__svc_stack_top:
+
+__exc_stack:
+    .space  512
+__exc_stack_top:
+

arch/arm/cortex-m/cortex-m4/los_exc.c

@@ -1,379 +0,0 @@
-/*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "los_exc_pri.h"
-#include "los_memcheck_pri.h"
-#ifdef LOSCFG_LIB_LIBC
-#include "string.h"
-#endif
-#include "securec.h"
-
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-#define EXC_INT_STATUS_LEN              OS_NVIC_INT_ENABLE_SIZE + OS_NVIC_INT_PEND_SIZE + OS_NVIC_INT_ACT_SIZE + \
-    OS_NVIC_INT_PRI_SIZE + OS_NVIC_EXCPRI_SIZE + OS_NVIC_SHCSR_SIZE + OS_NVIC_INT_CTRL_SIZE
-#define TASK_ARRAY_INIT_VALUE           0xff
-#define FAULT_STATUS_REG_BIT            32
-#define OS_NVIC_INT_CTRL_SIZE           4
-#define OS_NVIC_SHCSR_SIZE              4
-#define USGFAULT                        (1 << 18)
-#define BUSFAULT                        (1 << 17)
-#define MEMFAULT                        (1 << 16)
-#define DIV0FAULT                       (1 << 4)
-#define CORE_TYPE_CORTEX_M4             2
-#define HARDFAULT_IRQN                  (-13)
-static VOID *g_excContent;
-UINT32 g_curNestCount = 0;
-ExcInfo g_excInfo;
-
-__attribute__((noinline)) VOID LOS_Panic(const CHAR *fmt, ...)
-{
-    va_list ap;
-    va_start(ap,fmt);
-    PRINT_ERR(fmt, ap);
-    va_end(ap);
-    asm volatile ("swi 0");
-}
-
-UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
-    0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
-    0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
-    0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
-    0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
-};
-UINT32 g_excArraySize = 0;
-ExcInfoArray g_excArray[OS_EXC_TYPE_MAX - 1];
-
-UINT32 g_LR_regs = 0;
-UINT32 g_PC_regs = 0;
-
-LITE_OS_SEC_TEXT_INIT VOID OsExcInfoDisplay(ExcInfo *exc)
-{
-    PRINT_INFO("Phase      = 0x%x\n", exc->phase);
-    PRINT_INFO("Type       = 0x%x\n", exc->type);
-    PRINT_INFO("FaultAddr  = 0x%x\n", exc->faultAddr);
-    PRINT_INFO("ThrdPid    = 0x%x\n", exc->thrdPid);
-    PRINT_INFO("R0         = 0x%x\n", exc->context->uwR0);
-    PRINT_INFO("R1         = 0x%x\n", exc->context->uwR1);
-    PRINT_INFO("R2         = 0x%x\n", exc->context->uwR2);
-    PRINT_INFO("R3         = 0x%x\n", exc->context->uwR3);
-    PRINT_INFO("R4         = 0x%x\n", exc->context->uwR4);
-    PRINT_INFO("R5         = 0x%x\n", exc->context->uwR5);
-    PRINT_INFO("R6         = 0x%x\n", exc->context->uwR6);
-    PRINT_INFO("R7         = 0x%x\n", exc->context->uwR7);
-    PRINT_INFO("R8         = 0x%x\n", exc->context->uwR8);
-    PRINT_INFO("R9         = 0x%x\n", exc->context->uwR9);
-    PRINT_INFO("R10        = 0x%x\n", exc->context->uwR10);
-    PRINT_INFO("R11        = 0x%x\n", exc->context->uwR11);
-    PRINT_INFO("R12        = 0x%x\n", exc->context->uwR12);
-    PRINT_INFO("PriMask    = 0x%x\n", exc->context->uwPriMask);
-    PRINT_INFO("SP         = 0x%x\n", exc->context->uwSP);
-    PRINT_INFO("LR         = 0x%x\n", exc->context->uwLR);
-    PRINT_INFO("PC         = 0x%x\n", exc->context->uwPC);
-    PRINT_INFO("xPSR       = 0x%x\n", exc->context->uwxPSR);
-
-    g_LR_regs = exc->context->uwLR;
-    g_PC_regs = exc->context->uwPC;
-}
-
-/* ****************************************************************************
- Function : OsExcHandleEntry
- Description : EXC模块的处理分发函数
- Input  : excType
-        : faultAddr
-        : pid
-        : excBufAddr --- EXC寄存器信息的首地址
- Output : None
- Return : None
- **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID OsExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid,
-                                            EXC_CONTEXT_S *excBufAddr)
-{
-    UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT;  // 为2在中断中，为1 faultAddr有效
-    g_curNestCount++;
-    g_vuwIntCount++;
-    g_excInfo.nestCnt = g_curNestCount;
-
-    g_excInfo.type = excType & OS_NULL_SHORT;
-    g_excContent = (UINT32 *)g_aucTaskArray;
-
-    if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
-        g_excInfo.faultAddr = faultAddr;
-    } else {
-        g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
-    }
-
-    if (g_losTask.runTask != NULL) {
-        if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
-            g_excInfo.phase = OS_EXC_IN_HWI;
-            g_excInfo.thrdPid = pid;
-        } else {
-            g_excInfo.phase = OS_EXC_IN_TASK;
-            g_excInfo.thrdPid = g_losTask.runTask->taskID;
-        }
-    } else {
-        g_excInfo.phase = OS_EXC_IN_INIT;
-        g_excInfo.thrdPid = OS_NULL_INT;
-    }
-
-    if (excType & OS_EXC_FLAG_NO_FLOAT) {
-        g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
-    } else {
-        g_excInfo.context = excBufAddr;
-    }
-
-    OsExcSave2DDR();
-
-    OsExcInfoDisplay(&g_excInfo);
-
-    LOS_Reboot();
-}
-static VOID OsExcSaveIntStatus()
-{
-    UINT32 ret;
-    UINT32 failCnt = 0;
-    *((UINT32 *)g_excContent) = OS_EXC_TYPE_NVIC;
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-
-    // = OS_NVIC_INT_ENABLE_SIZE + OS_NVIC_INT_PEND_SIZE + OS_NVIC_INT_ACT_SIZE + OS_NVIC_INT_PRI_SIZE + 12 + 4 + 4
-    *((UINT32 *)g_excContent) = EXC_INT_STATUS_LEN;
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-    /* 保存中断ENABLE寄存器组 */
-    ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_SETENA_BASE, OS_NVIC_INT_ENABLE_SIZE);
-    g_excContent = (UINT8 *)g_excContent + OS_NVIC_INT_ENABLE_SIZE;
-    failCnt += (ret == EOK) ? 0 : 1;
-
-    /* 保存中断PEND寄存器组 */
-    ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_SETPEND_BASE, OS_NVIC_INT_PEND_SIZE);
-    g_excContent = (UINT8 *)g_excContent + OS_NVIC_INT_PEND_SIZE;
-    failCnt += (ret == EOK) ? 0 : 1;
-
-    /* 保存中断ACTIVE寄存器组 */
-    ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_INT_ACT_BASE, OS_NVIC_INT_ACT_SIZE);
-    g_excContent = (UINT8 *)g_excContent + OS_NVIC_INT_ACT_SIZE;
-    failCnt += (ret == EOK) ? 0 : 1;
-
-    /* 保存中断优先级寄存器组 */
-    ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_PRI_BASE, OS_NVIC_INT_PRI_SIZE);
-    g_excContent = (UINT8 *)g_excContent + OS_NVIC_INT_PRI_SIZE;
-    failCnt += (ret == EOK) ? 0 : 1;
-
-    /* 	系统异常优先级寄存器组 */
-    ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_EXCPRI_BASE, OS_NVIC_EXCPRI_SIZE);
-    g_excContent = (UINT8 *)g_excContent + OS_NVIC_EXCPRI_SIZE;
-    failCnt += (ret == EOK) ? 0 : 1;
-
-    /* 保存系统Handler控制及状态寄存器SHCSR */
-    ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_SHCSR, OS_NVIC_SHCSR_SIZE);
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-    failCnt += (ret == EOK) ? 0 : 1;
-
-    /* 保存中断控制及状态寄存器ICSR */
-    ret = memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (const VOID *)OS_NVIC_INT_CTRL, OS_NVIC_INT_CTRL_SIZE);
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-    failCnt += (ret == EOK) ? 0 : 1;
-
-    if (failCnt != 0) {
-        PRINT_ERR("OsExcSaveIntStatus copy register info failed, cnt:%d\n", failCnt);
-    }
-
-    return;
-}
-
-VOID OsExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
-{
-    ExcInfoArray *excInfo = NULL;
-    if ((type == 0) || (type >= OS_EXC_TYPE_MAX) || (func == NULL)) {
-        PRINT_ERR("OsExcRegister ERROR!\n");
-        return;
-    }
-    excInfo = &(g_excArray[type - 1]);
-    excInfo->uwType = type;
-    excInfo->pFnExcInfoCb = func;
-    excInfo->pArg = arg;
-    excInfo->uwValid = TRUE;
-}
-
-static VOID OsExcSaveSysInfo(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, UINT32 loop, UINT32 length, UINT32 index)
-{
-    UINT32 ret;
-    UINT32 buffer[OS_EXC_MAX_BUF_LEN];
-
-    *((UINT32 *)g_excContent) = type;
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-    *((UINT32 *)g_excContent) = length * (loop - index);
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-
-    for (; index < loop; index++) {
-        (VOID)memset_s(buffer, sizeof(UINT32) * OS_EXC_MAX_BUF_LEN, 0, sizeof(UINT32) * OS_EXC_MAX_BUF_LEN);
-        ret = func(index, (VOID *)buffer);
-        if (ret == LOS_OK) {
-            if (memcpy_s(g_excContent, MAX_EXC_MEM_SIZE, (VOID *)buffer, length) != EOK) {
-                PRINT_ERR("OsExcSaveSysInfo copy buffer failed\n");
-                return;
-            }
-            g_excContent = (UINT8 *)g_excContent + length;
-        } else {
-            g_excContent = (UINT8 *)g_excContent + length;
-        }
-    }
-}
-
-static VOID OsExcSaveInfo(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg)
-{
-    UINT32 length;
-    UINT32 index;
-    UINT32 loop;
-    UINT32 taskSwitchCount = 0;
-    TaskSwitchInfo *taskSwitchInfo = NULL;
-
-    if (arg == NULL) {
-        return;
-    }
-
-    switch (type) {
-        case OS_EXC_TYPE_TSK: /* save task info */
-            length = sizeof(TSK_INFO_S);
-            loop = *(UINT32 *)arg;
-            index = 0;
-            break;
-
-        case OS_EXC_TYPE_QUE: /* save queue info */
-            length = sizeof(QUEUE_INFO_S);
-            loop = *(UINT32 *)arg + 1;
-            index = 1;
-            break;
-
-        case OS_EXC_TYPE_NVIC:
-            (VOID)func(0, 0);
-            goto END;
-
-        case OS_EXC_TYPE_TSK_SWITCH: /* save task switch info */
-            // not necessary, just for macro int library
-            taskSwitchInfo = arg;
-            taskSwitchCount = taskSwitchInfo->cntInfo.maxCnt;
-            length = sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN;
-            if (taskSwitchInfo->cntInfo.isFull) {
-                index = taskSwitchInfo->idx;
-                loop = index + taskSwitchCount;
-            } else {
-                index = 0;
-                loop = taskSwitchInfo->idx;
-            }
-            break;
-
-        case OS_EXC_TYPE_MEM: /* save mem info */
-            length = sizeof(MEM_INFO_S);
-            loop = *(UINT32 *)arg;
-            index = 0;
-            break;
-
-        default:
-            goto END;
-    }
-    OsExcSaveSysInfo(type, (EXC_INFO_SAVE_CALLBACK)func, loop, length, index);
-END:
-    return;
-}
-
-static VOID OsExcSave2DDR(VOID)
-{
-    UINT32 index = 0;
-    UINT32 ret;
-    UINT32 failCnt = 0;
-
-    ret = memset_s(g_aucTaskArray, MAX_EXC_MEM_SIZE, TASK_ARRAY_INIT_VALUE, g_excArraySize);
-    if (ret != EOK) {
-        PRINT_ERR("memset failed\n");
-        return;
-    }
-
-    /* define core type */
-    *((UINT32 *)g_excContent) = CORE_TYPE_CORTEX_M4;  // 1 is cortex-M3, 2 is cortex-M4
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-
-    /* save exception info */
-    *((UINT32 *)g_excContent) = OS_EXC_TYPE_CONTEXT;
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-    *((UINT32 *)g_excContent) = sizeof(ExcInfo) - sizeof(UINT32) + sizeof(EXC_CONTEXT_S);
-
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-    ret = memcpy_s((VOID *)g_excContent, MAX_EXC_MEM_SIZE, (VOID *)&g_excInfo, sizeof(ExcInfo) - sizeof(UINT32));
-    g_excContent = (UINT8 *)g_excContent + sizeof(ExcInfo) - sizeof(UINT32);
-    failCnt += (ret == EOK) ? 0 : 1;
-
-    ret = memcpy_s((VOID *)g_excContent, MAX_EXC_MEM_SIZE, g_excInfo.context, sizeof(EXC_CONTEXT_S));
-    g_excContent = (UINT8 *)g_excContent + sizeof(EXC_CONTEXT_S);
-    failCnt += (ret == EOK) ? 0 : 1;
-
-    if (failCnt != 0) {
-        PRINT_ERR("OsExcSave2DDR copy exc info failed, cnt:%d\n", failCnt);
-    }
-
-    for (index = 0; index < (OS_EXC_TYPE_MAX - 1); index++) {
-        if (g_excArray[index].uwValid == FALSE) {
-            continue;
-        }
-        OsExcSaveInfo(g_excArray[index].uwType, g_excArray[index].pFnExcInfoCb, g_excArray[index].pArg);
-    }
-    *((UINT32 *)g_excContent) = OS_EXC_TYPE_MAX;
-    g_excContent = (UINT8 *)g_excContent + sizeof(UINT32);
-    return;
-}
-
-LITE_OS_SEC_TEXT_INIT VOID OsExcInit(UINT32 arraySize)
-{
-    g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = OsExcHardFault;
-    g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = OsExcNMI;
-    g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = OsExcMemFault;
-    g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = OsExcBusFault;
-    g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = OsExcUsageFault;
-    g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = OsExcSvcCall;
-    /* Enable USGFAULT, BUSFAULT, MEMFAULT */
-    *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
-    /* Enable DIV 0 and unaligned exception */  // 因为文件系统存在非对齐操作，故此异常暂不接管
-
-    *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
-    g_excArraySize = arraySize;
-
-    OsExcRegister(OS_EXC_TYPE_NVIC, (EXC_INFO_SAVE_CALLBACK)OsExcSaveIntStatus, NULL);
-}
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cplusplus */
-#endif /* __cplusplus */

arch/arm/cortex-m/cortex-m4/los_exc_pri.h

@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _LOS_EXC_PRI_H
-#define _LOS_EXC_PRI_H
-
-#include "los_exc.h"
-#include "los_sys_pri.h"
-#ifdef LOSCFG_LIB_LIBC
-#include "string.h"
-#endif
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-typedef enum {
-    OS_EXC_TYPE_CONTEXT     = 0,
-    OS_EXC_TYPE_TSK         = 1,
-    OS_EXC_TYPE_QUE         = 2,
-    OS_EXC_TYPE_NVIC        = 3,
-    OS_EXC_TYPE_TSK_SWITCH  = 4,
-    OS_EXC_TYPE_MEM         = 5,
-    OS_EXC_TYPE_MAX         = 6
-} ExcInfoType;
-
-typedef struct tagExcInfoCallBackArray {
-    ExcInfoType           uwType;
-    UINT32                  uwValid;
-    EXC_INFO_SAVE_CALLBACK  pFnExcInfoCb;
-    VOID*                   pArg;
-} ExcInfoArray;
-
-
-
-#define MAX_SCENE_INFO_SIZE     (8 + sizeof(ExcInfo) - 4 + sizeof(EXC_CONTEXT_S))
-#define MAX_TSK_INFO_SIZE       (8 + sizeof(TSK_INFO_S) * (LOSCFG_BASE_CORE_TSK_LIMIT + 1))
-#define MAX_INT_INFO_SIZE       (8 + 0x164)
-
-#if (LOSCFG_BASE_IPC_QUEUE == YES)
-#define MAX_QUEUE_INFO_SIZE     (8 + sizeof(QUEUE_INFO_S) * LOSCFG_BASE_IPC_QUEUE_LIMIT)
-#else
-#define MAX_QUEUE_INFO_SIZE     (0)
-#endif
-
-#if (LOSCFG_BASE_CORE_EXC_TSK_SWITCH == YES)
-#define MAX_SWITCH_INFO_SIZE    (8 + (sizeof(UINT32) + sizeof(CHAR) * LOS_TASK_NAMELEN) * OS_TASK_SWITCH_INFO_COUNT)
-#else
-#define MAX_SWITCH_INFO_SIZE    (0)
-#endif
-
-#if (LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK == YES)
-#define MAX_MEM_INFO_SIZE       (8 + sizeof(MEM_INFO_S) * OS_SYS_MEM_NUM)
-#else
-#define MAX_MEM_INFO_SIZE       (0)
-#endif
-
-#define MAX_EXC_MEM_SIZE ( 4 + MAX_SCENE_INFO_SIZE + MAX_TSK_INFO_SIZE + MAX_QUEUE_INFO_SIZE + MAX_INT_INFO_SIZE + MAX_SWITCH_INFO_SIZE + MAX_MEM_INFO_SIZE + 4)
-
-VOID OsExcRegister(ExcInfoType type, EXC_INFO_SAVE_CALLBACK func, VOID *arg);
-VOID LOS_Reboot(VOID);
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-#endif

arch/arm/cortex-m/cortex-m4/los_hw_sr_gcc.s

@@ -1,131 +0,0 @@
-;
-; Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
-; Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without modification,
-; are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice, this list of
-;    conditions and the following disclaimer.
-;
-; 2. Redistributions in binary form must reproduce the above copyright notice, this list
-;    of conditions and the following disclaimer in the documentation and/or other materials
-;    provided with the distribution.
-;
-; 3. Neither the name of the copyright holder nor the names of its contributors may be used
-;    to endorse or promote products derived from this software without specific prior written
-;    permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
-; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-
- .syntax unified
- .arch armv7e-m
- .thumb
- .fpu vfpv4
-
-
-    .extern g_saveSRContext
-    .extern g_saveAR
-    .extern g_losTask
-
-    .global OsSRSaveRegister
-    .global OsSRRestoreRegister
-
-    .section .text
-    .thumb
-
-        .type OsSRSaveRegister, %function
-        .global OsSRSaveRegister
-OsSRSaveRegister:
-        .fnstart
-        .cantunwind
-        PUSH    {R2}
-        LDR     R2, =g_saveAR
-        STR     R0, [R2]
-        STR     R1, [R2, #4]
-        POP     {R2}
-
-        MRS     R0, PSP
-
-        VSTMDB  R0!, {D0-D7}
-        VMRS    R1, FPSCR
-        STMFD   R0!, {R1}       //FPSCR
-        STMFD   R0!, {R1}       //NO_NAME
-
-        MRS     R1,  PSR
-        ORR     R1, R1, #0x01000000
-        STMFD   R0!, {R1}
-
-        MOV     R1,  LR
-        STMFD   R0!, {R1}    // ;PC
-        STMFD   R0!, {R1}    // ;LR
-
-        STMFD   R0!, {R12}
-
-        MOV      R12,  R0
-
-        LDR     R0, =g_saveAR
-        LDR     R0, [R0]
-        LDR     R1, =g_saveAR
-        LDR     R1, [R1, #4]
-
-        STMFD   R12!, {R0-R3}
-        STMFD   R12!, {R4-R11}
-        VSTMDB  R12!, {D8-D15}
-
-        MRS     R0,  CONTROL
-        STMFD   R12!,  {R0}
-
-        MRS     R0,  MSP
-        STMFD   R12!,  {R0}
-
-        LDR     R1, =g_losTask
-        LDR     R1, [R1]
-        STR     R12, [R1]
-
-        MSR     PSP, R12
-        BX      LR
-        .fnend
-
-        .type OsSRSaveRegister, %function
-        .global OsSRSaveRegister
-OsSRRestoreRegister:
-        .fnstart
-        .cantunwind
-        MRS     R0, MSP
-        ADD     R0, R0, #8
-        MSR     MSP, R0
-
-        LDR     R0, =g_losTask
-        LDR     R0,  [R0]
-        LDR     R12, [R0]
-
-        LDR     R0, =g_saveSRContext
-        ADD     R0, R0, #120
-        MSR     PSP, R0
-
-        LDMFD   R12!,{R0}
-        MSR     MSP, R0
-
-        LDMFD   R12!,{R0}
-        MSR     CONTROL, R0
-
-        VLDMIA  R12!,{D8-D15}
-        LDMFD   R12!,{R4-R11}
-
-        MSR     PSP, R12
-        MOV     LR, #0xFFFFFFED
-        BX      LR
-
-        .fnend

arch/arm/cortex-m/include/los_exc.h

@@ -1,363 +0,0 @@
-/*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _LOS_EXC_H
-#define _LOS_EXC_H
-
-#include "los_hwi.h"
-#include "los_task_pri.h"
-#include "los_queue.h"
-#include "los_memcheck.h"
-#include "los_sys_pri.h"
-#ifdef LOSCFG_LIB_LIBC
-#include "string.h"
-#endif
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cpluscplus */
-#endif /* __cpluscplus */
-
-#define OS_EXC_IN_INIT                      0
-#define OS_EXC_IN_TASK                      1
-#define OS_EXC_IN_HWI                       2
-
-#define OS_EXC_MAX_BUF_LEN                  25
-#define OS_EXC_MAX_NEST_DEPTH               1
-
-#define OS_NVIC_SHCSR                       0xE000ED24
-#define OS_NVIC_CCR                         0xE000ED14
-
-#define OS_NVIC_INT_ENABLE_SIZE             0x20
-#define OS_NVIC_INT_PRI_SIZE                0xF0
-#define OS_NVIC_EXCPRI_SIZE          0xC
-
-#define OS_NVIC_INT_PEND_SIZE               OS_NVIC_INT_ACT_SIZE
-#define OS_NVIC_INT_ACT_SIZE                OS_NVIC_INT_ENABLE_SIZE
-
-#define OS_EXC_FLAG_NO_FLOAT                0x10000000
-#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
-#define OS_EXC_FLAG_IN_HWI                  0x02
-
-#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
-
-/**
- *@ingroup los_exc
- * the struct of register files
- *
- * description: the register files that saved when exception triggered
- *
- * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
- */
-typedef struct tagExcContext {
-    //handler save
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    UINT32 S16;
-    UINT32 S17;
-    UINT32 S18;
-    UINT32 S19;
-    UINT32 S20;
-    UINT32 S21;
-    UINT32 S22;
-    UINT32 S23;
-    UINT32 S24;
-    UINT32 S25;
-    UINT32 S26;
-    UINT32 S27;
-    UINT32 S28;
-    UINT32 S29;
-    UINT32 S30;
-    UINT32 S31;
-#endif
-    UINT32 uwR4;
-    UINT32 uwR5;
-    UINT32 uwR6;
-    UINT32 uwR7;
-    UINT32 uwR8;
-    UINT32 uwR9;
-    UINT32 uwR10;
-    UINT32 uwR11;
-    UINT32 uwPriMask;
-    //auto save
-    UINT32 uwSP;
-    UINT32 uwR0;
-    UINT32 uwR1;
-    UINT32 uwR2;
-    UINT32 uwR3;
-    UINT32 uwR12;
-    UINT32 uwLR;
-    UINT32 uwPC;
-    UINT32 uwxPSR;
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED) && (__FPU_USED== 1U)))
-    UINT32 S0;
-    UINT32 S1;
-    UINT32 S2;
-    UINT32 S3;
-    UINT32 S4;
-    UINT32 S5;
-    UINT32 S6;
-    UINT32 S7;
-    UINT32 S8;
-    UINT32 S9;
-    UINT32 S10;
-    UINT32 S11;
-    UINT32 S12;
-    UINT32 S13;
-    UINT32 S14;
-    UINT32 S15;
-    UINT32 FPSCR;
-    UINT32 NO_NAME;
-#endif
-}EXC_CONTEXT_S;
-
-typedef UINT32 (*EXC_INFO_SAVE_CALLBACK)(UINT32, VOID*);
-typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
-VOID OsExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
-
-/**
- * @ingroup  los_hwi
- * @brief: Exception initialization.
- *
- * @par Description:
- * This API is used to configure the exception function vector table.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- *@param uwArraySize [IN] Memory size of exception.
- *
- * @retval: None
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-VOID OsExcInit(UINT32 uwArraySize);
-
-extern VOID OsExcNMI(VOID);
-extern VOID OsExcHardFault(VOID);
-extern VOID OsExcMemFault(VOID);
-extern VOID OsExcBusFault(VOID);
-extern VOID OsExcUsageFault(VOID);
-extern VOID OsExcSvcCall(VOID);
-extern VOID OsBackTrace(VOID);
-extern UINT8 g_aucTaskArray[];
-
-/**
- *@ingroup los_exc
- *@brief Kernel panic function.
- *
- *@par Description:
- *Stack function that prints kernel panics.
- *@attention After this function is called and stack information is printed, the system will fail to respond.
- *@attention The input parameter can be NULL.
- *@param fmt [IN] Type #char* : variadic argument.
- *
- *@retval #None.
- *
- *@par Dependency:
- *los_exc.h: the header file that contains the API declaration.
- *@see None.
-*/
-VOID LOS_Panic(const CHAR *fmt, ...);
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:总线状态寄存器入栈时发生错误
- */
-#define OS_EXC_BF_STKERR           1
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:总线状态寄存器出栈时发生错误
- */
-#define OS_EXC_BF_UNSTKERR         2
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:总线状态寄存器不精确的数据访问违例
- */
-#define OS_EXC_BF_IMPRECISERR      3
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:总线状态寄存器精确的数据访问违例
- */
-#define OS_EXC_BF_PRECISERR        4
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:总线状态寄存器取指时的访问违例
- */
-#define OS_EXC_BF_IBUSERR          5
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:存储器管理状态寄存器入栈时发生错误
- */
-#define OS_EXC_MF_MSTKERR          6
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:存储器管理状态寄存器出栈时发生错误
- */
-#define OS_EXC_MF_MUNSTKERR        7
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:存储器管理状态寄存器数据访问违例
- */
-#define OS_EXC_MF_DACCVIOL         8
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:存储器管理状态寄存器取指访问违例
- */
-#define OS_EXC_MF_IACCVIOL         9
-
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:用法错误，表示除法运算时除数为零
- */
-#define OS_EXC_UF_DIVBYZERO        10
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:用法错误，未对齐访问导致的错误
- */
-#define OS_EXC_UF_UNALIGNED        11
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:用法错误，试图执行协处理器相关指令
- */
-#define OS_EXC_UF_NOCP             12
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:用法错误，在异常返回时试图非法地加载EXC_RETURN到PC
- */
-#define OS_EXC_UF_INVPC            13
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:用法错误，试图切入ARM状态
- */
-#define OS_EXC_UF_INVSTATE         14
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:用法错误，执行的指令其编码是未定义的——解码不能
- */
-#define OS_EXC_UF_UNDEFINSTR       15
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:NMI中断
- */
-
-#define OS_EXC_CAUSE_NMI           16
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:硬fault
- */
-#define OS_EXC_CAUSE_HARDFAULT     17
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:任务处理函数退出
- */
-#define OS_EXC_CAUSE_TASK_EXIT     18
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:致命错误
- */
-#define OS_EXC_CAUSE_FATAL_ERR     19
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:调试事件导致的硬fault
- */
-#define OS_EXC_CAUSE_DEBUGEVT      20
-
-/**
- *@ingroup los_exc
- *Cortex-M3异常具体类型:取向量时发生的硬fault
- */
-#define OS_EXC_CAUSE_VECTBL        21
-
-/**
- *@ingroup los_exc
- * 异常信息结构体
- *
- * 描述:M4平台下的异常触发时保存的异常信息
- *
- */
-typedef struct tagExcInfo {
-    /**< 异常发生阶段： 0表示异常发生在初始化中，1表示异常发生在任务中，2表示异常发生在中断中 */
-    UINT16 phase;
-    /**< 异常类型,出异常时对照上面列出的1-19号 */
-    UINT16 type;
-    /**< 若为精确地址访问错误表示异常发生时的错误访问地址 */
-    UINT32 faultAddr;
-    /**< 在中断中发生异常，表示中断号。在任务中发生异常，表示任务id，如果发生在初始化中，则为0xffffffff */
-    UINT32 thrdPid;
-    /**< 异常嵌套个数，目前仅支持第一次进入异常时执行注册的钩子函数 */
-    UINT16 nestCnt;
-    /**< 保留 */
-    UINT16 reserved;
-    /**< 自动压栈浮点寄存器的异常发生时刻的硬件上下文 */
-    EXC_CONTEXT_S * context;
-} ExcInfo;
-
-extern UINT32 g_curNestCount;
-extern UINT32 g_vuwIntCount;
-
-static VOID OsExcSave2DDR(VOID);
-VOID OsExcInfoDisplay(ExcInfo *exc);
-
-
-extern TaskSwitchInfo g_taskSwitchInfo;
-extern UINT8 g_uwExcTbl[32];
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cpluscplus */
-#endif /* __cpluscplus */
-
-#endif /* _LOS_EXC_H */
-

arch/arm/cortex-m/include/los_hw.h

@@ -1,233 +0,0 @@
-/*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * @defgroup los_hw hardware
- * @ingroup kernel
- */
-
-#ifndef _LOS_HW_H
-#define _LOS_HW_H
-
-#include "los_base.h"
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-/* *
- * @ingroup los_hw
- * The initialization value of stack space.
- */
-#define EMPTY_STACK        0xCACA
-
-/* *
- * @ingroup los_hw
- * Trigger a task.
- */
-#define OsTaskTrap() __asm("   TRAP    #31")
-
-/* *
- * @ingroup los_hw
- * Check task schedule.
- */
-#define LOS_CHECK_SCHEDULE ((!g_losTaskLock))
-
-/* *
- * @ingroup los_hw
- * Define the type of a task context control block.
- */
-typedef struct tagTskContext {
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
-    UINT32 S16;
-    UINT32 S17;
-    UINT32 S18;
-    UINT32 S19;
-    UINT32 S20;
-    UINT32 S21;
-    UINT32 S22;
-    UINT32 S23;
-    UINT32 S24;
-    UINT32 S25;
-    UINT32 S26;
-    UINT32 S27;
-    UINT32 S28;
-    UINT32 S29;
-    UINT32 S30;
-    UINT32 S31;
-#endif
-    UINT32 uwR4;
-    UINT32 uwR5;
-    UINT32 uwR6;
-    UINT32 uwR7;
-    UINT32 uwR8;
-    UINT32 uwR9;
-    UINT32 uwR10;
-    UINT32 uwR11;
-    UINT32 uwPriMask;
-    UINT32 uwR0;
-    UINT32 uwR1;
-    UINT32 uwR2;
-    UINT32 uwR3;
-    UINT32 uwR12;
-    UINT32 uwLR;
-    UINT32 uwPC;
-    UINT32 uwxPSR;
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
-    UINT32 S0;
-    UINT32 S1;
-    UINT32 S2;
-    UINT32 S3;
-    UINT32 S4;
-    UINT32 S5;
-    UINT32 S6;
-    UINT32 S7;
-    UINT32 S8;
-    UINT32 S9;
-    UINT32 S10;
-    UINT32 S11;
-    UINT32 S12;
-    UINT32 S13;
-    UINT32 S14;
-    UINT32 S15;
-    UINT32 FPSCR;
-    UINT32 NO_NAME;
-#endif
-} TaskContext;
-
-/* *
- * @ingroup  los_hw
- * @brief: Task stack initialization.
- *
- * @par Description:
- * This API is used to initialize the task stack.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param  taskID     [IN] Type#UINT32: TaskID.
- * @param  stackSize  [IN] Type#UINT32: Total size of the stack.
- * @param  topStack   [IN] Type#VOID *: Top of task's stack.
- *
- * @retval: context Type#TaskContext *.
- * @par Dependency:
- * <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern VOID *OsTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack);
-
-/* *
- * @ingroup  los_hw
- * @brief: Task scheduling Function.
- *
- * @par Description:
- * This API is used to scheduling task.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param  None.
- *
- * @retval: None.
- * @par Dependency:
- * <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern VOID OsSchedule(VOID);
-
-/* *
- * @ingroup  los_hw
- * @brief: Function to determine whether task scheduling is required.
- *
- * @par Description:
- * This API is used to Judge and entry task scheduling.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param  None.
- *
- * @retval: None.
- * @par Dependency:
- * <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern VOID LOS_Schedule(VOID);
-
-/**
- * @ingroup  los_hw
- * @brief: Function to task exit.
- *
- * @par Description:
- * This API is used to exit task.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param  None.
- *
- * @retval: None.
- * @par Dependency:
- * <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-LITE_OS_SEC_TEXT_MINOR VOID OsTaskExit(VOID);
-
-/* *
- * @ingroup  los_hw
- * @brief: The M3 wait interrupt instruction.
- *
- * @par Description:
- * This API is used to make CPU enter to power-save mode.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param  None.
- *
- * @retval: None.
- * @par Dependency:
- * <ul><li>los_hw.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern VOID OsEnterSleep(VOID);
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-#endif /* _LOS_HW_H */
-

arch/arm/cortex-m/include/los_hwi.h

@@ -1,720 +0,0 @@
-/*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * @defgroup los_hwi Hardware interrupt
- * @ingroup kernel
- */
-#ifndef _LOS_HWI_H
-#define _LOS_HWI_H
-
-#include "los_base.h"
-#include "los_sys.h"
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-/* *
- * @ingroup los_hwi
- * Maximum number of used hardware interrupts.
- */
-#ifndef OS_HWI_MAX_NUM
-#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
-#endif
-
-/* *
- * @ingroup los_hwi
- * Highest priority of a hardware interrupt.
- */
-#ifndef OS_HWI_PRIO_HIGHEST
-#define OS_HWI_PRIO_HIGHEST                   0
-#endif
-
-/* *
- * @ingroup los_hwi
- * Lowest priority of a hardware interrupt.
- */
-#ifndef OS_HWI_PRIO_LOWEST
-#define OS_HWI_PRIO_LOWEST                    7
-#endif
-
-/* *
- * @ingroup los_config
- * Configuration item for interrupt with argument
- */
-#ifndef OS_HWI_WITH_ARG
-#define OS_HWI_WITH_ARG                       NO
-#endif
-
-/* *
- * @ingroup los_hwi
- * Define the type of a hardware interrupt number.
- */
-typedef UINT32 HWI_HANDLE_T;
-
-/* *
- * @ingroup los_hwi
- * Define the type of a hardware interrupt priority.
- */
-typedef UINT16 HWI_PRIOR_T;
-
-/* *
- * @ingroup los_hwi
- * Define the type of hardware interrupt mode configurations.
- */
-typedef UINT16 HWI_MODE_T;
-
-/* *
- * @ingroup los_hwi
- * Define the type of the parameter used for the hardware interrupt creation function. The function of this parameter varies among platforms.
- */
-typedef UINT32 HWI_ARG_T;
-
-/* *
- * @ingroup  los_hwi
- * Define the type of a hardware interrupt handling function.
- */
-#if (OS_HWI_WITH_ARG == YES)
-
-typedef VOID (*HWI_PROC_FUNC)(VOID *parm);
-typedef struct {
-    HWI_PROC_FUNC pfnHandler;
-    VOID *pParm;
-} HWI_SLAVE_FUNC;
-
-#else
-
-typedef VOID (*HWI_PROC_FUNC)(void);
-
-#endif
-
-/* *
- * @ingroup  los_hwi
- * Define the type of a hardware interrupt vector table function.
- */
-typedef VOID (**HWI_VECTOR_FUNC)(void);
-
-/* *
- * @ingroup los_hwi
- * Count of interrupts.
- */
-extern UINT32 g_vuwIntCount;
-
-/* *
- * @ingroup los_hwi
- * An interrupt is active.
- */
-#define OS_INT_ACTIVE                         (g_vuwIntCount > 0)
-
-/* *
- * @ingroup los_hwi
- * An interrupt is inactive.
- */
-#define OS_INT_INACTIVE                       (!(OS_INT_ACTIVE))
-
-/* *
- * @ingroup los_hwi
- * Count of M-Core system interrupt vector.
- */
-#define OS_SYS_VECTOR_CNT                     16
-
-/* *
- * @ingroup los_hwi
- * Count of M-Core interrupt vector.
- */
-#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
-
-/* *
- * @ingroup los_hwi
- * AIRCR register priority group parameter .
- */
-#define OS_NVIC_AIRCR_PRIGROUP                7
-
-/* *
- * @ingroup los_hwi
- * Boot interrupt vector table.
- */
-extern UINT32 _BootVectors[];
-
-/* *
- * @ingroup los_hwi
- * Hardware interrupt error code: Invalid interrupt number.
- *
- * Value: 0x02000900
- *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
- */
-#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
-
-/* *
- * @ingroup los_hwi
- * Hardware interrupt error code: Null hardware interrupt handling function.
- *
- * Value: 0x02000901
- *
- * Solution: Pass in a valid non-null hardware interrupt handling function.
- */
-#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
-
-/* *
- * @ingroup los_hwi
- * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
- *
- * Value: 0x02000902
- *
- * Solution: Increase the configured maximum number of supported hardware interrupts.
- */
-#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
-
-/* *
- * @ingroup los_hwi
- * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
- *
- * Value: 0x02000903
- *
- * Solution: Expand the configured memory.
- */
-#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
-
-/* *
- * @ingroup los_hwi
- * Hardware interrupt error code: The interrupt has already been created.
- *
- * Value: 0x02000904
- *
- * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
- */
-#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
-
-/* *
- * @ingroup los_hwi
- * Hardware interrupt error code: Invalid interrupt priority.
- *
- * Value: 0x02000905
- *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
- */
-#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
-
-/* *
- * @ingroup los_hwi
- * Hardware interrupt error code: Incorrect interrupt creation mode.
- *
- * Value: 0x02000906
- *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
- */
-#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
-
-/* *
- * @ingroup los_hwi
- * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
- *
- * Value: 0x02000907
- *
- * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
- */
-#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
-
-/* *
- * @ingroup los_hwi
- * SysTick control and status register.
- */
-#define OS_SYSTICK_CONTROL_REG                0xE000E010
-
-/* *
- * @ingroup los_hw
- * SysTick current value register.
- */
-#define OS_SYSTICK_CURRENT_REG                0xE000E018
-
-/* *
- * @ingroup los_hwi
- * Interrupt Priority-Level Registers.
- */
-#define OS_NVIC_PRI_BASE                      0xE000E400
-
-/* *
- * @ingroup los_hwi
- * Interrupt enable register for 0-31.
- */
-#define OS_NVIC_SETENA_BASE                   0xE000E100
-
-/* *
- * @ingroup los_hwi
- * interrupt pending register.
- */
-#define OS_NVIC_SETPEND_BASE                  0xE000E200
-
-/* *
- * @ingroup los_hwi
- * Interrupt active register.
- */
-#define OS_NVIC_INT_ACT_BASE                  0xE000E300
-
-/* *
- * @ingroup los_hwi
- * Interrupt disable register for 0-31.
- */
-#define OS_NVIC_CLRENA_BASE                   0xE000E180
-
-/* *
- * @ingroup los_hwi
- * Interrupt control and status register.
- */
-#define OS_NVIC_INT_CTRL                      0xE000ED04
-
-/* *
- * @ingroup los_hwi
- * Vector table offset register.
- */
-#define OS_NVIC_VTOR                          0xE000ED08
-
-/* *
- * @ingroup los_hwi
- * Application interrupt and reset control register
- */
-#define OS_NVIC_AIRCR                         0xE000ED0C
-
-/* *
- * @ingroup los_hwi
- * System exception priority register.
- */
-#define OS_NVIC_EXCPRI_BASE                   0xE000ED18
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 1 :reset.
- */
-#define OS_EXC_RESET                          1
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 2 :Non-Maskable Interrupt.
- */
-#define OS_EXC_NMI                            2
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 3 :(hard)fault.
- */
-#define OS_EXC_HARD_FAULT                     3
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 4 :MemManage fault.
- */
-#define OS_EXC_MPU_FAULT                      4
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 5 :Bus fault.
- */
-#define OS_EXC_BUS_FAULT                      5
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 6 :Usage fault.
- */
-#define OS_EXC_USAGE_FAULT                    6
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 11 :SVCall.
- */
-#define OS_EXC_SVC_CALL                       11
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 12 :Debug monitor.
- */
-#define OS_EXC_DBG_MONITOR                    12
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 14 :PendSV.
- */
-#define OS_EXC_PEND_SV                        14
-
-/* *
- * @ingroup los_hwi
- * Interrupt No. 15 :SysTick.
- */
-#define OS_EXC_SYS_TICK                       15
-
-/* *
- * @ingroup los_hwi
- * hardware interrupt form mapping handling function array.
- */
-extern HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT];
-
-#if (OS_HWI_WITH_ARG == YES)
-/* *
- * @ingroup los_hwi
- * hardware interrupt Slave form mapping handling function array.
- */
-extern HWI_SLAVE_FUNC g_hwiSlaveForm[OS_VECTOR_CNT];
-
-/* *
- * @ingroup los_hwi
- * Set interrupt vector table.
- */
-#define OsSetVectonr(num, vector, arg)                                    \
-    do {                                                                      \
-        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)OsInterrupt; \
-        g_hwiSlaveForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;  \
-        g_hwiSlaveForm[num + OS_SYS_VECTOR_CNT].pParm = (VOID *)arg;     \
-    } while(0)
-#else
-/* *
- * @ingroup los_hwi
- * hardware interrupt Slave form mapping handling function array.
- */
-extern HWI_PROC_FUNC g_hwiSlaveForm[OS_VECTOR_CNT];
-
-/* *
- * @ingroup los_hwi
- * Set interrupt vector table.
- */
-#define OsSetVector(num, vector)                             \
-    do {                                                          \
-        g_hwiForm[num + OS_SYS_VECTOR_CNT] = OsInterrupt;    \
-        g_hwiSlaveForm[num + OS_SYS_VECTOR_CNT] = vector; \
-    } while(0)
-#endif
-
-/* *
- * @ingroup  los_hwi
- * @brief Create a hardware interrupt.
- *
- * @par Description:
- * This API is used to configure a hardware interrupt and register a hardware interrupt handling function.
- *
- * @attention
- * <ul>
- * <li>The hardware interrupt module is usable only when the configuration item for hardware interrupt tailoring is enabled.</li>
- * <li>Hardware interrupt number value range: [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. The value range applicable for a Cortex-A7 platform is [32,95].</li>
- * <li>OS_HWI_MAX_NUM specifies the maximum number of interrupts that can be created.</li>
- * <li>Before executing an interrupt on a platform, refer to the chip manual of the platform.</li>
- * </ul>
- *
- * @param  hwiNum   [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable for a Cortex-A7 platform is [32,95].
- * @param  hwiPrio  [IN] Type#HWI_PRIOR_T: hardware interrupt priority. Ignore this parameter temporarily.
- * @param  mode     [IN] Type#HWI_MODE_T: hardware interrupt mode. Ignore this parameter temporarily.
- * @param  handler  [IN] Type#HWI_PROC_FUNC: interrupt handler used when a hardware interrupt is triggered.
- * @param  arg      [IN] Type#HWI_ARG_T: input parameter of the interrupt handler used when a hardware interrupt is triggered.
- *
- * @retval #OS_ERRNO_HWI_PROC_FUNC_NULL               0x02000901: Null hardware interrupt handling function.
- * @retval #OS_ERRNO_HWI_NUM_INVALID                  0x02000900: Invalid interrupt number.
- * @retval #OS_ERRNO_HWI_NO_MEMORY                    0x02000903: Insufficient memory for hardware interrupt creation.
- * @retval #OS_ERRNO_HWI_ALREADY_CREATED              0x02000904: The interrupt handler being created has already been created.
- * @retval #LOS_OK                                    0         : The interrupt is successfully created.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 LOS_HwiCreate(HWI_HANDLE_T hwiNum,
-                            HWI_PRIOR_T hwiPrio,
-                            HWI_MODE_T mode,
-                            HWI_PROC_FUNC handler,
-                            HWI_ARG_T arg);
-
-/* *
- * @ingroup  los_hwi
- * @brief: Hardware interrupt entry function.
- *
- * @par Description:
- * This API is used as all hardware interrupt handling function entry.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param:None.
- *
- * @retval:None.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern VOID OsInterrupt(VOID);
-
-/* *
- * @ingroup  los_hwi
- * @brief: Get a interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 OsIntNumGet(VOID);
-
-/* *
- * @ingroup  los_hwi
- * @brief: Default vector handling function.
- *
- * @par Description:
- * This API is used to configure interrupt for null function.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param:None.
- *
- * @retval:None.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li
-></ul>
- * @see None.
- */
-extern VOID OsHwiDefaultHandler(VOID);
-
-/* *
- * @ingroup  los_hwi
- * @brief: Reset the vector table.
- *
- * @par Description:
- * This API is used to reset the vector table.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param:None.
- *
- * @retval:None.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern VOID Reset_Handler(VOID);
-
-/* *
- * @ingroup  los_hwi
- * @brief: Pended System Call.
- *
- * @par Description:
- * PendSV can be pended and is useful for an OS to pend an exception
- * so that an action can be performed after other important tasks are completed.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param:None.
- *
- * @retval:None.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern VOID osPendSV(VOID);
-
-/* *
- * @ingroup los_hwi
- * @brief Enable all interrupts.
- *
- * @par Description:
- * <ul>
- * <li>This API is used to enable all IRQ and FIQ interrupts in the CPSR.</li>
- * </ul>
- * @attention
- * <ul>
- * <li>None.</li>
- * </ul>
- *
- * @param None.
- *
- * @retval CPSR value obtained after all interrupts are enabled.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see LOS_IntRestore
- */
-extern UINTPTR LOS_IntUnLock(VOID);
-
-/* *
- * @ingroup los_hwi
- * @brief Disable all interrupts.
- *
- * @par Description:
- * <ul>
- * <li>This API is used to disable all IRQ and FIQ interrupts in the CPSR.</li>
- * </ul>
- * @attention
- * <ul>
- * <li>None.</li>
- * </ul>
- *
- * @param None.
- *
- * @retval CPSR value obtained before all interrupts are disabled.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see LOS_IntRestore
- */
-extern UINTPTR LOS_IntLock(VOID);
-
-/* *
- * @ingroup los_hwi
- * @brief Restore interrupts.
- *
- * @par Description:
- * <ul>
- * <li>This API is used to restore the CPSR value obtained before all interrupts are disabled.</li>
- * </ul>
- * @attention
- * <ul>
- * <li>This API can be called only after all interrupts are disabled, and the input parameter value should be the value returned by calling the all interrupt disabling API.</li>
- * </ul>
- *
- * @param intSave [IN] CPSR value obtained before all interrupts are disabled.
- *
- * @retval None.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see LOS_IntLock
- */
-extern VOID LOS_IntRestore(UINTPTR intSave);
-
-/* *
- * @ingroup los_hwi
- * @brief Get value from xPSR register.
- *
- * @par Description:
- * <ul>
- * <li>This API is used to Get value from xPSR register.</li>
- * </ul>
- * @attention
- * <ul>
- * <li>None.</li>
- * </ul>
- *
- * @param  cntHi  [IN] CpuTick High 4 byte
- * @param  cntLo  [IN] CpuTick Low 4 byte
- *
- * @retval None.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see LOS_IntRestore
- */
-extern VOID LOS_GetCpuCycle(UINT32 *cntHi, UINT32 *cntLo);
-
-#if (LOSCFG_KERNEL_TICKLESS == YES)
-/**
- * @ingroup los_hwi
- * @brief reconfig systick, and clear SysTick_IRQn.
- *
- * @par Description:
- * <ul>
- * <li>This API is used to reconfig systick, and clear SysTick_IRQn.</li>
- * </ul>
- * @attention
- * <ul>
- * <li>None.</li>
- * </ul>
- *
- * @param  cyclesPerTick  [IN] Cycles Per Tick
- *
- * @retval None.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see LOS_IntRestore
- */
-extern VOID LOS_SysTickReload(UINT32 cyclesPerTick);
-#endif
-
-/**
- * @ingroup los_hwi
- * @brief Get System cycle count.
- *
- * @par Description:
- * <ul>
- * <li>This API is used to Get System cycle count.</li>
- * </ul>
- * @attention
- * <ul>
- * <li>None.</li>
- * </ul>
- *
- * @param  None.
- *
- * @retval: The value of the system cycle count.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see LOS_IntRestore
- */
-extern VOID LOS_GetCpuCycle(UINT32 *puwCntHi, UINT32 *puwCntLo);
-extern VOID LOS_GetSystickCycle(UINT32 *puwCntHi, UINT32 *puwCntLo);
-
-extern UINT32 LOS_SysTickCurrCycleGet(VOID);
-
-/* *
- * @ingroup  los_hwi
- * @brief Delete hardware interrupt.
- *
- * @par Description:
- * This API is used to delete hardware interrupt.
- *
- * @attention
- * <ul>
- * <li>The hardware interrupt module is usable only when the configuration item for hardware interrupt tailoring is enabled.</li>
- * <li>Hardware interrupt number value range: [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. The value range applicable for a Cortex-A7 platform is [32,95].</li>
- * <li>OS_HWI_MAX_NUM specifies the maximum number of interrupts that can be created.</li>
- * <li>Before executing an interrupt on a platform, refer to the chip manual of the platform.</li>
- * </ul>
- *
- * @param  hwiNum   [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable for a Cortex-A7 platform is [32,95].
- *
- * @retval #OS_ERRNO_HWI_NUM_INVALID              0x02000900: Invalid interrupt number.
- * @retval #LOS_OK                                0         : The interrupt is successfully delete.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 LOS_HwiDelete(HWI_HANDLE_T hwiNum);
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-#endif /* _LOS_HWI_H */
-

arch/arm/cortex-m/src/los_hw_tick.c

@@ -1,210 +0,0 @@
-/*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "los_tick_pri.h"
-#include "los_base.h"
-#include "los_task_pri.h"
-#include "los_swtmr.h"
-#include "los_hwi.h"
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cpluscplus */
-#endif /* __cpluscplus */
-
-#define TICK_CHECK                           0x4000000
-#define CYCLE_CHECK                          0xFFFFFFFFU
-#define SHIFT_32_BIT                          32
-
-
-/* ****************************************************************************
-Function    : OsTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 OsTickStart(VOID)
-{
-    UINT32 ret;
-
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
-
-#if (OS_HWI_WITH_ARG == YES)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)OsTickHandler, NULL);
-#else
-    OsSetVector(SysTick_IRQn, OsTickHandler);
-#endif
-
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-    g_ullTickCount = 0;
-
-    ret = SysTick_Config(g_cyclesPerTick);
-    if (ret == 1) {
-        return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
-    }
-
-    return LOS_OK;
-}
-
-#if (LOSCFG_KERNEL_TICKLESS == YES)
-/* ****************************************************************************
-Function    : LOS_SysTickReload
-Description : reconfig systick, and clear SysTick_IRQn
-Input       : cyclesPerTick --- cycles Per Tick
-output      : none
-return      : none
-**************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID LOS_SysTickReload(UINT32 cyclesPerTick)
-{
-    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-    NVIC_ClearPendingIRQ(SysTick_IRQn);
-    SysTick->LOAD = (UINT32)(cyclesPerTick - 1UL); /* set reload register */
-    SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
-}
-#endif
-
-/* ****************************************************************************
-Function    : LOS_SysTickCurrCycleGet
-Description : Get System cycle count
-Input       : none
-output      : none
-return      : hwCycle --- the system cycle count
-**************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 LOS_SysTickCurrCycleGet(VOID)
-{
-    UINT32 hwCycle;
-    UINTPTR intSave;
-
-    intSave = LOS_IntLock();
-    hwCycle = SysTick->VAL;
-
-    /* tick has come, but may interrupt environment, not counting the Tick interrupt response, to do +1 */
-    if ((SCB->ICSR & TICK_CHECK) != 0) {
-        hwCycle = SysTick->VAL;
-        hwCycle += g_cyclesPerTick;
-    }
-
-    LOS_IntRestore(intSave);
-
-    return hwCycle;
-}
-
-/* ****************************************************************************
-Function    : LOS_GetCpuCycle
-Description : Get System cycle count
-Input       : none
-output      : cntHi  --- CpuTick High 4 byte
-              cntLo  --- CpuTick Low 4 byte
-return      : none
-**************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID LOS_GetCpuCycle(UINT32 *cntHi, UINT32 *cntLo)
-{
-    UINT64 swTick;
-    UINT64 cycle;
-    UINT32 hwCycle;
-    UINTPTR intSave;
-
-    intSave = LOS_IntLock();
-
-    swTick = g_ullTickCount;
-    hwCycle = SysTick->VAL;
-
-    /* tick has come, but may interrupt environment, not counting the Tick interrupt response, to do +1 */
-    if ((SCB->ICSR & TICK_CHECK) != 0) {
-        hwCycle = SysTick->VAL;
-        swTick++;
-    }
-
-    cycle = (((swTick) * g_cyclesPerTick) + (g_cyclesPerTick - hwCycle));
-
-    *cntHi = cycle >> SHIFT_32_BIT;
-    *cntLo = cycle & CYCLE_CHECK;
-
-    LOS_IntRestore(intSave);
-
-    return;
-}
-
-/* ****************************************************************************
-Function    : LOS_GetSystickCycle
-Description : Get Sys tick cycle count
-Input       : none
-output      : cntHi  --- SysTick count High 4 byte
-              cntLo  --- SysTick count Low 4 byte
-return      : none
-**************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID LOS_GetSystickCycle(UINT32 *cntHi, UINT32 *cntLo)
-{
-    UINT64 swTick;
-    UINT64 cycle;
-    UINT32 hwCycle;
-    UINTPTR intSave;
-    UINT32 systickLoad;
-    UINT32 systickCur;
-
-    intSave = LOS_IntLock();
-
-    swTick = g_ullTickCount;
-
-    systickLoad = SysTick->LOAD;
-    systickCur = SysTick->VAL;
-    if (systickLoad < systickCur) {
-        LOS_IntRestore(intSave);
-        return;
-    }
-    hwCycle = systickLoad - systickCur;
-
-    /* tick has come, but may interrupt environment, not counting the Tick interrupt response, to do +1 */
-    if ((SCB->ICSR & TICK_CHECK) != 0) {
-        hwCycle = systickLoad - systickCur;
-        swTick++;
-    }
-
-    cycle = hwCycle + swTick * systickLoad;
-    *cntHi = cycle >> SHIFT_32_BIT;
-    *cntLo = cycle & CYCLE_CHECK;
-
-    LOS_IntRestore(intSave);
-
-    return;
-}
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cpluscplus */
-#endif /* __cpluscplus */

arch/arm/cortex-m/src/los_hwi.c

@@ -1,254 +0,0 @@
-/*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "los_hwi.h"
-#include "los_sr.h"
-
-#if (LOSCFG_KERNEL_TICKLESS == YES)
-#include "los_tickless_pri.h"
-#endif
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-/*lint -save -e40 -e522 -e533*/
-__weak VOID SysTickHandler(VOID)
-{
-    return;
-}
-
-UINT32 g_vuwIntCount = 0;
-/*lint -restore*/
-#ifdef __ICCARM__
-#pragma location = ".data.vector"
-#elif defined(__CC_ARM) || defined(__GNUC__)
-LITE_OS_SEC_VEC
-#endif
-
-HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {
-    (HWI_PROC_FUNC)0,                    // [0] Top of Stack
-    (HWI_PROC_FUNC)Reset_Handler,        // [1] reset
-    (HWI_PROC_FUNC)OsHwiDefaultHandler,  // [2] NMI Handler
-    (HWI_PROC_FUNC)OsHwiDefaultHandler,  // [3] Hard Fault Handler
-    (HWI_PROC_FUNC)OsHwiDefaultHandler,  // [4] MPU Fault Handler
-    (HWI_PROC_FUNC)OsHwiDefaultHandler,  // [5] Bus Fault Handler
-    (HWI_PROC_FUNC)OsHwiDefaultHandler,  // [6] Usage Fault Handler
-    (HWI_PROC_FUNC)0,                    // [7] Reserved
-    (HWI_PROC_FUNC)0,                    // [8] Reserved
-    (HWI_PROC_FUNC)0,                    // [9] Reserved
-    (HWI_PROC_FUNC)0,                    // [10] Reserved
-    (HWI_PROC_FUNC)OsHwiDefaultHandler,  // [11] SVCall Handler
-    (HWI_PROC_FUNC)OsHwiDefaultHandler,  // [12] Debug Monitor Handler
-    (HWI_PROC_FUNC)0,                    // [13] Reserved
-    (HWI_PROC_FUNC)osPendSV,             // [14] PendSV Handler
-    (HWI_PROC_FUNC)SysTickHandler,      // [15] SysTick Handler
-};
-#if (OS_HWI_WITH_ARG == YES)
-HWI_SLAVE_FUNC g_hwiSlaveForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
-#else
-HWI_PROC_FUNC g_hwiSlaveForm[OS_VECTOR_CNT] = {0};
-#endif
-
-/* ****************************************************************************
- Function    : OsIntNumGet
- Description : Get a interrupt number
- Input       : None
- Output      : None
- Return      : Interrupt Indexes number
- **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 OsIntNumGet(VOID)
-{
-    return __get_IPSR();
-}
-
-/* ****************************************************************************
- Function    : OsHwiDefaultHandler
- Description : default handler of the hardware interrupt
- Input       : None
- Output      : None
- Return      : None
- **************************************************************************** */
-/*lint -e529*/
-LITE_OS_SEC_TEXT_MINOR VOID OsHwiDefaultHandler(VOID)
-{
-    UINT32 irqNum = OsIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
-    while (1) {}
-}
-
-/* ****************************************************************************
- Function    : OsInterrupt
- Description : Hardware interrupt entry function
- Input       : None
- Output      : None
- Return      : None
- **************************************************************************** */
-LITE_OS_SEC_TEXT VOID OsInterrupt(VOID)
-{
-    UINT32 hwiIndex;
-    UINT32 intSave;
-
-#if (LOSCFG_KERNEL_RUNSTOP == YES)
-    SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
-#endif
-
-    intSave = LOS_IntLock();
-
-    g_vuwIntCount++;
-
-    LOS_IntRestore(intSave);
-
-    hwiIndex = OsIntNumGet();
-#if (LOSCFG_KERNEL_TICKLESS == YES)
-    osUpdateKernelTickCount(hwiIndex);
-#endif
-
-#if (OS_HWI_WITH_ARG == YES)
-    if (g_hwiSlaveForm[hwiIndex].pfnHandler != 0) {
-        g_hwiSlaveForm[hwiIndex].pfnHandler((VOID *)g_hwiSlaveForm[hwiIndex].pParm);
-    }
-#else
-    if (g_hwiSlaveForm[hwiIndex] != 0) {
-        g_hwiSlaveForm[hwiIndex]();
-    }
-#endif
-    intSave = LOS_IntLock();
-    g_vuwIntCount--;
-    LOS_IntRestore(intSave);
-}
-
-/* ****************************************************************************
- Function    : OsHwiInit
- Description : initialization of the hardware interrupt
- Input       : None
- Output      : None
- Return      : None
- **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID OsHwiInit()
-{
-    UINT32 index;
-
-    for (index = OS_SYS_VECTOR_CNT; index < OS_VECTOR_CNT; index++) {
-        g_hwiForm[index] = (HWI_PROC_FUNC)OsHwiDefaultHandler;
-    }
-
-    /* Interrupt vector table location */
-    SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
-#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
-    NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
-#endif
-
-    return;
-}
-/* ****************************************************************************
- Function    : LOS_HwiCreate
- Description : create hardware interrupt
- Input       : hwiNum   --- hwi num to create
-               hwiPrio  --- priority of the hwi
-               mode     --- unused
-               handler --- hwi handler
-               arg      --- param of the hwi handler
- Output      : None
- Return      : LOS_OK on success or error code on failure
- **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 LOS_HwiCreate(HWI_HANDLE_T hwiNum,
-                                           HWI_PRIOR_T hwiPrio,
-                                           HWI_MODE_T mode,
-                                           HWI_PROC_FUNC handler,
-                                           HWI_ARG_T arg)
-{
-    UINTPTR intSave;
-
-    if (handler == NULL) {
-        return OS_ERRNO_HWI_PROC_FUNC_NULL;
-    }
-
-    if (hwiNum >= OS_HWI_MAX_NUM) {
-        return OS_ERRNO_HWI_NUM_INVALID;
-    }
-
-    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)OsHwiDefaultHandler) {
-        return OS_ERRNO_HWI_ALREADY_CREATED;
-    }
-
-    if (hwiPrio > OS_HWI_PRIO_LOWEST) {
-        return OS_ERRNO_HWI_PRIO_INVALID;
-    }
-
-    intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == YES)
-    OsSetVector(hwiNum, handler, arg);
-#else
-    OsSetVector(hwiNum, handler);
-#endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
-
-    LOS_IntRestore(intSave);
-
-    return LOS_OK;
-}
-
-/* ****************************************************************************
- Function    : LOS_HwiDelete
- Description : Delete hardware interrupt
- Input       : hwiNum   --- hwi num to delete
- Output      : None
- Return      : LOS_OK on success or error code on failure
- **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 LOS_HwiDelete(HWI_HANDLE_T hwiNum)
-{
-    UINT32 intSave;
-
-    if (hwiNum >= OS_HWI_MAX_NUM) {
-        return OS_ERRNO_HWI_NUM_INVALID;
-    }
-
-    NVIC_DisableIRQ((IRQn_Type)hwiNum);
-
-    intSave = LOS_IntLock();
-
-    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)OsHwiDefaultHandler;
-
-    LOS_IntRestore(intSave);
-
-    return LOS_OK;
-}
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-

arch/arm/cortex-m3/keil/los_arch_atomic.h

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/arm/cortex-m3/keil/los_arch_context.h

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct TagTskContext {
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} TaskContext;
+
+/**
+ * @ingroup  los_config
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */

arch/arm/cortex-m3/keil/los_arch_interrupt.h

@@ -0,0 +1,683 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_INTERRUPT_H
+#define _LOS_ARCH_INTERRUPT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST                   0
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST                    7
+#endif
+
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of M-Core system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT                     16
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of M-Core interrupt vector.
+ */
+#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * AIRCR register priority group parameter .
+ */
+#define OS_NVIC_AIRCR_PRIGROUP                7
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Boot interrupt vector table.
+ */
+extern UINT32 _BootVectors[];
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M3 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M3 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * SysTick control and status register.
+ */
+#define OS_SYSTICK_CONTROL_REG                0xE000E010
+
+/* *
+ * @ingroup los_hw
+ * SysTick current value register.
+ */
+#define OS_SYSTICK_CURRENT_REG                0xE000E018
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt Priority-Level Registers.
+ */
+#define OS_NVIC_PRI_BASE                      0xE000E400
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt enable register for 0-31.
+ */
+#define OS_NVIC_SETENA_BASE                   0xE000E100
+
+/* *
+ * @ingroup los_arch_interrupt
+ * interrupt pending register.
+ */
+#define OS_NVIC_SETPEND_BASE                  0xE000E200
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt active register.
+ */
+#define OS_NVIC_INT_ACT_BASE                  0xE000E300
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt disable register for 0-31.
+ */
+#define OS_NVIC_CLRENA_BASE                   0xE000E180
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt control and status register.
+ */
+#define OS_NVIC_INT_CTRL                      0xE000ED04
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Vector table offset register.
+ */
+#define OS_NVIC_VTOR                          0xE000ED08
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Application interrupt and reset control register
+ */
+#define OS_NVIC_AIRCR                         0xE000ED0C
+
+/* *
+ * @ingroup los_arch_interrupt
+ * System exception priority register.
+ */
+#define OS_NVIC_EXCPRI_BASE                   0xE000ED18
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 1 :reset.
+ */
+#define OS_EXC_RESET                          1
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 2 :Non-Maskable Interrupt.
+ */
+#define OS_EXC_NMI                            2
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 3 :(hard)fault.
+ */
+#define OS_EXC_HARD_FAULT                     3
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 4 :MemManage fault.
+ */
+#define OS_EXC_MPU_FAULT                      4
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 5 :Bus fault.
+ */
+#define OS_EXC_BUS_FAULT                      5
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 6 :Usage fault.
+ */
+#define OS_EXC_USAGE_FAULT                    6
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 11 :SVCall.
+ */
+#define OS_EXC_SVC_CALL                       11
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 12 :Debug monitor.
+ */
+#define OS_EXC_DBG_MONITOR                    12
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 14 :PendSV.
+ */
+#define OS_EXC_PEND_SV                        14
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 15 :SysTick.
+ */
+#define OS_EXC_SYS_TICK                       15
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_arch_interrupt
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_arch_interrupt
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Reset the vector table.
+ *
+ * @par Description:
+ * This API is used to reset the vector table.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID Reset_Handler(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Pended System Call.
+ *
+ * @par Description:
+ * PendSV can be pended and is useful for an OS to pend an exception
+ * so that an action can be performed after other important tasks are completed.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalPendSV(VOID);
+
+
+#define OS_EXC_IN_INIT                      0
+#define OS_EXC_IN_TASK                      1
+#define OS_EXC_IN_HWI                       2
+
+#define OS_EXC_MAX_BUF_LEN                  25
+#define OS_EXC_MAX_NEST_DEPTH               1
+
+#define OS_NVIC_SHCSR                       0xE000ED24
+#define OS_NVIC_CCR                         0xE000ED14
+
+#define OS_NVIC_INT_ENABLE_SIZE             0x20
+#define OS_NVIC_INT_PRI_SIZE                0xF0
+#define OS_NVIC_EXCPRI_SIZE                 0xC
+#define OS_NVIC_INT_CTRL_SIZE               4
+#define OS_NVIC_SHCSR_SIZE                  4
+
+#define OS_NVIC_INT_PEND_SIZE               OS_NVIC_INT_ACT_SIZE
+#define OS_NVIC_INT_ACT_SIZE                OS_NVIC_INT_ENABLE_SIZE
+
+#define OS_EXC_FLAG_NO_FLOAT                0x10000000
+#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
+#define OS_EXC_FLAG_IN_HWI                  0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
+
+#define OS_EXC_EVENT                        0x00000001
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
+ */
+typedef struct TagExcContext {
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    /* auto save */
+    UINT32 uwSP;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED) && (__FPU_USED== 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+
+VOID HalExcNMI(VOID);
+VOID HalExcHardFault(VOID);
+VOID HalExcMemFault(VOID);
+VOID HalExcBusFault(VOID);
+VOID HalExcUsageFault(VOID);
+VOID HalExcSvcCall(VOID);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was being pushed.
+ */
+#define OS_EXC_BF_STKERR           1
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was out of the stack.
+ */
+#define OS_EXC_BF_UNSTKERR         2
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register imprecise data access violation.
+ */
+#define OS_EXC_BF_IMPRECISERR      3
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register exact data access violation.
+ */
+#define OS_EXC_BF_PRECISERR        4
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register access violation while pointing.
+ */
+#define OS_EXC_BF_IBUSERR          5
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was being pushed.
+ */
+#define OS_EXC_MF_MSTKERR          6
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
+ */
+#define OS_EXC_MF_MUNSTKERR        7
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register data access violation.
+ */
+#define OS_EXC_MF_DACCVIOL         8
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register access violation.
+ */
+#define OS_EXC_MF_IACCVIOL         9
+
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
+ */
+#define OS_EXC_UF_DIVBYZERO        10
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error, error caused by unaligned access.
+ */
+#define OS_EXC_UF_UNALIGNED        11
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
+ */
+#define OS_EXC_UF_NOCP             12
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
+ */
+#define OS_EXC_UF_INVPC            13
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
+ */
+#define OS_EXC_UF_INVSTATE         14
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
+ */
+#define OS_EXC_UF_UNDEFINSTR       15
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: NMI
+ */
+
+#define OS_EXC_CAUSE_NMI           16
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: hard fault
+ */
+#define OS_EXC_CAUSE_HARDFAULT     17
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: The task handler exits.
+ */
+#define OS_EXC_CAUSE_TASK_EXIT     18
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A fatal error.
+ */
+#define OS_EXC_CAUSE_FATAL_ERR     19
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Hard Fault caused by a debug event.
+ */
+#define OS_EXC_CAUSE_DEBUGEVT      20
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
+ */
+#define OS_EXC_CAUSE_VECTBL        21
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M3 platform.
+ *
+ */
+typedef struct TagExcInfo {
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    UINT16 phase;
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
+    UINT16 type;
+    /**< If the exact address access error indicates the wrong access address when the exception occurred */
+    UINT32 faultAddr;
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    UINT32 thrdPid;
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
+    UINT16 nestCnt;
+    /**< reserve */
+    UINT16 reserved;
+    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+    EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_curNestCount;
+extern UINT32 g_intCount;
+extern UINT8 g_uwExcTbl[32];
+extern ExcInfo g_excInfo;
+
+#define MAX_INT_INFO_SIZE       (8 + 0x164)
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_INTERRUPT_H */

arch/arm/cortex-m3/keil/los_arch_timer.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */

arch/arm/cortex-m3/keil/los_atomic.S

@@ -0,0 +1,98 @@
+;
+; Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this list of
+;    conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice, this list
+;    of conditions and the following disclaimer in the documentation and/or other materials
+;    provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without specific prior written
+;    permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+        EXPORT  ArchAtomicRead
+        EXPORT  ArchAtomicSet
+        EXPORT  ArchAtomicAdd
+        EXPORT  ArchAtomicSub
+        EXPORT  ArchAtomicXchg32bits
+        EXPORT  ArchAtomicCmpXchg32bits
+
+    PRESERVE8
+    AREA  |.text|, CODE, READONLY
+    THUMB
+
+
+        EXPORT  ArchAtomicRead
+        EXPORT  ArchAtomicSet
+        EXPORT  ArchAtomicAdd
+        EXPORT  ArchAtomicSub
+        EXPORT  ArchAtomicXchg32bits
+        EXPORT  ArchAtomicCmpXchg32bits
+
+    PRESERVE8
+    AREA  |.text|, CODE, READONLY
+    THUMB
+
+ArchAtomicRead
+    ldrex r1, [r0]
+    mov r0, r1
+    bx lr
+
+ArchAtomicSet
+    ldrex r2, [r0]
+    strex r3, r1, [r0]
+    teq r3, #0
+    bne ArchAtomicSet
+    bx lr
+
+ArchAtomicAdd
+    ldrex r2, [r0]
+    add r2, r2, r1
+    strex r3, r2, [r0]
+    teq r3, #0
+    bne ArchAtomicAdd
+    mov r0, r2
+    bx lr
+
+ArchAtomicSub
+    ldrex r2, [r0]
+    sub r2, r2, r1
+    strex r3, r2, [r0]
+    teq r3, #0
+    bne ArchAtomicSub
+    mov r0, r2
+    bx lr
+
+ArchAtomicXchg32bits
+    ldrex r2, [r0]
+    strex r3, r1, [r0]
+    teq r3, #0
+    bne ArchAtomicXchg32bits
+    mov r0, r2
+
+ArchAtomicCmpXchg32bits
+    ldrex r3, [r0]
+    cmp r3, r2
+    bne end
+    strex r4, r1, [r0]
+    teq r4, #0
+    bne ArchAtomicCmpXchg32bits
+end

arch/arm/cortex-m3/keil/los_context.c

@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "ARMCM3.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
+
+/* ****************************************************************************
+ Function    : ArchInit
+ Description : arch init function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+    HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function    : ArchSysExit
+ Description : Task exit function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+    LOS_IntLock();
+    while (1) {
+    }
+}
+
+/* ****************************************************************************
+ Function    : ArchTskStackInit
+ Description : Task stack initialization function
+ Input       : taskID     --- TaskID
+               stackSize  --- Total size of the stack
+               topStack   --- Top of task's stack
+ Output      : None
+ Return      : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
+
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    context->S16 = 0xAA000010;
+    context->S17 = 0xAA000011;
+    context->S18 = 0xAA000012;
+    context->S19 = 0xAA000013;
+    context->S20 = 0xAA000014;
+    context->S21 = 0xAA000015;
+    context->S22 = 0xAA000016;
+    context->S23 = 0xAA000017;
+    context->S24 = 0xAA000018;
+    context->S25 = 0xAA000019;
+    context->S26 = 0xAA00001A;
+    context->S27 = 0xAA00001B;
+    context->S28 = 0xAA00001C;
+    context->S29 = 0xAA00001D;
+    context->S30 = 0xAA00001E;
+    context->S31 = 0xAA00001F;
+    context->S0 = 0xAA000000;
+    context->S1 = 0xAA000001;
+    context->S2 = 0xAA000002;
+    context->S3 = 0xAA000003;
+    context->S4 = 0xAA000004;
+    context->S5 = 0xAA000005;
+    context->S6 = 0xAA000006;
+    context->S7 = 0xAA000007;
+    context->S8 = 0xAA000008;
+    context->S9 = 0xAA000009;
+    context->S10 = 0xAA00000A;
+    context->S11 = 0xAA00000B;
+    context->S12 = 0xAA00000C;
+    context->S13 = 0xAA00000D;
+    context->S14 = 0xAA00000E;
+    context->S15 = 0xAA00000F;
+    context->FPSCR = 0x00000000;
+    context->NO_NAME = 0xAA000011;
+#endif
+
+    context->uwR4 = 0x04040404L;
+    context->uwR5 = 0x05050505L;
+    context->uwR6 = 0x06060606L;
+    context->uwR7 = 0x07070707L;
+    context->uwR8 = 0x08080808L;
+    context->uwR9 = 0x09090909L;
+    context->uwR10 = 0x10101010L;
+    context->uwR11 = 0x11111111L;
+    context->uwPriMask = 0;
+    context->uwR0 = taskID;
+    context->uwR1 = 0x01010101L;
+    context->uwR2 = 0x02020202L;
+    context->uwR3 = 0x03030303L;
+    context->uwR12 = 0x12121212L;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
+    context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
+    context->uwxPSR = 0x01000000L;
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+    return LOS_OK; /* never return */
+}

arch/arm/cortex-m3/keil/los_dispatch.S

@@ -1,162 +1,138 @@
-;
-; Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
-; Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without modification,
-; are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice, this list of
-;    conditions and the following disclaimer.
-;
-; 2. Redistributions in binary form must reproduce the above copyright notice, this list
-;    of conditions and the following disclaimer in the documentation and/or other materials
-;    provided with the distribution.
-;
-; 3. Neither the name of the copyright holder nor the names of its contributors may be used
-;    to endorse or promote products derived from this software without specific prior written
-;    permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
-; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-
-        PRESERVE8
-
-        EXPORT  LOS_IntLock
-        EXPORT  LOS_IntUnLock
-        EXPORT  LOS_IntRestore
-        EXPORT  LOS_StartToRun
-        EXPORT  osTaskSchedule
-        EXPORT  osPendSV
-
-        IMPORT  g_losTask
-        IMPORT  g_taskSwitchHook
-        IMPORT  g_taskScheduled
-
-OS_NVIC_INT_CTRL            EQU     0xE000ED04
-OS_NVIC_SYSPRI2             EQU     0xE000ED20
-OS_NVIC_PENDSV_PRI          EQU     0xF0F00000
-OS_NVIC_PENDSVSET           EQU     0x10000000
-OS_TASK_STATUS_RUNNING      EQU     0x0010
-
-    SECTION    .text:CODE(2)
-    THUMB
-    REQUIRE8
-
-LOS_StartToRun
-    LDR     R4, =OS_NVIC_SYSPRI2
-    LDR     R5, =OS_NVIC_PENDSV_PRI
-    STR     R5, [R4]
-
-    LDR     R0, =g_taskScheduled
-    MOV     R1, #1
-    STR     R1, [R0]
-
-    MOV     R0, #2
-    MSR     CONTROL, R0
-
-
-    LDR     R0, =g_losTask
-    LDR     R2, [R0, #4]
-    LDR     R0, =g_losTask
-    STR     R2, [R0]
-
-    LDR     R3, =g_losTask
-    LDR     R0, [R3]
-    LDRH    R7, [R0 , #4]
-    MOV     R8,  #OS_TASK_STATUS_RUNNING
-    ORR     R7,  R7,  R8
-    STRH    R7,  [R0 , #4]
-
-    LDR     R12, [R0]
-    ADD     R12, R12, #100
-
-    LDMFD   R12!, {R0-R7}
-    ADD     R12, R12, #72
-    MSR     PSP, R12
-    VPUSH   S0;
-    VPOP    S0;
-
-    MOV     LR, R5
-   ;MSR     xPSR, R7
-
-    CPSIE   I
-    BX      R6
-
-
-LOS_IntLock
-    MRS     R0, PRIMASK
-    CPSID   I
-    BX      LR
-
-LOS_IntUnLock
-    MRS     R0, PRIMASK
-    CPSIE   I
-    BX      LR
-
-LOS_IntRestore
-    MSR     PRIMASK, R0
-    BX      LR
-
-osTaskSchedule
-    LDR     R0, =OS_NVIC_INT_CTRL
-    LDR     R1, =OS_NVIC_PENDSVSET
-    STR     R1, [R0]
-    BX      LR
-
-osPendSV
-    MRS     R12, PRIMASK
-    CPSID   I
-
-    LDR     R2, =g_taskSwitchHook
-    LDR     R2, [R2]
-    CBZ     R2, TaskSwitch
-    PUSH    {R12, LR}
-    BLX     R2
-    POP     {R12, LR}
-
-TaskSwitch
-    MRS     R0, PSP
-
-    STMFD   R0!, {R4-R12}
-    VSTMDB  R0!, {D8-D15}
-
-    LDR     R5, =g_losTask
-    LDR     R6, [R5]
-    STR     R0, [R6]
-
-
-    LDRH    R7, [R6 , #4]
-    MOV     R8,#OS_TASK_STATUS_RUNNING
-    BIC     R7, R7, R8
-    STRH    R7, [R6 , #4]
-
-
-    LDR     R0, =g_losTask
-    LDR     R0, [R0, #4]
-    STR     R0, [R5]
-
-
-    LDRH    R7, [R0 , #4]
-    MOV     R8,  #OS_TASK_STATUS_RUNNING
-    ORR     R7, R7, R8
-    STRH    R7,  [R0 , #4]
-
-    LDR     R1,   [R0]
-    VLDMIA  R1!, {D8-D15}
-    LDMFD   R1!, {R4-R12}
-    MSR     PSP,  R1
-
-    MSR     PRIMASK, R12
-    BX      LR
-
-    END
+;
+; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this list of
+;    conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice, this list
+;    of conditions and the following disclaimer in the documentation and/or other materials
+;    provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without specific prior written
+;    permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+        PRESERVE8
+
+        EXPORT  ArchIntLock
+        EXPORT  ArchIntUnLock
+        EXPORT  ArchIntRestore
+        EXPORT  HalStartToRun
+        EXPORT  ArchTaskSchedule
+        EXPORT  HalPendSV
+        IMPORT  OsSchedTaskSwitch
+        IMPORT  g_losTask
+
+OS_NVIC_INT_CTRL            EQU     0xE000ED04
+OS_NVIC_SYSPRI2             EQU     0xE000ED20
+OS_NVIC_PENDSV_PRI          EQU     0xF0F00000
+OS_NVIC_PENDSVSET           EQU     0x10000000
+OS_TASK_STATUS_RUNNING      EQU     0x0010
+
+    AREA  |.text|, CODE, READONLY
+    THUMB
+    REQUIRE8
+
+HalStartToRun
+    LDR     R4, =OS_NVIC_SYSPRI2
+    LDR     R5, =OS_NVIC_PENDSV_PRI
+    STR     R5, [R4]
+
+    MOV     R0, #2
+    MSR     CONTROL, R0
+
+    LDR     R1, =g_losTask
+    LDR     R0, [R1, #4]
+    LDR     R12, [R0]
+    ;ADD     R12, R12, #100
+    ADD     R12, R12, #36
+
+    LDMFD   R12!, {R0-R7}
+    ;ADD     R12, R12, #72
+    MSR     PSP, R12
+    ;VPUSH   S0;
+    ;VPOP    S0;
+
+    MOV     LR, R5
+   ;MSR     xPSR, R7
+
+    CPSIE   I
+    BX      R6
+
+
+ArchIntLock
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+ArchIntUnLock
+    MRS     R0, PRIMASK
+    CPSIE   I
+    BX      LR
+
+ArchIntRestore
+    MSR     PRIMASK, R0
+    BX      LR
+
+ArchTaskSchedule
+    LDR     R0, =OS_NVIC_INT_CTRL
+    LDR     R1, =OS_NVIC_PENDSVSET
+    STR     R1, [R0]
+    DSB
+    ISB
+    BX      LR
+
+HalPendSV
+    MRS     R12, PRIMASK
+    CPSID   I
+
+HalTaskSwitch
+    PUSH    {R12, LR}
+    BL      OsSchedTaskSwitch
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R0, LR
+    BNE     TaskContextSwitch
+    MSR     PRIMASK, R12
+    BX      LR
+
+TaskContextSwitch
+    MOV     LR, R0
+    MRS     R0, PSP
+
+    STMFD   R0!, {R4-R12}
+    ;VSTMDB  R0!, {D8-D15}
+
+    LDR     R5, =g_losTask
+    LDR     R6, [R5]
+    STR     R0, [R6]
+
+    LDR     R0, [R5, #4]
+    STR     R0, [R5]
+
+    LDR     R1,   [R0]
+    ;VLDMIA  R1!, {D8-D15}
+    LDMFD   R1!, {R4-R12}
+    MSR     PSP,  R1
+
+    MSR     PRIMASK, R12
+    BX      LR
+
+    END

arch/arm/cortex-m3/keil/los_exc.S

@@ -0,0 +1,285 @@
+;
+; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this list of
+;    conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice, this list
+;    of conditions and the following disclaimer in the documentation and/or other materials
+;    provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without specific prior written
+;    permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+    PRESERVE8
+    AREA  |.text|, CODE, READONLY
+    THUMB
+
+    EXPORT  HalExcNMI
+    EXPORT  HalExcHardFault
+    EXPORT  HalExcMemFault
+    EXPORT  HalExcBusFault
+    EXPORT  HalExcUsageFault
+    EXPORT  HalExcSvcCall
+
+    IMPORT HalExcHandleEntry
+    IMPORT g_uwExcTbl
+    IMPORT g_taskScheduled
+
+OS_FLG_BGD_ACTIVE   EQU   0x0002
+
+OS_EXC_CAUSE_NMI            EQU   16
+OS_EXC_CAUSE_HARDFAULT      EQU   17
+
+HF_DEBUGEVT     EQU   20
+HF_VECTBL       EQU   21
+
+FLAG_ADDR_VALID             EQU   0x10000
+FLAG_HWI_ACTIVE             EQU   0x20000
+FLAG_NO_FLOAT               EQU   0x10000000
+
+OS_NVIC_FSR                 EQU   0xE000ED28      ;include BusFault/MemFault/UsageFault State Register
+OS_NVIC_HFSR                EQU   0xE000ED2C      ;HardFault State Register
+OS_NVIC_BFAR                EQU   0xE000ED38
+OS_NVIC_MMAR                EQU   0xE000ED34
+OS_NVIC_ACT_BASE            EQU   0xE000E300
+OS_NVIC_SHCSRS              EQU   0xE000ED24
+OS_NVIC_SHCSR_MASK          EQU   0xC00
+
+HalExcNMI
+    MOV  R0, #OS_EXC_CAUSE_NMI
+    MOV  R1, #0
+    B  osExcDispatch
+
+HalExcHardFault
+    MOV  R0, #OS_EXC_CAUSE_HARDFAULT
+    LDR  R2, =OS_NVIC_HFSR
+    LDR  R2, [R2]
+
+    MOV  R1, #HF_DEBUGEVT
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x80000000
+    BNE  osExcDispatch     ; DEBUGEVT
+
+    AND  R0, R0 , #0x000000FF
+    MOV  R1, #HF_VECTBL
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x00000002
+    BNE  osExcDispatch     ; VECTBL
+
+    ;if not DEBUGEVT and VECTBL then is FORCED
+    AND  R0, R0, #0x000000FF
+
+    LDR  R2, =OS_NVIC_FSR
+    LDR  R2, [R2]
+
+    TST  R2, #0x8000     ; BFARVALID
+    BNE  _HFBusFault     ; BusFault
+
+    TST  R2, #0x80       ; MMARVALID
+    BNE  _HFMemFault     ; MemFault
+
+    MOV  R12,#0
+    B    osHFExcCommonBMU
+
+_HFBusFault
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    B    osHFExcCommonBMU
+
+_HFMemFault
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+
+osHFExcCommonBMU
+    CLZ  R2, R2
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R2
+    LDRB R2, [R3]
+    ORR  R0, R0, R2, LSL #0x8
+    ORR  R0, R0 ,R12
+    B    osExcDispatch
+
+HalExcSvcCall
+    TST   LR, #0x4
+    ITE   EQ
+    MRSEQ R0, MSP
+    MRSNE R0, PSP
+    LDR   R1, [R0,#24]
+    LDRB  R0, [R1,#-2]
+    MOV   R1, #0
+    B     osExcDispatch
+
+HalExcBusFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x8000 ; BFARVALID
+    BEQ  _ExcBusNoADDR
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1F00
+
+    B    osExcCommonBMU
+
+_ExcBusNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcMemFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x80 ; MMARVALID
+    BEQ  _ExcMemNoADDR
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1B
+
+    B    osExcCommonBMU
+
+_ExcMemNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcUsageFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    MOV  R1, #0x030F
+    LSL  R1, R1, #16
+    AND  R0, R0, R1
+    MOV  R12, #0
+
+osExcCommonBMU
+    CLZ  R0, R0
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R0
+    LDRB R0, [R3]
+    ORR  R0, R0, R12
+
+; R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid),  R1 -- EXCADDR
+osExcDispatch
+    LDR   R2, =OS_NVIC_ACT_BASE
+    MOV   R12, #8                       ; R12 is hwi check loop counter
+
+_hwiActiveCheck
+    LDR   R3, [R2]                      ; R3 store active hwi register when exc
+    CMP   R3, #0
+    BEQ   _hwiActiveCheckNext
+
+    ; exc occured in IRQ
+    ORR   R0, R0, #FLAG_HWI_ACTIVE
+    RBIT  R2, R3
+    CLZ   R2, R2
+    AND   R12, R12, #1
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as pid
+
+_ExcInMSP
+    CMP   LR, #0xFFFFFFE9
+    BNE   _NoFloatInMsp
+    ADD   R3, R13, #104
+    PUSH  {R3}
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    ;VPUSH {D8-D15}
+    B     _handleEntry
+
+_NoFloatInMsp
+    ADD   R3, R13, #32
+    PUSH  {R3} ; save IRQ SP            ; store message-->exc: MSP(R13)
+
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+    B     _handleEntry
+
+_hwiActiveCheckNext
+    ADD   R2, R2, #4                        ; next NVIC ACT ADDR
+    SUBS  R12, R12, #1
+    BNE   _hwiActiveCheck
+
+    ;/*NMI interrupt excption*/
+    LDR   R2, =OS_NVIC_SHCSRS
+    LDRH  R2,[R2]
+    LDR   R3,=OS_NVIC_SHCSR_MASK
+    AND   R2, R2,R3
+    CMP   R2,#0
+    BNE   _ExcInMSP
+    ; exc occured in Task or Init or exc
+    ; reserved for register info from task stack
+
+    LDR  R2, =g_taskScheduled
+    LDR  R2, [R2]
+    TST  R2, #1         ; OS_FLG_BGD_ACTIVE
+    BEQ  _ExcInMSP                      ; if exc occured in Init then branch
+
+
+    CMP   LR, #0xFFFFFFED               ;auto push floating registers
+    BNE   _NoFloatInPsp
+
+    ; exc occured in Task
+    MOV   R2,  R13
+    SUB   R13, #96                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #104
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+    ;VPUSH {D8-D15}
+
+    ; copy auto saved task register
+
+    LDMFD R3!, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    ;VLDMIA  R3!, {D8-D15}
+    ;VSTMDB  R2!, {D8-D15}
+    STMFD R2!, {R4-R11}
+    B     _handleEntry
+
+_NoFloatInPsp
+    MOV   R2,  R13                           ;no auto push floating registers
+    SUB   R13, #32                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #32
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+
+    LDMFD R3, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    STMFD R2!, {R4-R11}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+
+_handleEntry
+    MOV R3, R13                         ; R13:the 4th param
+    CPSID I
+    CPSID F
+    B  HalExcHandleEntry
+
+    NOP
+    END

arch/arm/cortex-m3/keil/los_interrupt.c

@@ -0,0 +1,615 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "los_interrupt.h"
+#include <stdarg.h>
+#include "securec.h"
+#include "los_context.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+
+/*lint -save -e40 -e522 -e533*/
+UINT32 g_intCount = 0;
+
+/*lint -restore*/
+#ifdef __ICCARM__
+#pragma location = ".data.vector"
+#elif defined(__CC_ARM) || defined(__GNUC__)
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
+LITE_OS_SEC_VEC
+#endif
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+    HWI_PROC_FUNC pfnHandler;
+    VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+    }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+    }
+}
+#endif
+
+WEAK VOID SysTick_Handler(VOID)
+{
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HwiNumGet
+ Description : Get an interrupt number
+ Input       : None
+ Output      : None
+ Return      : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+    return __get_IPSR();
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+    return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function    : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+/*lint -e529*/
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+    while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+    UINT32 hwiIndex;
+    UINT32 intSave;
+
+#if (LOSCFG_KERNEL_RUNSTOP == 1)
+    SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
+#endif
+
+    intSave = LOS_IntLock();
+    g_intCount++;
+    LOS_IntRestore(intSave);
+
+    hwiIndex = HwiNumGet();
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+
+    HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+        g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+    }
+#else
+    if (g_hwiHandlerForm[hwiIndex] != 0) {
+        g_hwiHandlerForm[hwiIndex]();
+    }
+#endif
+
+    HalAftInterruptHandler(hwiIndex);
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+    intSave = LOS_IntLock();
+    g_intCount--;
+    LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiCreate
+ Description : create hardware interrupt
+ Input       : hwiNum   --- hwi num to create
+               hwiPrio  --- priority of the hwi
+               hwiMode  --- unused
+               hwiHandler --- hwi handler
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T hwiMode,
+                                           HWI_PROC_FUNC hwiHandler,
+                                           HwiIrqParam *irqParam)
+{
+    (VOID)hwiMode;
+    UINT32 intSave;
+
+    if (hwiHandler == NULL) {
+        return OS_ERRNO_HWI_PROC_FUNC_NULL;
+    }
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return OS_ERRNO_HWI_ALREADY_CREATED;
+    }
+
+    if (hwiPrio > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (irqParam != NULL) {
+        OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+    } else {
+        OsSetVector(hwiNum, hwiHandler, NULL);
+    }
+#else
+    (VOID)irqParam;
+    OsSetVector(hwiNum, hwiHandler);
+#endif
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input       : hwiNum   --- hwi num to delete
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+    (VOID)irqParam;
+    UINT32 intSave;
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    HwiMask((IRQn_Type)hwiNum);
+
+    intSave = LOS_IntLock();
+
+    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+#define FAULT_STATUS_REG_BIT            32
+#define USGFAULT                        (1 << 18)
+#define BUSFAULT                        (1 << 17)
+#define MEMFAULT                        (1 << 16)
+#define DIV0FAULT                       (1 << 4)
+#define UNALIGNFAULT                    (1 << 3)
+#define HARDFAULT_IRQN                  (-13)
+
+ExcInfo g_excInfo = {0};
+
+UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
+    0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
+    0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
+    0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
+    0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
+};
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcNvicDump(VOID)
+{
+#define OS_NR_NVIC_EXC_DUMP_TYPES   7
+    UINT32 *base = NULL;
+    UINT32 len, i, j;
+    UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
+        OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
+    };
+    UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
+        OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
+        OS_NVIC_INT_CTRL_SIZE
+    };
+    CHAR strRgEnable[] = "enable";
+    CHAR strRgPending[] = "pending";
+    CHAR strRgActive[] = "active";
+    CHAR strRgPriority[] = "priority";
+    CHAR strRgException[] = "exception";
+    CHAR strRgShcsr[] = "shcsr";
+    CHAR strRgIntCtrl[] = "control";
+    CHAR *strRgs[] = {
+        strRgEnable, strRgPending, strRgActive, strRgPriority,
+        strRgException, strRgShcsr, strRgIntCtrl
+    };
+
+    PRINTK("\r\nOS exception NVIC dump:\n");
+    for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
+        base = (UINT32 *)rgNvicBases[i];
+        len = rgNvicLens[i];
+        PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
+        len = (len >> 2); /* 2: Gets the next register offset */
+        for (j = 0; j < len; j++) {
+            PRINTK("0x%x ", *(base + j));
+            if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
+                PRINTK("\n");
+            }
+        }
+        PRINTK("\n");
+    }
+}
+
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+    CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+    PRINTK("Type      = %d\n", excInfo->type);
+    PRINTK("ThrdPid   = %d\n", excInfo->thrdPid);
+    PRINTK("Phase     = %s\n", phaseStr[excInfo->phase]);
+    PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Current task info:\n");
+    if (excInfo->phase == OS_EXC_IN_TASK) {
+        LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+        PRINTK("Task name = %s\n", taskCB->taskName);
+        PRINTK("Task ID   = %d\n", taskCB->taskID);
+        PRINTK("Task SP   = %p\n", taskCB->stackPointer);
+        PRINTK("Task ST   = 0x%x\n", taskCB->topOfStack);
+        PRINTK("Task SS   = 0x%x\n", taskCB->stackSize);
+    } else if (excInfo->phase == OS_EXC_IN_HWI) {
+        PRINTK("Exception occur in interrupt phase!\n");
+    } else {
+        PRINTK("Exception occur in system init phase!\n");
+    }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Exception reg dump:\n");
+    PRINTK("PC        = 0x%x\n", excInfo->context->uwPC);
+    PRINTK("LR        = 0x%x\n", excInfo->context->uwLR);
+    PRINTK("SP        = 0x%x\n", excInfo->context->uwSP);
+    PRINTK("R0        = 0x%x\n", excInfo->context->uwR0);
+    PRINTK("R1        = 0x%x\n", excInfo->context->uwR1);
+    PRINTK("R2        = 0x%x\n", excInfo->context->uwR2);
+    PRINTK("R3        = 0x%x\n", excInfo->context->uwR3);
+    PRINTK("R4        = 0x%x\n", excInfo->context->uwR4);
+    PRINTK("R5        = 0x%x\n", excInfo->context->uwR5);
+    PRINTK("R6        = 0x%x\n", excInfo->context->uwR6);
+    PRINTK("R7        = 0x%x\n", excInfo->context->uwR7);
+    PRINTK("R8        = 0x%x\n", excInfo->context->uwR8);
+    PRINTK("R9        = 0x%x\n", excInfo->context->uwR9);
+    PRINTK("R10       = 0x%x\n", excInfo->context->uwR10);
+    PRINTK("R11       = 0x%x\n", excInfo->context->uwR11);
+    PRINTK("R12       = 0x%x\n", excInfo->context->uwR12);
+    PRINTK("PriMask   = 0x%x\n", excInfo->context->uwPriMask);
+    PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+    UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+    UINT32 index;
+
+    OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
+
+    PRINTK("----- backtrace start -----\n");
+    for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+        if (LR[index] == 0) {
+            break;
+        }
+        PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
+    }
+    PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+    PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+    MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+    UINT32 errCnt;
+    UINT32 i;
+
+    (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+    errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+    if (errCnt < OS_SYS_MEM_NUM) {
+        errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+    }
+
+    if (errCnt == 0) {
+        PRINTK("all memory pool check passed!\n");
+        return;
+    }
+
+    for (i = 0; i < errCnt; i++) {
+        PRINTK("pool num    = %d\n", i);
+        PRINTK("pool type   = %d\n", memExcInfo[i].type);
+        PRINTK("pool addr   = 0x%x\n", memExcInfo[i].startAddr);
+        PRINTK("pool size   = 0x%x\n", memExcInfo[i].size);
+        PRINTK("pool free   = 0x%x\n", memExcInfo[i].free);
+        PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
+        PRINTK("pool error node addr  = 0x%x\n", memExcInfo[i].errorAddr);
+        PRINTK("pool error node len   = 0x%x\n", memExcInfo[i].errorLen);
+        PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
+    }
+#endif
+    UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+    if (ret == LOS_OK) {
+        PRINTK("system heap memcheck over, all passed!\n");
+    }
+
+    PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+    PRINTK("*************Exception Information**************\n");
+    OsExcTypeInfo(excInfo);
+    OsExcCurTaskInfo(excInfo);
+    OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+    OsExcBackTraceInfo(excInfo);
+#endif
+    OsGetAllTskInfo();
+    OsExcNvicDump();
+    OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+    UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
+    g_intCount++;
+    g_excInfo.nestCnt++;
+
+    g_excInfo.type = excType & OS_NULL_SHORT;
+
+    if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
+        g_excInfo.faultAddr = faultAddr;
+    } else {
+        g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+    }
+    if (g_losTask.runTask != NULL) {
+        if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
+            g_excInfo.phase = OS_EXC_IN_HWI;
+            g_excInfo.thrdPid = pid;
+        } else {
+            g_excInfo.phase = OS_EXC_IN_TASK;
+            g_excInfo.thrdPid = g_losTask.runTask->taskID;
+        }
+    } else {
+        g_excInfo.phase = OS_EXC_IN_INIT;
+        g_excInfo.thrdPid = OS_NULL_INT;
+    }
+    if (excType & OS_EXC_FLAG_NO_FLOAT) {
+        g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
+    } else {
+        g_excInfo.context = excBufAddr;
+    }
+
+    OsDoExcHook(EXC_INTERRUPT);
+    OsExcInfoDisplay(&g_excInfo);
+    ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function    : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    UINT32 index;
+    g_hwiForm[0] = 0;             /* [0] Top of Stack */
+    g_hwiForm[1] = Reset_Handler; /* [1] reset */
+    for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
+        g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+    }
+    /* Exception handler register */
+    g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT]   = HalExcNMI;
+    g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT]        = HalExcHardFault;
+    g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = HalExcMemFault;
+    g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT]         = HalExcBusFault;
+    g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT]       = HalExcUsageFault;
+    g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT]           = HalExcSvcCall;
+    g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT]           = HalPendSV;
+    g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT]          = SysTick_Handler;
+
+    /* Interrupt vector table location */
+    SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
+#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
+    NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
+#endif
+
+    /* Enable USGFAULT, BUSFAULT, MEMFAULT */
+    *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+	
+    /* Enable DIV 0 and unaligned exception */
+#ifdef LOSCFG_ARCH_UNALIGNED_EXC
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
+#else
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
+#endif
+
+    return;
+}
+

arch/arm/cortex-m3/keil/los_startup.s

@@ -1,62 +1,66 @@
-;
-; Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
-; Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without modification,
-; are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice, this list of
-;    conditions and the following disclaimer.
-;
-; 2. Redistributions in binary form must reproduce the above copyright notice, this list
-;    of conditions and the following disclaimer in the documentation and/or other materials
-;    provided with the distribution.
-;
-; 3. Neither the name of the copyright holder nor the names of its contributors may be used
-;    to endorse or promote products derived from this software without specific prior written
-;    permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
-; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-
-    PRESERVE8
-
-    AREA    RESET, CODE, READONLY
-    THUMB
-
-    IMPORT  ||Image$$ARM_LIB_STACKHEAP$$ZI$$Limit||
-    IMPORT  PendSV_Handler
-
-    EXPORT  _BootVectors
-    EXPORT  osResetVector
-
-_BootVectors
-    DCD     ||Image$$ARM_LIB_STACKHEAP$$ZI$$Limit||
-    DCD     osResetVector
-
-
-osResetVector
-    CPSID   I
-
-	IMPORT LOS_HardBootInit
-    LDR     R0, =LOS_HardBootInit
-    BLX      R0
-	
-    IMPORT  __main
-    LDR     R0, =__main
-    BX      R0
-
-
-    ALIGN
-    END
-
+;
+; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this list of
+;    conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice, this list
+;    of conditions and the following disclaimer in the documentation and/or other materials
+;    provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without specific prior written
+;    permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*----------------------------------------------------------------------------
+;*      Name:    LOS_VENDOR.S
+;*      Purpose: Thread scheduler
+;*      Rev.:    V1.0.0
+;*----------------------------------------------------------------------------
+
+
+        PRESERVE8
+
+    AREA    RESET, CODE, READONLY
+    THUMB
+
+    IMPORT  ||Image$$ARM_LIB_STACKHEAP$$ZI$$Limit||
+    IMPORT  HalHwiDefaultHandler
+
+    EXPORT  _BootVectors
+    EXPORT  Reset_Handler
+
+_BootVectors
+    DCD     ||Image$$ARM_LIB_STACKHEAP$$ZI$$Limit||
+    DCD     Reset_Handler
+    DCD     HalHwiDefaultHandler
+    DCD     HalHwiDefaultHandler
+
+
+Reset_Handler
+    CPSID   I
+
+    IMPORT  LOS_HardBootInit
+    BL      LOS_HardBootInit
+    IMPORT  __main
+    LDR     R0, =__main
+    BX      R0
+
+    ALIGN
+    END

arch/arm/cortex-m3/keil/los_timer.c

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "ARMCM3.h"
+#include "los_tick.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+    UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
+
+    tick->freq = OS_SYS_CLOCK;
+
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
+#else
+    OsSetVector(tick->irqNum, handler);
+#endif
+#endif
+
+    ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
+    if (ret == 1) {
+        return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
+    }
+
+    return LOS_OK;
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+    if (nextResponseTime > g_archTickTimer.periodMax) {
+        nextResponseTime = g_archTickTimer.periodMax;
+    }
+
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
+    SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+
+    return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+    UINT32 hwCycle = 0;
+    UINT32 intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
+    *period = SysTick->LOAD;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
+    LOS_IntRestore(intSave);
+    return (UINT64)hwCycle;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return LOS_OK;
+}

arch/arm/cortex-m33/gcc/BUILD.gn

@@ -0,0 +1,38 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_group("gcc") {
+  if (defined(LOSCFG_SECURE_TRUSTZONE)) {
+    modules = [ "TZ" ]
+  } else {
+    modules = [ "NTZ" ]
+  }
+}

arch/arm/cortex-m33/gcc/NTZ/BUILD.gn

@@ -0,0 +1,46 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_name = "arch"
+kernel_module(module_name) {
+  sources = [
+    "los_context.c",
+    "los_dispatch.S",
+    "los_exc.S",
+    "los_interrupt.c",
+    "los_timer.c",
+  ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
+}
+
+config("public") {
+  include_dirs = [ "." ]
+}

arch/arm/cortex-m33/gcc/NTZ/los_arch_atomic.h

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    __asm__ __volatile__("ldrex %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%1]\n"
+                             "strex %0, %2, [%1]\n"
+                             : "=&r"(status)
+                             : "r"(v), "r"(setVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "add %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "sub %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%3]\n"
+                             "strex %1, %4, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("ldrex %0, %2\n"
+                             "mov %1, #0\n"
+                             "cmp %0, %3\n"
+                             "bne 1f\n"
+                             "strex %1, %4, %2\n"
+                             "1:"
+                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
+                             : "r"(oldVal), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/arm/cortex-m33/gcc/NTZ/los_arch_context.h

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct TagTskContext {
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} TaskContext;
+
+/**
+ * @ingroup  los_config
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */

arch/arm/cortex-m33/gcc/NTZ/los_arch_interrupt.h

@@ -0,0 +1,683 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_INTERRUPT_H
+#define _LOS_ARCH_INTERRUPT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST                   0
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST                    7
+#endif
+
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of M-Core system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT                     16
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of M-Core interrupt vector.
+ */
+#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * AIRCR register priority group parameter .
+ */
+#define OS_NVIC_AIRCR_PRIGROUP                7
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Boot interrupt vector table.
+ */
+extern UINT32 _BootVectors[];
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * SysTick control and status register.
+ */
+#define OS_SYSTICK_CONTROL_REG                0xE000E010
+
+/* *
+ * @ingroup los_hw
+ * SysTick current value register.
+ */
+#define OS_SYSTICK_CURRENT_REG                0xE000E018
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt Priority-Level Registers.
+ */
+#define OS_NVIC_PRI_BASE                      0xE000E400
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt enable register for 0-31.
+ */
+#define OS_NVIC_SETENA_BASE                   0xE000E100
+
+/* *
+ * @ingroup los_arch_interrupt
+ * interrupt pending register.
+ */
+#define OS_NVIC_SETPEND_BASE                  0xE000E200
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt active register.
+ */
+#define OS_NVIC_INT_ACT_BASE                  0xE000E300
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt disable register for 0-31.
+ */
+#define OS_NVIC_CLRENA_BASE                   0xE000E180
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt control and status register.
+ */
+#define OS_NVIC_INT_CTRL                      0xE000ED04
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Vector table offset register.
+ */
+#define OS_NVIC_VTOR                          0xE000ED08
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Application interrupt and reset control register
+ */
+#define OS_NVIC_AIRCR                         0xE000ED0C
+
+/* *
+ * @ingroup los_arch_interrupt
+ * System exception priority register.
+ */
+#define OS_NVIC_EXCPRI_BASE                   0xE000ED18
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 1 :reset.
+ */
+#define OS_EXC_RESET                          1
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 2 :Non-Maskable Interrupt.
+ */
+#define OS_EXC_NMI                            2
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 3 :(hard)fault.
+ */
+#define OS_EXC_HARD_FAULT                     3
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 4 :MemManage fault.
+ */
+#define OS_EXC_MPU_FAULT                      4
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 5 :Bus fault.
+ */
+#define OS_EXC_BUS_FAULT                      5
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 6 :Usage fault.
+ */
+#define OS_EXC_USAGE_FAULT                    6
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 11 :SVCall.
+ */
+#define OS_EXC_SVC_CALL                       11
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 12 :Debug monitor.
+ */
+#define OS_EXC_DBG_MONITOR                    12
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 14 :PendSV.
+ */
+#define OS_EXC_PEND_SV                        14
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 15 :SysTick.
+ */
+#define OS_EXC_SYS_TICK                       15
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_arch_interrupt
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_arch_interrupt
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Reset the vector table.
+ *
+ * @par Description:
+ * This API is used to reset the vector table.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID Reset_Handler(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Pended System Call.
+ *
+ * @par Description:
+ * PendSV can be pended and is useful for an OS to pend an exception
+ * so that an action can be performed after other important tasks are completed.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalPendSV(VOID);
+
+
+#define OS_EXC_IN_INIT                      0
+#define OS_EXC_IN_TASK                      1
+#define OS_EXC_IN_HWI                       2
+
+#define OS_EXC_MAX_BUF_LEN                  25
+#define OS_EXC_MAX_NEST_DEPTH               1
+
+#define OS_NVIC_SHCSR                       0xE000ED24
+#define OS_NVIC_CCR                         0xE000ED14
+
+#define OS_NVIC_INT_ENABLE_SIZE             0x20
+#define OS_NVIC_INT_PRI_SIZE                0xF0
+#define OS_NVIC_EXCPRI_SIZE                 0xC
+#define OS_NVIC_INT_CTRL_SIZE               4
+#define OS_NVIC_SHCSR_SIZE                  4
+
+#define OS_NVIC_INT_PEND_SIZE               OS_NVIC_INT_ACT_SIZE
+#define OS_NVIC_INT_ACT_SIZE                OS_NVIC_INT_ENABLE_SIZE
+
+#define OS_EXC_FLAG_NO_FLOAT                0x10000000
+#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
+#define OS_EXC_FLAG_IN_HWI                  0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
+
+#define OS_EXC_EVENT                        0x00000001
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
+ */
+typedef struct TagExcContext {
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    /* auto save */
+    UINT32 uwSP;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED) && (__FPU_USED== 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+
+VOID HalExcNMI(VOID);
+VOID HalExcHardFault(VOID);
+VOID HalExcMemFault(VOID);
+VOID HalExcBusFault(VOID);
+VOID HalExcUsageFault(VOID);
+VOID HalSVCHandler(VOID);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was being pushed.
+ */
+#define OS_EXC_BF_STKERR           1
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was out of the stack.
+ */
+#define OS_EXC_BF_UNSTKERR         2
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register imprecise data access violation.
+ */
+#define OS_EXC_BF_IMPRECISERR      3
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register exact data access violation.
+ */
+#define OS_EXC_BF_PRECISERR        4
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register access violation while pointing.
+ */
+#define OS_EXC_BF_IBUSERR          5
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was being pushed.
+ */
+#define OS_EXC_MF_MSTKERR          6
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
+ */
+#define OS_EXC_MF_MUNSTKERR        7
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register data access violation.
+ */
+#define OS_EXC_MF_DACCVIOL         8
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register access violation.
+ */
+#define OS_EXC_MF_IACCVIOL         9
+
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
+ */
+#define OS_EXC_UF_DIVBYZERO        10
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error, error caused by unaligned access.
+ */
+#define OS_EXC_UF_UNALIGNED        11
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
+ */
+#define OS_EXC_UF_NOCP             12
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
+ */
+#define OS_EXC_UF_INVPC            13
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
+ */
+#define OS_EXC_UF_INVSTATE         14
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
+ */
+#define OS_EXC_UF_UNDEFINSTR       15
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: NMI
+ */
+
+#define OS_EXC_CAUSE_NMI           16
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: hard fault
+ */
+#define OS_EXC_CAUSE_HARDFAULT     17
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: The task handler exits.
+ */
+#define OS_EXC_CAUSE_TASK_EXIT     18
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A fatal error.
+ */
+#define OS_EXC_CAUSE_FATAL_ERR     19
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Hard Fault caused by a debug event.
+ */
+#define OS_EXC_CAUSE_DEBUGEVT      20
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
+ */
+#define OS_EXC_CAUSE_VECTBL        21
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M33 platform.
+ *
+ */
+typedef struct TagExcInfo {
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    UINT16 phase;
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
+    UINT16 type;
+    /**< If the exact address access error indicates the wrong access address when the exception occurred */
+    UINT32 faultAddr;
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    UINT32 thrdPid;
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
+    UINT16 nestCnt;
+    /**< reserve */
+    UINT16 reserved;
+    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+    EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_curNestCount;
+extern UINT32 g_intCount;
+extern UINT8 g_uwExcTbl[32];
+extern ExcInfo g_excInfo;
+
+#define MAX_INT_INFO_SIZE       (8 + 0x164)
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_INTERRUPT_H */

arch/arm/cortex-m33/gcc/NTZ/los_arch_timer.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */

arch/arm/cortex-m33/gcc/NTZ/los_context.c

@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
+
+/* ****************************************************************************
+ Function    : ArchInit
+ Description : arch init function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+    HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function    : ArchSysExit
+ Description : Task exit function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+    LOS_IntLock();
+    while (1) {
+    }
+}
+
+/* ****************************************************************************
+ Function    : ArchTskStackInit
+ Description : Task stack initialization function
+ Input       : taskID     --- TaskID
+               stackSize  --- Total size of the stack
+               topStack   --- Top of task's stack
+ Output      : None
+ Return      : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
+
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    context->S16 = 0xAA000010;
+    context->S17 = 0xAA000011;
+    context->S18 = 0xAA000012;
+    context->S19 = 0xAA000013;
+    context->S20 = 0xAA000014;
+    context->S21 = 0xAA000015;
+    context->S22 = 0xAA000016;
+    context->S23 = 0xAA000017;
+    context->S24 = 0xAA000018;
+    context->S25 = 0xAA000019;
+    context->S26 = 0xAA00001A;
+    context->S27 = 0xAA00001B;
+    context->S28 = 0xAA00001C;
+    context->S29 = 0xAA00001D;
+    context->S30 = 0xAA00001E;
+    context->S31 = 0xAA00001F;
+    context->S0 = 0xAA000000;
+    context->S1 = 0xAA000001;
+    context->S2 = 0xAA000002;
+    context->S3 = 0xAA000003;
+    context->S4 = 0xAA000004;
+    context->S5 = 0xAA000005;
+    context->S6 = 0xAA000006;
+    context->S7 = 0xAA000007;
+    context->S8 = 0xAA000008;
+    context->S9 = 0xAA000009;
+    context->S10 = 0xAA00000A;
+    context->S11 = 0xAA00000B;
+    context->S12 = 0xAA00000C;
+    context->S13 = 0xAA00000D;
+    context->S14 = 0xAA00000E;
+    context->S15 = 0xAA00000F;
+    context->FPSCR = 0x00000000;
+    context->NO_NAME = 0xAA000011;
+#endif
+
+    context->uwR4 = 0x04040404L;
+    context->uwR5 = 0x05050505L;
+    context->uwR6 = 0x06060606L;
+    context->uwR7 = 0x07070707L;
+    context->uwR8 = 0x08080808L;
+    context->uwR9 = 0x09090909L;
+    context->uwR10 = 0x10101010L;
+    context->uwR11 = 0x11111111L;
+    context->uwPriMask = 0;
+    context->uwR0 = taskID;
+    context->uwR1 = 0x01010101L;
+    context->uwR2 = 0x02020202L;
+    context->uwR3 = 0x03030303L;
+    context->uwR12 = 0x12121212L;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
+    context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
+    context->uwxPSR = 0x01000000L;
+
+    return (VOID *)context;
+}
+
+#if (LOSCFG_KERNEL_SIGNAL == 1)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    UNUSED(stackTop);
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+#endif
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+    return LOS_OK; /* never return */
+}

arch/arm/cortex-m33/gcc/NTZ/los_dispatch.S

@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .syntax unified
+ .arch armv7e-m
+ .thumb
+ .fpu fpv5-d16
+//;.arch_extension sec
+
+
+.equ    OS_FPU_CPACR,                0xE000ED88
+.equ    OS_FPU_CPACR_ENABLE,         0x00F00000
+.equ    OS_NVIC_INT_CTRL,            0xE000ED04
+.equ    OS_NVIC_SYSPRI2,             0xE000ED20
+.equ    OS_NVIC_PENDSV_PRI,          0xF0F00000
+.equ    OS_NVIC_PENDSVSET,           0x10000000
+.equ    OS_TASK_STATUS_RUNNING,      0x0010
+
+    .section .text
+    .thumb
+
+.macro SIGNAL_CONTEXT_RESTORE
+    push    {r12, lr}
+    blx     OsSignalTaskContextRestore
+    pop     {r12, lr}
+    cmp     r0, #0
+    mov     r1, r0
+    bne     SignalContextRestore
+.endm
+
+    .type HalStartToRun, %function
+    .global HalStartToRun
+HalStartToRun:
+    .fnstart
+    .cantunwind
+
+    ldr     r4, =OS_NVIC_SYSPRI2
+    ldr     r5, =OS_NVIC_PENDSV_PRI
+    str     r5, [r4]
+
+    mov     r0, #2
+    msr     CONTROL, r0
+
+    ldr     r1, =g_losTask
+    ldr     r0, [r1, #4]
+    ldr     r12, [r0]
+
+    ldr.w   r1, =OS_FPU_CPACR
+    ldr     r1, [r1]
+    and     r1, r1, #OS_FPU_CPACR_ENABLE
+    cmp     r1, #OS_FPU_CPACR_ENABLE
+    bne     __DisabledFPU
+
+    add     r12, r12, #100
+
+    ldmfd   r12!, {r0-r7}
+    add     r12, r12, #72
+    msr     psp, r12
+    vpush   {S0}
+    vpop    {S0}
+
+    mov     lr, r5
+    cpsie   I
+    bx      r6
+
+__DisabledFPU:
+    ADD     r12, r12, #36
+
+    LDMFD   r12!, {r0-r7}
+    MSR     psp, r12
+    MOV     lr, r5
+    cpsie   I
+    BX      r6
+    .fnend
+
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
+    .fnstart
+    .cantunwind
+
+    MRS R0, PRIMASK
+    CPSID I
+    BX LR
+    .fnend
+
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
+    .fnstart
+    .cantunwind
+
+    MRS R0, PRIMASK
+    CPSIE I
+    BX LR
+    .fnend
+
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
+    .fnstart
+    .cantunwind
+
+    MSR PRIMASK, R0
+    BX LR
+    .fnend
+
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
+    .fnstart
+    .cantunwind
+
+    ldr     r0, =OS_NVIC_INT_CTRL
+    ldr     r1, =OS_NVIC_PENDSVSET
+    str     r1, [r0]
+    dsb
+    isb
+    bx      lr
+   .fnend
+
+    .type HalPendSV, %function
+    .global HalPendSV
+HalPendSV:
+    .fnstart
+    .cantunwind
+
+    mrs     r12, PRIMASK
+    cpsid   I
+
+HalTaskSwitch:
+    SIGNAL_CONTEXT_RESTORE
+
+    push    {r12, lr}
+    blx     OsSchedTaskSwitch
+    pop     {r12, lr}
+    cmp     r0, #0
+    mov     r0, lr
+    bne     TaskContextSwitch
+    msr     PRIMASK, r12
+    bx      lr
+
+TaskContextSwitch:
+    mov     lr, r0
+    mrs     r0, psp
+
+    stmfd   r0!, {r4-r12}
+
+    ldr.w   r3, =OS_FPU_CPACR
+    ldr     r3, [r3]
+    and     r3, r3, #OS_FPU_CPACR_ENABLE
+    cmp     r3, #OS_FPU_CPACR_ENABLE
+    bne     __DisabledFPU1
+    vstmdb   r0!, {d8-d15}
+
+__DisabledFPU1:
+    ldr     r5, =g_losTask
+    ldr     r6, [r5]
+    str     r0, [r6]
+
+    ldr     r0, [r5, #4]
+    str     r0, [r5]
+    ldr     r1,   [r0]
+
+SignalContextRestore:
+    ldr.w   r3, =OS_FPU_CPACR
+    ldr     r3, [r3]
+    and     r3, r3, #OS_FPU_CPACR_ENABLE
+    cmp     r3, #OS_FPU_CPACR_ENABLE
+    bne     __DisabledFPU2
+    VLDMIA  r1!, {d8-d15}
+
+__DisabledFPU2:
+    ldmfd   r1!, {r4-r12}
+    msr     psp,  r1
+    msr     PRIMASK, r12
+    bx      lr
+
+    .fnend

arch/arm/cortex-m33/gcc/NTZ/los_exc.S

@@ -1,384 +1,384 @@
-;
-; Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
-; Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without modification,
-; are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice, this list of
-;    conditions and the following disclaimer.
-;
-; 2. Redistributions in binary form must reproduce the above copyright notice, this list
-;    of conditions and the following disclaimer in the documentation and/or other materials
-;    provided with the distribution.
-;
-; 3. Neither the name of the copyright holder nor the names of its contributors may be used
-;    to endorse or promote products derived from this software without specific prior written
-;    permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
-; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-
- .syntax unified
- .arch armv7e-m
- .thumb
-.fpu vfpv4
-.section .text
-
-
-    .global  OsExcNMI
-    .global  OsExcHardFault
-    .global  OsExcMemFault
-    .global  OsExcBusFault
-    .global  OsExcUsageFault
-    .global  OsExcSvcCall
-
-    .extern OsExcHandleEntry
-    .extern g_vuwLosFlag
-    .extern g_uwCurNestCount
-    .extern g_uwExcTbl
-    .extern g_taskScheduled
-
-.equ OS_FLG_BGD_ACTIVE,   0x0002
-
-.equ OS_EXC_CAUSE_NMI,   16
-.equ OS_EXC_CAUSE_HARDFAULT,   17
-
-.equ HF_DEBUGEVT,   20
-.equ HF_VECTBL,   21
-
-.equ FLAG_ADDR_VALID,   0x10000
-.equ FLAG_HWI_ACTIVE,   0x20000
-.equ FLAG_NO_FLOAT,   0x10000000
-
-.equ OS_NVIC_FSR                 ,   0xE000ED28      //include BusFault/MemFault/UsageFault State Regeister
-.equ OS_NVIC_HFSR                ,   0xE000ED2C      //HardFault State Regeister
-.equ OS_NVIC_BFAR                ,   0xE000ED38
-.equ OS_NVIC_MMAR                ,   0xE000ED34
-.equ OS_NVIC_ACT_BASE            ,   0xE000E300
-.equ OS_NVIC_SHCSRS              ,   0xE000ED24
-.equ OS_NVIC_SHCSR_MASK          ,   0xC00
-
-    .type OsExcNMI, %function
-    .global OsExcNMI
-OsExcNMI:
-    .fnstart
-    .cantunwind
-    MOV  R0, #OS_EXC_CAUSE_NMI
-    MOV  R1, #0
-    B  osExcDispatch
-    .fnend
-
-    .type OsExcHardFault, %function
-    .global OsExcHardFault
-OsExcHardFault:
-    .fnstart
-    .cantunwind
-    MOV  R0, #OS_EXC_CAUSE_HARDFAULT
-    LDR  R2, =OS_NVIC_HFSR
-    LDR  R2, [R2]
-
-    MOV  R1, #HF_DEBUGEVT
-    ORR  R0, R0, R1, LSL #0x8
-    TST  R2, #0x80000000
-    BNE  osExcDispatch     // DEBUGEVT
-
-    AND  R0, #0x000000FF
-    MOV  R1, #HF_VECTBL
-    ORR  R0, R0, R1, LSL #0x8
-    TST  R2, #0x00000002
-    BNE  osExcDispatch     // VECTBL
-
-    //if not DEBUGEVT and VECTBL then is FORCED
-    AND  R0, #0x000000FF
-
-    LDR  R2, =OS_NVIC_FSR
-    LDR  R2, [R2]
-
-    TST  R2, #0x8000     // BFARVALID
-    BNE  _HFBusFault     // BusFault
-
-    TST  R2, #0x80       // MMARVALID
-    BNE  _HFMemFault     // MemFault
-
-    MOV  R12,#0
-    B    osHFExcCommonBMU
-    .fnend
-
-    .type _HFBusFault, %function
-
-_HFBusFault:
-    .fnstart
-    .cantunwind
-    LDR  R1, =OS_NVIC_BFAR
-    LDR  R1, [R1]
-    MOV  R12, #FLAG_ADDR_VALID
-    B    osHFExcCommonBMU
-    .fnend
-
-    .type _HFMemFault, %function
-
-_HFMemFault:
-    .fnstart
-    .cantunwind
-    LDR  R1, =OS_NVIC_MMAR
-    LDR  R1, [R1]
-    MOV  R12, #FLAG_ADDR_VALID
-    .fnend
-
-    .type osHFExcCommonBMU, %function
-    .global osHFExcCommonBMU
-osHFExcCommonBMU:
-    .fnstart
-    .cantunwind
-    CLZ  R2, R2
-    LDR  R3, =g_uwExcTbl
-    ADD  R3, R3, R2
-    LDRB R2, [R3]
-    ORR  R0, R0, R2, LSL #0x8
-    ORR  R0, R12
-    B    osExcDispatch
-    .fnend
-
-    .type OsExcSvcCall, %function
-    .global OsExcSvcCall
-OsExcSvcCall:
-    .fnstart
-    .cantunwind
-    TST   LR, #0x4
-    ITE   EQ
-    MRSEQ R0, MSP
-    MRSNE R0, PSP
-    LDR   R1, [R0,#24]
-    LDRB  R0, [R1,#-2]
-    MOV   R1, #0
-    B     osExcDispatch
-    .fnend
-
-    .type OsExcBusFault, %function
-    .global OsExcBusFault
-OsExcBusFault:
-    .fnstart
-    .cantunwind
-    LDR  R0, =OS_NVIC_FSR
-    LDR  R0, [R0]
-
-    TST  R0, #0x8000  // BFARVALID
-    BEQ  _ExcBusNoADDR
-    LDR  R1, =OS_NVIC_BFAR
-    LDR  R1, [R1]
-    MOV  R12, #FLAG_ADDR_VALID
-    AND  R0, #0x1F00
-
-    B    osExcCommonBMU
-    .fnend
-
-    .type _ExcBusNoADDR, %function
-    .global _ExcBusNoADDR
-_ExcBusNoADDR:
-    .fnstart
-    .cantunwind
-    MOV  R12,#0
-    B    osExcCommonBMU
-    .fnend
-
-    .type OsExcMemFault, %function
-    .global OsExcMemFault
-OsExcMemFault:
-    .fnstart
-    .cantunwind
-    LDR  R0, =OS_NVIC_FSR
-    LDR  R0, [R0]
-
-    TST  R0, #0x80 // MMARVALID
-    BEQ  _ExcMemNoADDR
-    LDR  R1, =OS_NVIC_MMAR
-    LDR  R1, [R1]
-    MOV  R12, #FLAG_ADDR_VALID
-    AND  R0, #0x1B
-
-    B    osExcCommonBMU
-    .fnend
-
-    .type _ExcMemNoADDR, %function
-    .global _ExcMemNoADDR
-_ExcMemNoADDR:
-    .fnstart
-    .cantunwind
-    MOV  R12,#0
-    B    osExcCommonBMU
-    .fnend
-
-    .type OsExcUsageFault, %function
-    .global OsExcUsageFault
-OsExcUsageFault:
-    .fnstart
-    .cantunwind
-    LDR  R0, =OS_NVIC_FSR
-    LDR  R0, [R0]
-
-    LDR  R1, =#0x030F
-    LSL  R1, #16
-    AND  R0, R1
-    MOV  R12, #0
-    .fnend
-
-    .type osExcCommonBMU, %function
-    .global osExcCommonBMU
-osExcCommonBMU:
-    .fnstart
-    .cantunwind
-    CLZ  R0, R0
-    LDR  R3, =g_uwExcTbl
-    ADD  R3, R3, R0
-    LDRB R0, [R3]
-    ORR  R0, R0, R12
-    .fnend
-// R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid),  R1 -- EXCADDR
-
-    .type osExcDispatch, %function
-    .global osExcDispatch
-osExcDispatch:
-    .fnstart
-    .cantunwind
-    LDR   R2, =OS_NVIC_ACT_BASE
-    MOV   R12, #8                       // R12 is hwi check loop counter
-    .fnend
-
-    .type _hwiActiveCheck, %function
-    .global _hwiActiveCheck
-_hwiActiveCheck:
-    .fnstart
-    .cantunwind
-    LDR   R3, [R2]                      // R3 store active hwi register when exc
-    CMP   R3, #0
-    BEQ   _hwiActiveCheckNext
-
-    // exc occured in IRQ
-    ORR   R0, #FLAG_HWI_ACTIVE
-    RBIT  R2, R3
-    CLZ   R2, R2
-    AND   R12, #1
-    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as uwPid
-    .fnend
-
-    .type _ExcInMSP, %function
-    .global _ExcInMSP
-_ExcInMSP:
-    .fnstart
-    .cantunwind
-    CMP   LR, #0XFFFFFFED
-    BNE   _NoFloatInMsp
-    ADD   R3, R13, #104
-    PUSH  {R3}
-    MRS   R12, PRIMASK                  // store message-->exc: disable int?
-    PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-    VPUSH {D8-D15}
-    B     _handleEntry
-  .fnend
-
-    .type _NoFloatInMsp, %function
-    .global _NoFloatInMsp
-_NoFloatInMsp:
-    .fnstart
-    .cantunwind
-    ADD   R3, R13, #32
-    PUSH  {R3} // save IRQ SP            // store message-->exc: MSP(R13)
-
-    MRS   R12, PRIMASK                  // store message-->exc: disable int?
-    PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-    ORR   R0, R0, #FLAG_NO_FLOAT
-    B     _handleEntry
-  .fnend
-
-    .type _hwiActiveCheckNext, %function
-    .global _hwiActiveCheckNext
-_hwiActiveCheckNext:
-    .fnstart
-    .cantunwind
-    ADD   R2, #4                        // next NVIC ACT ADDR
-    SUBS  R12, #1
-    BNE   _hwiActiveCheck
-
-    /*NMI interrupt excption*/
-    LDR   R2, =OS_NVIC_SHCSRS
-    LDRH  R2,[R2]
-    LDR   R3,=OS_NVIC_SHCSR_MASK
-    AND   R2, R2,R3
-    CMP   R2,#0
-    BNE   _ExcInMSP
-    // exc occured in Task or Init or exc
-    // reserved for register info from task stack
-
-    LDR  R2, =g_taskScheduled
-    LDR  R2, [R2]
-    TST  R2, #1         // OS_FLG_BGD_ACTIVE
-    BEQ  _ExcInMSP                      // if exc occured in Init then branch
-
-
-    CMP   LR, #0xFFFFFFED               //auto push floating registers
-    BNE   _NoFloatInPsp
-
-    // exc occured in Task
-    MOV   R2,  R13
-    SUB   R13, #96                      // add 8 Bytes reg(for STMFD)
-
-    MRS   R3,  PSP
-    ADD   R12, R3, #104
-    PUSH  {R12}    // save task SP
-
-    MRS   R12, PRIMASK
-    PUSH {R4-R12}
-    VPUSH {D8-D15}
-
-    // copy auto saved task register
-
-    LDMFD R3!, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
-    VLDMIA  R3!, {D8-D15}
-    VSTMDB  R2!, {D8-D15}
-    STMFD R2!, {R4-R11}
-    B     _handleEntry
-  .fnend
-
-    .type _NoFloatInPsp, %function
-    .global _NoFloatInPsp
-_NoFloatInPsp:
-    .fnstart
-    .cantunwind
-    MOV   R2,  R13                           //no auto push floating registers
-    SUB   R13, #32                      // add 8 Bytes reg(for STMFD)
-
-    MRS   R3,  PSP
-    ADD   R12, R3, #32
-    PUSH  {R12}    // save task SP
-
-    MRS   R12, PRIMASK
-    PUSH {R4-R12}
-
-    LDMFD R3, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
-    STMFD R2!, {R4-R11}
-    ORR   R0, R0, #FLAG_NO_FLOAT
-  .fnend
-
-    .type _handleEntry, %function
-    .global _handleEntry
-_handleEntry:
-    .fnstart
-    .cantunwind
-    MOV R3, R13                         // R13:the 4th param
-    CPSID I
-    CPSID F
-    B  OsExcHandleEntry
-
-    NOP
-  .fnend
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .syntax unified
+ .arch armv7e-m
+ .thumb
+.fpu fpv5-d16
+.section .text
+
+
+    .global  HalExcNMI
+    .global  HalExcHardFault
+    .global  HalExcMemFault
+    .global  HalExcBusFault
+    .global  HalExcUsageFault
+    .global  HalSVCHandler
+
+    .extern HalExcHandleEntry
+    .extern g_uwExcTbl
+    .extern g_taskScheduled
+
+.equ OS_FLG_BGD_ACTIVE,   0x0002
+
+.equ OS_EXC_CAUSE_NMI,   16
+.equ OS_EXC_CAUSE_HARDFAULT,   17
+
+.equ HF_DEBUGEVT,   20
+.equ HF_VECTBL,   21
+
+.equ FLAG_ADDR_VALID,   0x10000
+.equ FLAG_HWI_ACTIVE,   0x20000
+.equ FLAG_NO_FLOAT,   0x10000000
+
+.equ OS_NVIC_FSR                 ,   0xE000ED28      //include BusFault/MemFault/UsageFault State Register
+.equ OS_NVIC_HFSR                ,   0xE000ED2C      //HardFault State Register
+.equ OS_NVIC_BFAR                ,   0xE000ED38
+.equ OS_NVIC_MMAR                ,   0xE000ED34
+.equ OS_NVIC_ACT_BASE            ,   0xE000E300
+.equ OS_NVIC_SHCSRS              ,   0xE000ED24
+.equ OS_NVIC_SHCSR_MASK          ,   0xC00
+
+    .type HalExcNMI, %function
+    .global HalExcNMI
+HalExcNMI:
+    .fnstart
+    .cantunwind
+    MOV  R0, #OS_EXC_CAUSE_NMI
+    MOV  R1, #0
+    B  osExcDispatch
+    .fnend
+
+    .type HalExcHardFault, %function
+    .global HalExcHardFault
+HalExcHardFault:
+    .fnstart
+    .cantunwind
+    MOV  R0, #OS_EXC_CAUSE_HARDFAULT
+    LDR  R2, =OS_NVIC_HFSR
+    LDR  R2, [R2]
+
+    MOV  R1, #HF_DEBUGEVT
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x80000000
+    BNE  osExcDispatch     // DEBUGEVT
+
+    AND  R0, R0 , #0x000000FF
+    MOV  R1, #HF_VECTBL
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x00000002
+    BNE  osExcDispatch     // VECTBL
+
+    //if not DEBUGEVT and VECTBL then is FORCED
+    AND  R0, R0, #0x000000FF
+
+    LDR  R2, =OS_NVIC_FSR
+    LDR  R2, [R2]
+
+    TST  R2, #0x8000     // BFARVALID
+    BNE  _HFBusFault     // BusFault
+
+    TST  R2, #0x80       // MMARVALID
+    BNE  _HFMemFault     // MemFault
+
+    MOV  R12,#0
+    B    osHFExcCommonBMU
+    .fnend
+
+    .type _HFBusFault, %function
+
+_HFBusFault:
+    .fnstart
+    .cantunwind
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    B    osHFExcCommonBMU
+    .fnend
+
+    .type _HFMemFault, %function
+
+_HFMemFault:
+    .fnstart
+    .cantunwind
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    .fnend
+
+    .type osHFExcCommonBMU, %function
+    .global osHFExcCommonBMU
+osHFExcCommonBMU:
+    .fnstart
+    .cantunwind
+    CLZ  R2, R2
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R2
+    LDRB R2, [R3]
+    ORR  R0, R0, R2, LSL #0x8
+    ORR  R0, R0 ,R12
+    B    osExcDispatch
+    .fnend
+
+    .type HalSVCHandler, %function
+    .global HalSVCHandler
+HalSVCHandler:
+    .fnstart
+    .cantunwind
+    TST   LR, #0x4
+    ITE   EQ
+    MRSEQ R0, MSP
+    MRSNE R0, PSP
+    LDR   R1, [R0,#24]
+    LDRB  R0, [R1,#-2]
+    MOV   R1, #0
+    B     osExcDispatch
+    .fnend
+
+    .type HalExcBusFault, %function
+    .global HalExcBusFault
+HalExcBusFault:
+    .fnstart
+    .cantunwind
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x8000  // BFARVALID
+    BEQ  _ExcBusNoADDR
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1F00
+
+    B    osExcCommonBMU
+    .fnend
+
+    .type _ExcBusNoADDR, %function
+    .global _ExcBusNoADDR
+_ExcBusNoADDR:
+    .fnstart
+    .cantunwind
+    MOV  R12,#0
+    B    osExcCommonBMU
+    .fnend
+
+    .type HalExcMemFault, %function
+    .global HalExcMemFault
+HalExcMemFault:
+    .fnstart
+    .cantunwind
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x80 // MMARVALID
+    BEQ  _ExcMemNoADDR
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1B
+
+    B    osExcCommonBMU
+    .fnend
+
+    .type _ExcMemNoADDR, %function
+    .global _ExcMemNoADDR
+_ExcMemNoADDR:
+    .fnstart
+    .cantunwind
+    MOV  R12,#0
+    B    osExcCommonBMU
+    .fnend
+
+    .type HalExcUsageFault, %function
+    .global HalExcUsageFault
+HalExcUsageFault:
+    .fnstart
+    .cantunwind
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    MOVW  R1, #0x030F
+    LSL  R1, R1, #16
+    AND  R0, R0, R1
+    MOV  R12, #0
+
+    .fnend
+
+    .type osExcCommonBMU, %function
+    .global osExcCommonBMU
+osExcCommonBMU:
+    .fnstart
+    .cantunwind
+    CLZ  R0, R0
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R0
+    LDRB R0, [R3]
+    ORR  R0, R0, R12
+    .fnend
+// R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid),  R1 -- EXCADDR
+
+    .type osExcDispatch, %function
+    .global osExcDispatch
+osExcDispatch:
+    .fnstart
+    .cantunwind
+    LDR   R2, =OS_NVIC_ACT_BASE
+    MOV   R12, #8                       // R12 is hwi check loop counter
+    .fnend
+
+    .type _hwiActiveCheck, %function
+    .global _hwiActiveCheck
+_hwiActiveCheck:
+    .fnstart
+    .cantunwind
+    LDR   R3, [R2]                      // R3 store active hwi register when exc
+    CMP   R3, #0
+    BEQ   _hwiActiveCheckNext
+
+    // exc occured in IRQ
+    ORR   R0, R0, #FLAG_HWI_ACTIVE
+    RBIT  R2, R3
+    CLZ   R2, R2
+    AND   R12, R12, #1
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
+    .fnend
+
+    .type _ExcInMSP, %function
+    .global _ExcInMSP
+_ExcInMSP:
+    .fnstart
+    .cantunwind
+    CMP   LR, #0xFFFFFFE9
+    BNE   _NoFloatInMsp
+    ADD   R3, R13, #104
+    PUSH  {R3}
+    MRS   R12, PRIMASK                  // store message-->exc: disable int?
+    PUSH {R4-R12}                       // store message-->exc: {R4-R12}
+    VPUSH {D8-D15}
+    B     _handleEntry
+  .fnend
+
+    .type _NoFloatInMsp, %function
+    .global _NoFloatInMsp
+_NoFloatInMsp:
+    .fnstart
+    .cantunwind
+    ADD   R3, R13, #32
+    PUSH  {R3} // save IRQ SP            // store message-->exc: MSP(R13)
+
+    MRS   R12, PRIMASK                  // store message-->exc: disable int?
+    PUSH {R4-R12}                       // store message-->exc: {R4-R12}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+    B     _handleEntry
+  .fnend
+
+    .type _hwiActiveCheckNext, %function
+    .global _hwiActiveCheckNext
+_hwiActiveCheckNext:
+    .fnstart
+    .cantunwind
+    ADD   R2, R2, #4                        // next NVIC ACT ADDR
+    SUBS  R12, R12, #1
+    BNE   _hwiActiveCheck
+
+    /*NMI interrupt excption*/
+    LDR   R2, =OS_NVIC_SHCSRS
+    LDRH  R2,[R2]
+    LDR   R3,=OS_NVIC_SHCSR_MASK
+    AND   R2, R2,R3
+    CMP   R2,#0
+    BNE   _ExcInMSP
+    // exc occured in Task or Init or exc
+    // reserved for register info from task stack
+
+    LDR  R2, =g_taskScheduled
+    LDR  R2, [R2]
+    TST  R2, #1                         // OS_FLG_BGD_ACTIVE
+    BEQ  _ExcInMSP                      // if exc occured in Init then branch
+
+
+    CMP   LR, #0xFFFFFFED               //auto push floating registers
+    BNE   _NoFloatInPsp
+
+    // exc occured in Task
+    MOV   R2,  R13
+    SUB   R13, #96                      // add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #104
+    PUSH  {R12}                         // save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+    VPUSH {D8-D15}
+
+    // copy auto saved task register
+
+    LDMFD R3!, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
+    VLDMIA  R3!, {D8-D15}
+    VSTMDB  R2!, {D8-D15}
+    STMFD R2!, {R4-R11}
+    B     _handleEntry
+  .fnend
+
+    .type _NoFloatInPsp, %function
+    .global _NoFloatInPsp
+_NoFloatInPsp:
+    .fnstart
+    .cantunwind
+    MOV   R2,  R13                      // no auto push floating registers
+    SUB   R13, #32                      // add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #32
+    PUSH  {R12}                         // save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+
+    LDMFD R3, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
+    STMFD R2!, {R4-R11}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+  .fnend
+
+    .type _handleEntry, %function
+    .global _handleEntry
+_handleEntry:
+    .fnstart
+    .cantunwind
+    MOV R3, R13                         // R13:the 4th param
+    CPSID I
+    CPSID F
+    B  HalExcHandleEntry
+
+    NOP
+  .fnend
+

arch/arm/cortex-m33/gcc/NTZ/los_interrupt.c

@@ -0,0 +1,606 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "los_interrupt.h"
+#include <stdarg.h>
+#include "securec.h"
+#include "los_context.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+
+#define DEF_HANDLER_START_INDEX 2
+/*lint -save -e40 -e522 -e533*/
+UINT32 g_intCount = 0;
+
+/*lint -restore*/
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+    HWI_PROC_FUNC pfnHandler;
+    VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+    }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+    }
+}
+#endif
+
+/* ****************************************************************************
+ Function    : HwiNumGet
+ Description : Get an interrupt number
+ Input       : None
+ Output      : None
+ Return      : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+    return __get_IPSR();
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+    return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function    : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+/*lint -e529*/
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+    while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+    UINT32 hwiIndex;
+    UINT32 intSave;
+
+#if (LOSCFG_KERNEL_RUNSTOP == 1)
+    SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
+#endif
+
+    intSave = LOS_IntLock();
+    g_intCount++;
+    LOS_IntRestore(intSave);
+
+    hwiIndex = HwiNumGet();
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+
+    HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+        g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+    }
+#else
+    if (g_hwiHandlerForm[hwiIndex] != 0) {
+        g_hwiHandlerForm[hwiIndex]();
+    }
+#endif
+
+    HalAftInterruptHandler(hwiIndex);
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+    intSave = LOS_IntLock();
+    g_intCount--;
+    LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiCreate
+ Description : create hardware interrupt
+ Input       : hwiNum   --- hwi num to create
+               hwiPrio  --- priority of the hwi
+               hwiMode  --- unused
+               hwiHandler --- hwi handler
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T hwiMode,
+                                           HWI_PROC_FUNC hwiHandler,
+                                           HwiIrqParam *irqParam)
+{
+    (VOID)hwiMode;
+    UINT32 intSave;
+
+    if (hwiHandler == NULL) {
+        return OS_ERRNO_HWI_PROC_FUNC_NULL;
+    }
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return OS_ERRNO_HWI_ALREADY_CREATED;
+    }
+
+    if (hwiPrio > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (irqParam != NULL) {
+        OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+    } else {
+        OsSetVector(hwiNum, hwiHandler, NULL);
+    }
+#else
+    (VOID)irqParam;
+    OsSetVector(hwiNum, hwiHandler);
+#endif
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input       : hwiNum   --- hwi num to delete
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+    (VOID)irqParam;
+    UINT32 intSave;
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    HwiMask((IRQn_Type)hwiNum);
+
+    intSave = LOS_IntLock();
+
+    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+#define FAULT_STATUS_REG_BIT            32
+#define USGFAULT                        (1 << 18)
+#define BUSFAULT                        (1 << 17)
+#define MEMFAULT                        (1 << 16)
+#define DIV0FAULT                       (1 << 4)
+#define UNALIGNFAULT                    (1 << 3)
+#define HARDFAULT_IRQN                  (-13)
+
+ExcInfo g_excInfo = {0};
+
+UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
+    0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
+    0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
+    0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
+    0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
+};
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcNvicDump(VOID)
+{
+#define OS_NR_NVIC_EXC_DUMP_TYPES   7
+    UINT32 *base = NULL;
+    UINT32 len, i, j;
+    UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
+        OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
+    };
+    UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
+        OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
+        OS_NVIC_INT_CTRL_SIZE
+    };
+    CHAR strRgEnable[] = "enable";
+    CHAR strRgPending[] = "pending";
+    CHAR strRgActive[] = "active";
+    CHAR strRgPriority[] = "priority";
+    CHAR strRgException[] = "exception";
+    CHAR strRgShcsr[] = "shcsr";
+    CHAR strRgIntCtrl[] = "control";
+    CHAR *strRgs[] = {
+        strRgEnable, strRgPending, strRgActive, strRgPriority,
+        strRgException, strRgShcsr, strRgIntCtrl
+    };
+
+    PRINTK("\r\nOS exception NVIC dump:\n");
+    for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
+        base = (UINT32 *)rgNvicBases[i];
+        len = rgNvicLens[i];
+        PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
+        len = (len >> 2); /* 2: Gets the next register offset */
+        for (j = 0; j < len; j++) {
+            PRINTK("0x%x ", *(base + j));
+            if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
+                PRINTK("\n");
+            }
+        }
+        PRINTK("\n");
+    }
+}
+
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+    CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+    PRINTK("Type      = %d\n", excInfo->type);
+    PRINTK("ThrdPid   = %d\n", excInfo->thrdPid);
+    PRINTK("Phase     = %s\n", phaseStr[excInfo->phase]);
+    PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Current task info:\n");
+    if (excInfo->phase == OS_EXC_IN_TASK) {
+        LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+        PRINTK("Task name = %s\n", taskCB->taskName);
+        PRINTK("Task ID   = %d\n", taskCB->taskID);
+        PRINTK("Task SP   = %p\n", taskCB->stackPointer);
+        PRINTK("Task ST   = 0x%x\n", taskCB->topOfStack);
+        PRINTK("Task SS   = 0x%x\n", taskCB->stackSize);
+    } else if (excInfo->phase == OS_EXC_IN_HWI) {
+        PRINTK("Exception occur in interrupt phase!\n");
+    } else {
+        PRINTK("Exception occur in system init phase!\n");
+    }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Exception reg dump:\n");
+    PRINTK("PC        = 0x%x\n", excInfo->context->uwPC);
+    PRINTK("LR        = 0x%x\n", excInfo->context->uwLR);
+    PRINTK("SP        = 0x%x\n", excInfo->context->uwSP);
+    PRINTK("R0        = 0x%x\n", excInfo->context->uwR0);
+    PRINTK("R1        = 0x%x\n", excInfo->context->uwR1);
+    PRINTK("R2        = 0x%x\n", excInfo->context->uwR2);
+    PRINTK("R3        = 0x%x\n", excInfo->context->uwR3);
+    PRINTK("R4        = 0x%x\n", excInfo->context->uwR4);
+    PRINTK("R5        = 0x%x\n", excInfo->context->uwR5);
+    PRINTK("R6        = 0x%x\n", excInfo->context->uwR6);
+    PRINTK("R7        = 0x%x\n", excInfo->context->uwR7);
+    PRINTK("R8        = 0x%x\n", excInfo->context->uwR8);
+    PRINTK("R9        = 0x%x\n", excInfo->context->uwR9);
+    PRINTK("R10       = 0x%x\n", excInfo->context->uwR10);
+    PRINTK("R11       = 0x%x\n", excInfo->context->uwR11);
+    PRINTK("R12       = 0x%x\n", excInfo->context->uwR12);
+    PRINTK("PriMask   = 0x%x\n", excInfo->context->uwPriMask);
+    PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+    UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+    UINT32 index;
+
+    OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
+
+    PRINTK("----- backtrace start -----\n");
+    for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+        if (LR[index] == 0) {
+            break;
+        }
+        PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
+    }
+    PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+    PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+    MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+    UINT32 errCnt;
+    UINT32 i;
+
+    (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+    errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+    if (errCnt < OS_SYS_MEM_NUM) {
+        errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+    }
+
+    if (errCnt == 0) {
+        PRINTK("all memory pool check passed!\n");
+        return;
+    }
+
+    for (i = 0; i < errCnt; i++) {
+        PRINTK("pool num    = %d\n", i);
+        PRINTK("pool type   = %d\n", memExcInfo[i].type);
+        PRINTK("pool addr   = 0x%x\n", memExcInfo[i].startAddr);
+        PRINTK("pool size   = 0x%x\n", memExcInfo[i].size);
+        PRINTK("pool free   = 0x%x\n", memExcInfo[i].free);
+        PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
+        PRINTK("pool error node addr  = 0x%x\n", memExcInfo[i].errorAddr);
+        PRINTK("pool error node len   = 0x%x\n", memExcInfo[i].errorLen);
+        PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
+    }
+#endif
+    UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+    if (ret == LOS_OK) {
+        PRINTK("system heap memcheck over, all passed!\n");
+    }
+
+    PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+    PRINTK("*************Exception Information**************\n");
+    OsExcTypeInfo(excInfo);
+    OsExcCurTaskInfo(excInfo);
+    OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+    OsExcBackTraceInfo(excInfo);
+#endif
+    OsGetAllTskInfo();
+    OsExcNvicDump();
+    OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+    UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
+    g_intCount++;
+    g_excInfo.nestCnt++;
+
+    g_excInfo.type = excType & OS_NULL_SHORT;
+
+    if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
+        g_excInfo.faultAddr = faultAddr;
+    } else {
+        g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+    }
+    if (g_losTask.runTask != NULL) {
+        if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
+            g_excInfo.phase = OS_EXC_IN_HWI;
+            g_excInfo.thrdPid = pid;
+        } else {
+            g_excInfo.phase = OS_EXC_IN_TASK;
+            g_excInfo.thrdPid = g_losTask.runTask->taskID;
+        }
+    } else {
+        g_excInfo.phase = OS_EXC_IN_INIT;
+        g_excInfo.thrdPid = OS_NULL_INT;
+    }
+    if (excType & OS_EXC_FLAG_NO_FLOAT) {
+        g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
+    } else {
+        g_excInfo.context = excBufAddr;
+    }
+
+    OsDoExcHook(EXC_INTERRUPT);
+    OsExcInfoDisplay(&g_excInfo);
+    ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function    : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    UINT32 index;
+    g_hwiForm[0] = 0;             /* [0] Top of Stack */
+    g_hwiForm[1] = 0; /* [1] reset */
+    for (index = DEF_HANDLER_START_INDEX; index < OS_VECTOR_CNT; index++) {
+        g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+    }
+    /* Exception handler register */
+    g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT]   = HalExcNMI;
+    g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT]        = HalExcHardFault;
+    g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = HalExcMemFault;
+    g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT]         = HalExcBusFault;
+    g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT]       = HalExcUsageFault;
+    g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT]           = HalSVCHandler;
+    g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT]           = HalPendSV;
+    g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT]          = OsTickHandler;
+
+    /* Interrupt vector table location */
+    SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
+#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
+    NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
+#endif
+
+    /* Enable USGFAULT, BUSFAULT, MEMFAULT */
+    *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+	
+    /* Enable DIV 0 and unaligned exception */
+#ifdef LOSCFG_ARCH_UNALIGNED_EXC
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
+#else
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
+#endif
+
+    return;
+}
+

arch/arm/cortex-m33/gcc/NTZ/los_timer.c

@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "los_tick.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+    UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
+
+    tick->freq = OS_SYS_CLOCK;
+
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
+#else
+    OsSetVector(tick->irqNum, handler);
+#endif
+#endif
+
+    ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
+    if (ret == 1) {
+        return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
+    }
+
+    return LOS_OK;
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+    if (nextResponseTime > g_archTickTimer.periodMax) {
+        nextResponseTime = g_archTickTimer.periodMax;
+    }
+
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
+    SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+    UINT32 hwCycle = 0;
+    UINT32 intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
+    *period = SysTick->LOAD;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
+    LOS_IntRestore(intSave);
+    return (UINT64)hwCycle;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return LOS_OK;
+}

arch/arm/cortex-m33/gcc/TZ/BUILD.gn

@@ -0,0 +1,52 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_name = "arch"
+kernel_module(module_name) {
+  sources = [
+    "non_secure/los_context.c",
+    "non_secure/los_dispatch.S",
+    "non_secure/los_exc.S",
+    "non_secure/los_interrupt.c",
+    "non_secure/los_timer.c",
+    "non_secure/los_trustzone.c",
+  ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
+
+  include_dirs = [
+    "non_secure",
+    "secure",
+  ]
+}
+
+config("public") {
+  include_dirs = [ "non_secure" ]
+}

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_atomic.h

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    __asm__ __volatile__("ldrex %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%1]\n"
+                             "strex %0, %2, [%1]\n"
+                             : "=&r"(status)
+                             : "r"(v), "r"(setVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "add %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "sub %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%3]\n"
+                             "strex %1, %4, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("ldrex %0, %2\n"
+                             "mov %1, #0\n"
+                             "cmp %0, %3\n"
+                             "bne 1f\n"
+                             "strex %1, %4, %2\n"
+                             "1:"
+                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
+                             : "r"(oldVal), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_context.h

@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct TagTskContext {
+    UINT32 secureContext;
+    UINT32 stackLimit;
+    UINT32 excReturn;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} TaskContext;
+
+/**
+ * @ingroup  los_config
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_interrupt.h

@@ -0,0 +1,683 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_INTERRUPT_H
+#define _LOS_ARCH_INTERRUPT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST                   0
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST                    7
+#endif
+
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of M-Core system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT                     16
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of M-Core interrupt vector.
+ */
+#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * AIRCR register priority group parameter .
+ */
+#define OS_NVIC_AIRCR_PRIGROUP                7
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Boot interrupt vector table.
+ */
+extern UINT32 _BootVectors[];
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * SysTick control and status register.
+ */
+#define OS_SYSTICK_CONTROL_REG                0xE000E010
+
+/* *
+ * @ingroup los_hw
+ * SysTick current value register.
+ */
+#define OS_SYSTICK_CURRENT_REG                0xE000E018
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt Priority-Level Registers.
+ */
+#define OS_NVIC_PRI_BASE                      0xE000E400
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt enable register for 0-31.
+ */
+#define OS_NVIC_SETENA_BASE                   0xE000E100
+
+/* *
+ * @ingroup los_arch_interrupt
+ * interrupt pending register.
+ */
+#define OS_NVIC_SETPEND_BASE                  0xE000E200
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt active register.
+ */
+#define OS_NVIC_INT_ACT_BASE                  0xE000E300
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt disable register for 0-31.
+ */
+#define OS_NVIC_CLRENA_BASE                   0xE000E180
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt control and status register.
+ */
+#define OS_NVIC_INT_CTRL                      0xE000ED04
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Vector table offset register.
+ */
+#define OS_NVIC_VTOR                          0xE000ED08
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Application interrupt and reset control register
+ */
+#define OS_NVIC_AIRCR                         0xE000ED0C
+
+/* *
+ * @ingroup los_arch_interrupt
+ * System exception priority register.
+ */
+#define OS_NVIC_EXCPRI_BASE                   0xE000ED18
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 1 :reset.
+ */
+#define OS_EXC_RESET                          1
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 2 :Non-Maskable Interrupt.
+ */
+#define OS_EXC_NMI                            2
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 3 :(hard)fault.
+ */
+#define OS_EXC_HARD_FAULT                     3
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 4 :MemManage fault.
+ */
+#define OS_EXC_MPU_FAULT                      4
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 5 :Bus fault.
+ */
+#define OS_EXC_BUS_FAULT                      5
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 6 :Usage fault.
+ */
+#define OS_EXC_USAGE_FAULT                    6
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 11 :SVCall.
+ */
+#define OS_EXC_SVC_CALL                       11
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 12 :Debug monitor.
+ */
+#define OS_EXC_DBG_MONITOR                    12
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 14 :PendSV.
+ */
+#define OS_EXC_PEND_SV                        14
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Interrupt No. 15 :SysTick.
+ */
+#define OS_EXC_SYS_TICK                       15
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_arch_interrupt
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_arch_interrupt
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Reset the vector table.
+ *
+ * @par Description:
+ * This API is used to reset the vector table.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID Reset_Handler(VOID);
+
+/* *
+ * @ingroup  los_arch_interrupt
+ * @brief: Pended System Call.
+ *
+ * @par Description:
+ * PendSV can be pended and is useful for an OS to pend an exception
+ * so that an action can be performed after other important tasks are completed.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalPendSV(VOID);
+
+
+#define OS_EXC_IN_INIT                      0
+#define OS_EXC_IN_TASK                      1
+#define OS_EXC_IN_HWI                       2
+
+#define OS_EXC_MAX_BUF_LEN                  25
+#define OS_EXC_MAX_NEST_DEPTH               1
+
+#define OS_NVIC_SHCSR                       0xE000ED24
+#define OS_NVIC_CCR                         0xE000ED14
+
+#define OS_NVIC_INT_ENABLE_SIZE             0x20
+#define OS_NVIC_INT_PRI_SIZE                0xF0
+#define OS_NVIC_EXCPRI_SIZE                 0xC
+#define OS_NVIC_INT_CTRL_SIZE               4
+#define OS_NVIC_SHCSR_SIZE                  4
+
+#define OS_NVIC_INT_PEND_SIZE               OS_NVIC_INT_ACT_SIZE
+#define OS_NVIC_INT_ACT_SIZE                OS_NVIC_INT_ENABLE_SIZE
+
+#define OS_EXC_FLAG_NO_FLOAT                0x10000000
+#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
+#define OS_EXC_FLAG_IN_HWI                  0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
+
+#define OS_EXC_EVENT                        0x00000001
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
+ */
+typedef struct TagExcContext {
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    /* auto save */
+    UINT32 uwSP;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED) && (__FPU_USED== 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+
+VOID HalExcNMI(VOID);
+VOID HalExcHardFault(VOID);
+VOID HalExcMemFault(VOID);
+VOID HalExcBusFault(VOID);
+VOID HalExcUsageFault(VOID);
+VOID HalSVCHandler(VOID);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was being pushed.
+ */
+#define OS_EXC_BF_STKERR           1
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was out of the stack.
+ */
+#define OS_EXC_BF_UNSTKERR         2
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register imprecise data access violation.
+ */
+#define OS_EXC_BF_IMPRECISERR      3
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register exact data access violation.
+ */
+#define OS_EXC_BF_PRECISERR        4
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register access violation while pointing.
+ */
+#define OS_EXC_BF_IBUSERR          5
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was being pushed.
+ */
+#define OS_EXC_MF_MSTKERR          6
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
+ */
+#define OS_EXC_MF_MUNSTKERR        7
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register data access violation.
+ */
+#define OS_EXC_MF_DACCVIOL         8
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register access violation.
+ */
+#define OS_EXC_MF_IACCVIOL         9
+
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
+ */
+#define OS_EXC_UF_DIVBYZERO        10
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error, error caused by unaligned access.
+ */
+#define OS_EXC_UF_UNALIGNED        11
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
+ */
+#define OS_EXC_UF_NOCP             12
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
+ */
+#define OS_EXC_UF_INVPC            13
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
+ */
+#define OS_EXC_UF_INVSTATE         14
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
+ */
+#define OS_EXC_UF_UNDEFINSTR       15
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: NMI
+ */
+
+#define OS_EXC_CAUSE_NMI           16
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: hard fault
+ */
+#define OS_EXC_CAUSE_HARDFAULT     17
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: The task handler exits.
+ */
+#define OS_EXC_CAUSE_TASK_EXIT     18
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A fatal error.
+ */
+#define OS_EXC_CAUSE_FATAL_ERR     19
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Hard Fault caused by a debug event.
+ */
+#define OS_EXC_CAUSE_DEBUGEVT      20
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
+ */
+#define OS_EXC_CAUSE_VECTBL        21
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M33 platform.
+ *
+ */
+typedef struct TagExcInfo {
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    UINT16 phase;
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
+    UINT16 type;
+    /**< If the exact address access error indicates the wrong access address when the exception occurred */
+    UINT32 faultAddr;
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    UINT32 thrdPid;
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
+    UINT16 nestCnt;
+    /**< reserve */
+    UINT16 reserved;
+    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+    EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_curNestCount;
+extern UINT32 g_intCount;
+extern UINT8 g_uwExcTbl[32];
+extern ExcInfo g_excInfo;
+
+#define MAX_INT_INFO_SIZE       (8 + 0x164)
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_INTERRUPT_H */

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_timer.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */

arch/arm/cortex-m33/gcc/TZ/non_secure/los_context.c

@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
+
+/* ****************************************************************************
+ Function    : ArchInit
+ Description : arch init function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+    HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function    : ArchSysExit
+ Description : Task exit function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+    LOS_IntLock();
+    while (1) {
+    }
+}
+
+/* ****************************************************************************
+ Function    : ArchTskStackInit
+ Description : Task stack initialization function
+ Input       : taskID     --- TaskID
+               stackSize  --- Total size of the stack
+               topStack   --- Top of task's stack
+ Output      : None
+ Return      : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
+
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    context->S16 = 0xAA000010;
+    context->S17 = 0xAA000011;
+    context->S18 = 0xAA000012;
+    context->S19 = 0xAA000013;
+    context->S20 = 0xAA000014;
+    context->S21 = 0xAA000015;
+    context->S22 = 0xAA000016;
+    context->S23 = 0xAA000017;
+    context->S24 = 0xAA000018;
+    context->S25 = 0xAA000019;
+    context->S26 = 0xAA00001A;
+    context->S27 = 0xAA00001B;
+    context->S28 = 0xAA00001C;
+    context->S29 = 0xAA00001D;
+    context->S30 = 0xAA00001E;
+    context->S31 = 0xAA00001F;
+    context->S0 = 0xAA000000;
+    context->S1 = 0xAA000001;
+    context->S2 = 0xAA000002;
+    context->S3 = 0xAA000003;
+    context->S4 = 0xAA000004;
+    context->S5 = 0xAA000005;
+    context->S6 = 0xAA000006;
+    context->S7 = 0xAA000007;
+    context->S8 = 0xAA000008;
+    context->S9 = 0xAA000009;
+    context->S10 = 0xAA00000A;
+    context->S11 = 0xAA00000B;
+    context->S12 = 0xAA00000C;
+    context->S13 = 0xAA00000D;
+    context->S14 = 0xAA00000E;
+    context->S15 = 0xAA00000F;
+    context->FPSCR = 0x00000000;
+    context->NO_NAME = 0xAA000011;
+#endif
+
+    context->secureContext = 0UL;
+    context->stackLimit = (UINT32)topStack;
+    context->excReturn = 0xFFFFFFBC;
+
+    context->uwR4 = 0x04040404L;
+    context->uwR5 = 0x05050505L;
+    context->uwR6 = 0x06060606L;
+    context->uwR7 = 0x07070707L;
+    context->uwR8 = 0x08080808L;
+    context->uwR9 = 0x09090909L;
+    context->uwR10 = 0x10101010L;
+    context->uwR11 = 0x11111111L;
+    context->uwPriMask = 0;
+    context->uwR0 = taskID;
+    context->uwR1 = 0x01010101L;
+    context->uwR2 = 0x02020202L;
+    context->uwR3 = 0x03030303L;
+    context->uwR12 = 0x12121212L;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
+    context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
+    context->uwxPSR = 0x01000000L;
+
+    return (VOID *)context;
+}
+
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->stackLimit = (UINT32)stackTop;
+    context->excReturn = 0xFFFFFFBC;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+    return LOS_OK; /* never return */
+}

arch/arm/cortex-m33/gcc/TZ/non_secure/los_dispatch.S

@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .syntax unified
+ .arch armv7e-m
+ .thumb
+ .fpu fpv5-d16
+
+.equ    OS_FPU_CPACR,                0xE000ED88
+.equ    OS_FPU_CPACR_ENABLE,         0x00F00000
+.equ    OS_NVIC_INT_CTRL,            0xE000ED04
+.equ    OS_NVIC_SYSPRI2,             0xE000ED20
+.equ    OS_NVIC_PENDSV_PRI,          0xF0F00000
+.equ    OS_NVIC_PENDSVSET,           0x10000000
+.equ    OS_TASK_STATUS_RUNNING,      0x0010
+
+    .section .text
+    .thumb
+
+.macro SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+.endm
+
+    .type HalStartFirstTask, %function
+    .global HalStartFirstTask
+HalStartFirstTask:
+    MOV     R0, #2
+    MSR     CONTROL, R0
+
+    LDR     R1, =g_losTask
+    LDR     R0, [R1, #4]
+
+    LDR     R12, [R0]                  /* Get the stack pointer of the current task. */
+    LDMFD   R12!, {R1-R3}              /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 = excReturn.*/
+    LDR     R4, =g_secureContext
+    STR     R1, [R4]                   /* Set the secureContext to g_secureContext handler. */
+    MSR     PSPLIM, R2                 /* Set the stackLmit for the PSPLIM about current task. */
+    ISB
+
+    LDR.W   R1, =OS_FPU_CPACR
+    LDR     R1, [R1]
+    AND     R1, R1, #OS_FPU_CPACR_ENABLE
+    CMP     R1, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU1
+    ADD     R12, R12, #64
+    VPUSH   {S0}
+    VPOP    {S0}
+
+__DisabledFPU1:
+    ADD     R12, R12, #36
+    MSR     PSP, R12
+    CPSIE   I
+    BX      R3
+
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
+    .fnstart
+    .cantunwind
+
+    MRS R0, PRIMASK
+    CPSID I
+    BX LR
+    .fnend
+
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
+    .fnstart
+    .cantunwind
+
+    MRS R0, PRIMASK
+    CPSIE I
+    BX LR
+    .fnend
+
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
+    .fnstart
+    .cantunwind
+
+    MSR PRIMASK, R0
+    BX LR
+    .fnend
+
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
+    .fnstart
+    .cantunwind
+
+    ldr     r0, =OS_NVIC_INT_CTRL
+    ldr     r1, =OS_NVIC_PENDSVSET
+    str     r1, [r0]
+    dsb
+    isb
+    bx      lr
+   .fnend
+
+    .type HalPendSV, %function
+    .global HalPendSV
+HalPendSV:
+    .fnstart
+    .cantunwind
+
+    mrs     r12, PRIMASK
+    cpsid   I
+
+HalTaskSwitch:
+    SIGNAL_CONTEXT_RESTORE
+
+    push    {r12, lr}
+    blx     OsSchedTaskSwitch
+    pop     {r12, lr}
+    cmp     r0, #0
+    mov     r0, lr
+    bne     TaskContextSwitch
+    msr     PRIMASK, r12
+    bx      lr
+
+TaskContextSwitch:
+    mov     lr, r0
+    mrs     r0, psp
+
+    LDR     R2, =g_secureContext
+    LDR     R1, [R2]
+    CBZ     R1, __SaveNSContext               /* If the g_secureContext is NULL, so no secure context to save. */
+
+    PUSH    {R0-R1, R12, R14}                 /* Store registers, include LR, PRIMASK. */
+    BL      HalSecureContextSave              /* Store the secure context to g_secureContext->curStackPointer. */
+    POP     {R0-R3}
+    MOV     LR, R3
+    MOV     R12, R2                           /* R2 = PRIMASK. */
+
+__SaveNSContext:
+    STMFD   R0!, {R4-R12}
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU2
+    VSTMDB  R0!, {D8-D15}
+
+__DisabledFPU2:
+    LDR     R5, =g_losTask
+    LDR     R6, [R5]                          /* Get the stackPointer handler of the current task. */
+    SUBS    R0, R0, #12
+    STR     R0, [R6]                          /* Save the new top of stack in TCB. */
+    MRS     R2, PSPLIM
+    MOV     R3, LR
+    STMIA   R0!, {R1, R2-R3}                  /* Store g_secureContext, PSPLIM and LR on the stack of current task. */
+
+    LDR     R0, [R5, #4]
+    STR     R0, [R5]
+    LDR     R1, [R0]
+
+SignalContextRestore:
+    LDMIA   R1!, {R0, R2-R3}                  /* Restore secureContext, PSPLIM and LR from the current task stack. */
+    MSR     PSPLIM, R2
+    MOV     LR, R3
+    LDR     R2, =g_secureContext
+    STR     R0, [R2]                          /* Set the secureContext of the new task to g_secureContext. */
+    CBZ     R0, __RestoreNSContext            /* If there is no secure context for the new task, so restore from the non-secure context. */
+    PUSH    {R1, R3}
+    BL      HalSecureContextLoad              /* Restore the secure context. */
+    POP     {R1, R3}
+    MOV     LR, R3
+
+__RestoreNSContext:
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU3
+    VLDMIA  R1!, {D8-D15}
+
+__DisabledFPU3:
+    LDMFD   R1!, {R4-R12}
+    MSR     PSP,  R1
+
+    MSR     PRIMASK, R12
+    BX      LR
+    .fnend
+
+    .type HalSVCStartSchedule, %function
+    .global HalSVCStartSchedule
+HalSVCStartSchedule:
+    .fnstart
+    .cantunwind
+    LDR     R4, =OS_NVIC_SYSPRI2
+    LDR     R5, =OS_NVIC_PENDSV_PRI
+    STR     R5, [R4]
+    CPSIE   I
+    DSB
+    ISB
+    SVC     2
+    .fnend
+
+    .type HalSVCSecureContextAlloc, %function
+    .global HalSVCSecureContextAlloc
+HalSVCSecureContextAlloc:
+    .fnstart
+    .cantunwind
+    SVC     0
+    BX      LR
+    .fnend
+
+    .type HalSVCSecureContextFree, %function
+    .global HalSVCSecureContextFree
+HalSVCSecureContextFree:
+    .fnstart
+    .cantunwind
+    SVC     1
+    BX      LR
+    .fnend
+
+    .type HalSVCHandler, %function
+    .global HalSVCHandler
+HalSVCHandler:
+    .fnstart
+    .cantunwind
+    TST     LR, #0x04
+    ITE     EQ
+    MRSEQ   R1, MSP
+    MRSNE   R1, PSP
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]                     /* Get the SVC number. */
+
+    PUSH    {LR}
+    MOV     R2, R1                            /* Get the stack for R2. */
+    LDMFD   R2!, {R1}                         /* Get the input arg for HalSecureSVCHandler. */
+    STMFD   R2!, {R1}
+    BL      HalSecureSVCHandler
+    POP     {LR}
+    BX      LR
+    .fnend

arch/arm/cortex-m33/gcc/TZ/non_secure/los_exc.S

@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .syntax unified
+ .arch armv7e-m
+ .thumb
+.fpu fpv5-d16
+.section .text
+
+
+    .global  HalExcNMI
+    .global  HalExcHardFault
+    .global  HalExcMemFault
+    .global  HalExcBusFault
+    .global  HalExcUsageFault
+
+    .extern HalExcHandleEntry
+    .extern g_uwExcTbl
+    .extern g_taskScheduled
+
+.equ OS_FLG_BGD_ACTIVE,   0x0002
+
+.equ OS_EXC_CAUSE_NMI,   16
+.equ OS_EXC_CAUSE_HARDFAULT,   17
+
+.equ HF_DEBUGEVT,   20
+.equ HF_VECTBL,   21
+
+.equ FLAG_ADDR_VALID,   0x10000
+.equ FLAG_HWI_ACTIVE,   0x20000
+.equ FLAG_NO_FLOAT,   0x10000000
+
+.equ OS_NVIC_FSR                 ,   0xE000ED28      //include BusFault/MemFault/UsageFault State Register
+.equ OS_NVIC_HFSR                ,   0xE000ED2C      //HardFault State Register
+.equ OS_NVIC_BFAR                ,   0xE000ED38
+.equ OS_NVIC_MMAR                ,   0xE000ED34
+.equ OS_NVIC_ACT_BASE            ,   0xE000E300
+.equ OS_NVIC_SHCSRS              ,   0xE000ED24
+.equ OS_NVIC_SHCSR_MASK          ,   0xC00
+
+    .type HalExcNMI, %function
+    .global HalExcNMI
+HalExcNMI:
+    .fnstart
+    .cantunwind
+    MOV  R0, #OS_EXC_CAUSE_NMI
+    MOV  R1, #0
+    B  osExcDispatch
+    .fnend
+
+    .type HalExcHardFault, %function
+    .global HalExcHardFault
+HalExcHardFault:
+    .fnstart
+    .cantunwind
+    MOV  R0, #OS_EXC_CAUSE_HARDFAULT
+    LDR  R2, =OS_NVIC_HFSR
+    LDR  R2, [R2]
+
+    MOV  R1, #HF_DEBUGEVT
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x80000000
+    BNE  osExcDispatch     // DEBUGEVT
+
+    AND  R0, R0 , #0x000000FF
+    MOV  R1, #HF_VECTBL
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x00000002
+    BNE  osExcDispatch     // VECTBL
+
+    //if not DEBUGEVT and VECTBL then is FORCED
+    AND  R0, R0, #0x000000FF
+
+    LDR  R2, =OS_NVIC_FSR
+    LDR  R2, [R2]
+
+    TST  R2, #0x8000     // BFARVALID
+    BNE  _HFBusFault     // BusFault
+
+    TST  R2, #0x80       // MMARVALID
+    BNE  _HFMemFault     // MemFault
+
+    MOV  R12,#0
+    B    osHFExcCommonBMU
+    .fnend
+
+    .type _HFBusFault, %function
+
+_HFBusFault:
+    .fnstart
+    .cantunwind
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    B    osHFExcCommonBMU
+    .fnend
+
+    .type _HFMemFault, %function
+
+_HFMemFault:
+    .fnstart
+    .cantunwind
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    .fnend
+
+    .type osHFExcCommonBMU, %function
+    .global osHFExcCommonBMU
+osHFExcCommonBMU:
+    .fnstart
+    .cantunwind
+    CLZ  R2, R2
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R2
+    LDRB R2, [R3]
+    ORR  R0, R0, R2, LSL #0x8
+    ORR  R0, R0 ,R12
+    B    osExcDispatch
+    .fnend
+
+    .type HalExcBusFault, %function
+    .global HalExcBusFault
+HalExcBusFault:
+    .fnstart
+    .cantunwind
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x8000  // BFARVALID
+    BEQ  _ExcBusNoADDR
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1F00
+
+    B    osExcCommonBMU
+    .fnend
+
+    .type _ExcBusNoADDR, %function
+    .global _ExcBusNoADDR
+_ExcBusNoADDR:
+    .fnstart
+    .cantunwind
+    MOV  R12,#0
+    B    osExcCommonBMU
+    .fnend
+
+    .type HalExcMemFault, %function
+    .global HalExcMemFault
+HalExcMemFault:
+    .fnstart
+    .cantunwind
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x80 // MMARVALID
+    BEQ  _ExcMemNoADDR
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1B
+
+    B    osExcCommonBMU
+    .fnend
+
+    .type _ExcMemNoADDR, %function
+    .global _ExcMemNoADDR
+_ExcMemNoADDR:
+    .fnstart
+    .cantunwind
+    MOV  R12,#0
+    B    osExcCommonBMU
+    .fnend
+
+    .type HalExcUsageFault, %function
+    .global HalExcUsageFault
+HalExcUsageFault:
+    .fnstart
+    .cantunwind
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    MOVW  R1, #0x030F
+    LSL  R1, R1, #16
+    AND  R0, R0, R1
+    MOV  R12, #0
+
+    .fnend
+
+    .type osExcCommonBMU, %function
+    .global osExcCommonBMU
+osExcCommonBMU:
+    .fnstart
+    .cantunwind
+    CLZ  R0, R0
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R0
+    LDRB R0, [R3]
+    ORR  R0, R0, R12
+    .fnend
+// R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid),  R1 -- EXCADDR
+
+    .type osExcDispatch, %function
+    .global osExcDispatch
+osExcDispatch:
+    .fnstart
+    .cantunwind
+    LDR   R2, =OS_NVIC_ACT_BASE
+    MOV   R12, #8                       // R12 is hwi check loop counter
+    .fnend
+
+    .type _hwiActiveCheck, %function
+    .global _hwiActiveCheck
+_hwiActiveCheck:
+    .fnstart
+    .cantunwind
+    LDR   R3, [R2]                      // R3 store active hwi register when exc
+    CMP   R3, #0
+    BEQ   _hwiActiveCheckNext
+
+    // exc occured in IRQ
+    ORR   R0, R0, #FLAG_HWI_ACTIVE
+    RBIT  R2, R3
+    CLZ   R2, R2
+    AND   R12, R12, #1
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
+    .fnend
+
+    .type _ExcInMSP, %function
+    .global _ExcInMSP
+_ExcInMSP:
+    .fnstart
+    .cantunwind
+    CMP   LR, #0xFFFFFFE9
+    BNE   _NoFloatInMsp
+    ADD   R3, R13, #104
+    PUSH  {R3}
+    MRS   R12, PRIMASK                  // store message-->exc: disable int?
+    PUSH {R4-R12}                       // store message-->exc: {R4-R12}
+    VPUSH {D8-D15}
+    B     _handleEntry
+  .fnend
+
+    .type _NoFloatInMsp, %function
+    .global _NoFloatInMsp
+_NoFloatInMsp:
+    .fnstart
+    .cantunwind
+    ADD   R3, R13, #32
+    PUSH  {R3} // save IRQ SP            // store message-->exc: MSP(R13)
+
+    MRS   R12, PRIMASK                  // store message-->exc: disable int?
+    PUSH {R4-R12}                       // store message-->exc: {R4-R12}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+    B     _handleEntry
+  .fnend
+
+    .type _hwiActiveCheckNext, %function
+    .global _hwiActiveCheckNext
+_hwiActiveCheckNext:
+    .fnstart
+    .cantunwind
+    ADD   R2, R2, #4                        // next NVIC ACT ADDR
+    SUBS  R12, R12, #1
+    BNE   _hwiActiveCheck
+
+    /*NMI interrupt excption*/
+    LDR   R2, =OS_NVIC_SHCSRS
+    LDRH  R2,[R2]
+    LDR   R3,=OS_NVIC_SHCSR_MASK
+    AND   R2, R2,R3
+    CMP   R2,#0
+    BNE   _ExcInMSP
+    // exc occured in Task or Init or exc
+    // reserved for register info from task stack
+
+    LDR  R2, =g_taskScheduled
+    LDR  R2, [R2]
+    TST  R2, #1                         // OS_FLG_BGD_ACTIVE
+    BEQ  _ExcInMSP                      // if exc occured in Init then branch
+
+
+    CMP   LR, #0xFFFFFFED               //auto push floating registers
+    BNE   _NoFloatInPsp
+
+    // exc occured in Task
+    MOV   R2,  R13
+    SUB   R13, #96                      // add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #104
+    PUSH  {R12}                         // save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+    VPUSH {D8-D15}
+
+    // copy auto saved task register
+
+    LDMFD R3!, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
+    VLDMIA  R3!, {D8-D15}
+    VSTMDB  R2!, {D8-D15}
+    STMFD R2!, {R4-R11}
+    B     _handleEntry
+  .fnend
+
+    .type _NoFloatInPsp, %function
+    .global _NoFloatInPsp
+_NoFloatInPsp:
+    .fnstart
+    .cantunwind
+    MOV   R2,  R13                      // no auto push floating registers
+    SUB   R13, #32                      // add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #32
+    PUSH  {R12}                         // save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+
+    LDMFD R3, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
+    STMFD R2!, {R4-R11}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+  .fnend
+
+    .type _handleEntry, %function
+    .global _handleEntry
+_handleEntry:
+    .fnstart
+    .cantunwind
+    MOV R3, R13                         // R13:the 4th param
+    CPSID I
+    CPSID F
+    B  HalExcHandleEntry
+
+    NOP
+  .fnend
+

arch/arm/cortex-m33/gcc/TZ/non_secure/los_interrupt.c

@@ -0,0 +1,606 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "los_interrupt.h"
+#include <stdarg.h>
+#include "securec.h"
+#include "los_context.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+
+#define DEF_HANDLER_START_INDEX 2
+/*lint -save -e40 -e522 -e533*/
+UINT32 g_intCount = 0;
+
+/*lint -restore*/
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+    HWI_PROC_FUNC pfnHandler;
+    VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+    }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+    }
+}
+#endif
+
+/* ****************************************************************************
+ Function    : HwiNumGet
+ Description : Get an interrupt number
+ Input       : None
+ Output      : None
+ Return      : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+    return __get_IPSR();
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+    return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function    : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+/*lint -e529*/
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+    while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+    UINT32 hwiIndex;
+    UINT32 intSave;
+
+#if (LOSCFG_KERNEL_RUNSTOP == 1)
+    SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
+#endif
+
+    intSave = LOS_IntLock();
+    g_intCount++;
+    LOS_IntRestore(intSave);
+
+    hwiIndex = HwiNumGet();
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+
+    HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+        g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+    }
+#else
+    if (g_hwiHandlerForm[hwiIndex] != 0) {
+        g_hwiHandlerForm[hwiIndex]();
+    }
+#endif
+
+    HalAftInterruptHandler(hwiIndex);
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+    intSave = LOS_IntLock();
+    g_intCount--;
+    LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiCreate
+ Description : create hardware interrupt
+ Input       : hwiNum   --- hwi num to create
+               hwiPrio  --- priority of the hwi
+               hwiMode  --- unused
+               hwiHandler --- hwi handler
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T hwiMode,
+                                           HWI_PROC_FUNC hwiHandler,
+                                           HwiIrqParam *irqParam)
+{
+    (VOID)hwiMode;
+    UINT32 intSave;
+
+    if (hwiHandler == NULL) {
+        return OS_ERRNO_HWI_PROC_FUNC_NULL;
+    }
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return OS_ERRNO_HWI_ALREADY_CREATED;
+    }
+
+    if (hwiPrio > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (irqParam != NULL) {
+        OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+    } else {
+        OsSetVector(hwiNum, hwiHandler, NULL);
+    }
+#else
+    (VOID)irqParam;
+    OsSetVector(hwiNum, hwiHandler);
+#endif
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input       : hwiNum   --- hwi num to delete
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+    (VOID)irqParam;
+    UINT32 intSave;
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    intSave = LOS_IntLock();
+
+    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+#define FAULT_STATUS_REG_BIT            32
+#define USGFAULT                        (1 << 18)
+#define BUSFAULT                        (1 << 17)
+#define MEMFAULT                        (1 << 16)
+#define DIV0FAULT                       (1 << 4)
+#define UNALIGNFAULT                    (1 << 3)
+#define HARDFAULT_IRQN                  (-13)
+
+ExcInfo g_excInfo = {0};
+
+UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
+    0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
+    0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
+    0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
+    0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
+};
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcNvicDump(VOID)
+{
+#define OS_NR_NVIC_EXC_DUMP_TYPES   7
+    UINT32 *base = NULL;
+    UINT32 len, i, j;
+    UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
+        OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
+    };
+    UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
+        OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
+        OS_NVIC_INT_CTRL_SIZE
+    };
+    CHAR strRgEnable[] = "enable";
+    CHAR strRgPending[] = "pending";
+    CHAR strRgActive[] = "active";
+    CHAR strRgPriority[] = "priority";
+    CHAR strRgException[] = "exception";
+    CHAR strRgShcsr[] = "shcsr";
+    CHAR strRgIntCtrl[] = "control";
+    CHAR *strRgs[] = {
+        strRgEnable, strRgPending, strRgActive, strRgPriority,
+        strRgException, strRgShcsr, strRgIntCtrl
+    };
+
+    PRINTK("\r\nOS exception NVIC dump:\n");
+    for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
+        base = (UINT32 *)rgNvicBases[i];
+        len = rgNvicLens[i];
+        PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
+        len = (len >> 2); /* 2: Gets the next register offset */
+        for (j = 0; j < len; j++) {
+            PRINTK("0x%x ", *(base + j));
+            if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
+                PRINTK("\n");
+            }
+        }
+        PRINTK("\n");
+    }
+}
+
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+    CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+    PRINTK("Type      = %d\n", excInfo->type);
+    PRINTK("ThrdPid   = %d\n", excInfo->thrdPid);
+    PRINTK("Phase     = %s\n", phaseStr[excInfo->phase]);
+    PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Current task info:\n");
+    if (excInfo->phase == OS_EXC_IN_TASK) {
+        LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+        PRINTK("Task name = %s\n", taskCB->taskName);
+        PRINTK("Task ID   = %d\n", taskCB->taskID);
+        PRINTK("Task SP   = %p\n", taskCB->stackPointer);
+        PRINTK("Task ST   = 0x%x\n", taskCB->topOfStack);
+        PRINTK("Task SS   = 0x%x\n", taskCB->stackSize);
+    } else if (excInfo->phase == OS_EXC_IN_HWI) {
+        PRINTK("Exception occur in interrupt phase!\n");
+    } else {
+        PRINTK("Exception occur in system init phase!\n");
+    }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Exception reg dump:\n");
+    PRINTK("PC        = 0x%x\n", excInfo->context->uwPC);
+    PRINTK("LR        = 0x%x\n", excInfo->context->uwLR);
+    PRINTK("SP        = 0x%x\n", excInfo->context->uwSP);
+    PRINTK("R0        = 0x%x\n", excInfo->context->uwR0);
+    PRINTK("R1        = 0x%x\n", excInfo->context->uwR1);
+    PRINTK("R2        = 0x%x\n", excInfo->context->uwR2);
+    PRINTK("R3        = 0x%x\n", excInfo->context->uwR3);
+    PRINTK("R4        = 0x%x\n", excInfo->context->uwR4);
+    PRINTK("R5        = 0x%x\n", excInfo->context->uwR5);
+    PRINTK("R6        = 0x%x\n", excInfo->context->uwR6);
+    PRINTK("R7        = 0x%x\n", excInfo->context->uwR7);
+    PRINTK("R8        = 0x%x\n", excInfo->context->uwR8);
+    PRINTK("R9        = 0x%x\n", excInfo->context->uwR9);
+    PRINTK("R10       = 0x%x\n", excInfo->context->uwR10);
+    PRINTK("R11       = 0x%x\n", excInfo->context->uwR11);
+    PRINTK("R12       = 0x%x\n", excInfo->context->uwR12);
+    PRINTK("PriMask   = 0x%x\n", excInfo->context->uwPriMask);
+    PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+    UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+    UINT32 index;
+
+    OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
+
+    PRINTK("----- backtrace start -----\n");
+    for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+        if (LR[index] == 0) {
+            break;
+        }
+        PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
+    }
+    PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+    PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+    MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+    UINT32 errCnt;
+    UINT32 i;
+
+    (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+    errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+    if (errCnt < OS_SYS_MEM_NUM) {
+        errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+    }
+
+    if (errCnt == 0) {
+        PRINTK("all memory pool check passed!\n");
+        return;
+    }
+
+    for (i = 0; i < errCnt; i++) {
+        PRINTK("pool num    = %d\n", i);
+        PRINTK("pool type   = %d\n", memExcInfo[i].type);
+        PRINTK("pool addr   = 0x%x\n", memExcInfo[i].startAddr);
+        PRINTK("pool size   = 0x%x\n", memExcInfo[i].size);
+        PRINTK("pool free   = 0x%x\n", memExcInfo[i].free);
+        PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
+        PRINTK("pool error node addr  = 0x%x\n", memExcInfo[i].errorAddr);
+        PRINTK("pool error node len   = 0x%x\n", memExcInfo[i].errorLen);
+        PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
+    }
+#endif
+    UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+    if (ret == LOS_OK) {
+        PRINTK("system heap memcheck over, all passed!\n");
+    }
+
+    PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+    PRINTK("*************Exception Information**************\n");
+    OsExcTypeInfo(excInfo);
+    OsExcCurTaskInfo(excInfo);
+    OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+    OsExcBackTraceInfo(excInfo);
+#endif
+    OsGetAllTskInfo();
+    OsExcNvicDump();
+    OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+    UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
+    g_intCount++;
+    g_excInfo.nestCnt++;
+
+    g_excInfo.type = excType & OS_NULL_SHORT;
+
+    if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
+        g_excInfo.faultAddr = faultAddr;
+    } else {
+        g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+    }
+    if (g_losTask.runTask != NULL) {
+        if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
+            g_excInfo.phase = OS_EXC_IN_HWI;
+            g_excInfo.thrdPid = pid;
+        } else {
+            g_excInfo.phase = OS_EXC_IN_TASK;
+            g_excInfo.thrdPid = g_losTask.runTask->taskID;
+        }
+    } else {
+        g_excInfo.phase = OS_EXC_IN_INIT;
+        g_excInfo.thrdPid = OS_NULL_INT;
+    }
+    if (excType & OS_EXC_FLAG_NO_FLOAT) {
+        g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
+    } else {
+        g_excInfo.context = excBufAddr;
+    }
+
+    OsDoExcHook(EXC_INTERRUPT);
+    OsExcInfoDisplay(&g_excInfo);
+    ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function    : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    UINT32 index;
+    g_hwiForm[0] = 0; /* [0] Top of Stack */
+    g_hwiForm[1] = 0; /* [1] reset */
+    for (index = DEF_HANDLER_START_INDEX; index < OS_VECTOR_CNT; index++) {
+        g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+    }
+    /* Exception handler register */
+    g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT]   = HalExcNMI;
+    g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT]        = HalExcHardFault;
+    g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = HalExcMemFault;
+    g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT]         = HalExcBusFault;
+    g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT]       = HalExcUsageFault;
+    g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT]           = HalSVCHandler;
+    g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT]           = HalPendSV;
+    g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT]          = OsTickHandler;
+
+    /* Interrupt vector table location */
+    SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
+#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
+    NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
+#endif
+
+    /* Enable USGFAULT, BUSFAULT, MEMFAULT */
+    *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+	
+    /* Enable DIV 0 and unaligned exception */
+#ifdef LOSCFG_ARCH_UNALIGNED_EXC
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
+#else
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
+#endif
+
+    return;
+}
+

arch/arm/cortex-m33/gcc/TZ/non_secure/los_timer.c

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "los_tick.h"
+#include "los_arch_interrupt.h"
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+    UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
+
+    tick->freq = OS_SYS_CLOCK;
+
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
+#else
+    OsSetVector(tick->irqNum, handler);
+#endif
+#endif
+
+    ret = SysTick_Config(g_cyclesPerTick);
+    if (ret == 1) {
+        return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
+    }
+
+    return LOS_OK;
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+    if (nextResponseTime > g_archTickTimer.periodMax) {
+        nextResponseTime = g_archTickTimer.periodMax;
+    }
+
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
+    SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+    UINT32 hwCycle = 0；
+    UINT32 intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
+    *period = SysTick->LOAD;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
+    LOS_IntRestore(intSave);
+    return (UINT64)hwCycle;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return LOS_OK;
+}

arch/arm/cortex-m33/gcc/TZ/non_secure/los_trustzone.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_trustzone.h"
+#include "los_secure_macros.h"
+#include "los_secure_context.h"
+#include "los_debug.h"
+#include "los_arch_context.h"
+#include "los_interrupt.h"
+
+OsSecureContext *g_secureContext = NULL;
+
+VOID HalSecureSVCHandler(UINT32 svcID, UINTPTR arg)
+{
+    switch (svcID) {
+        case OS_SVC_START_SCHEDULE:
+            HalSecureContextInit();
+            HalStartFirstTask();
+            break;
+        case OS_SVC_ALLOCATE_SECURE_CONTEXT:
+            g_secureContext = HalSecureContextAlloc(arg);
+            LOS_ASSERT(g_secureContext != NULL);
+            HalSecureContextLoad(g_secureContext);
+            break;
+        case OS_SVC_FREE_SECURE_CONTEXT:
+            HalSecureContextFree(g_secureContext);
+            break;
+        default:
+            PRINT_ERR("Incorrect svc id = %u\n", svcID);
+            break;
+    }
+}
+
+VOID HalStartToRun(VOID)
+{
+    HalSVCStartSchedule();
+}
+
+VOID LOS_SecureContextAlloc(UINT32 secureStackSize)
+{
+    if (secureStackSize == 0) {
+        return;
+    }
+
+    LOS_ASSERT((__get_IPSR() == 0) && (__get_PRIMASK() == 0));
+    secureStackSize = LOS_Align(secureStackSize, sizeof(UINTPTR));
+    HalSVCSecureContextAlloc(secureStackSize);
+}
+
+VOID LOS_SecureContextFree(VOID)
+{
+    HalSVCSecureContextFree();
+}
+

arch/arm/cortex-m33/gcc/TZ/non_secure/los_trustzone.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_TRUSTZONE_H
+#define _LOS_TRUSTZONE_H
+
+#include "los_config.h"
+#include "los_task.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+extern VOID LOS_SecureContextAlloc(UINT32 secureStackSize);
+extern VOID LOS_SecureContextFree(VOID);
+
+extern VOID HalStartFirstTask(VOID);
+extern VOID HalSVCStartSchedule(VOID);
+extern VOID HalSVCSecureContextAlloc(UINT32 secureStackSize);
+extern VOID HalSVCSecureContextFree(VOID);
+extern VOID HalSVCHandler(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
+

arch/arm/cortex-m33/gcc/TZ/secure/los_secure_context.c

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_secure_context.h"
+#include "los_secure_macros.h"
+#include "los_secure_heap.h"
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextInit(VOID)
+{
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return;
+    }
+
+    HalSecureContextInitAsm();
+}
+
+OS_CMSE_NS_ENTRY OsSecureContext *HalSecureContextAlloc(UINT32 size)
+{
+    OsSecureContext *secureContext = NULL;
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return NULL;
+    }
+
+    secureContext = HalSecureMalloc(sizeof(OsSecureContext));
+    if (secureContext == NULL) {
+        return NULL;
+    }
+
+    secureContext->stackLimit = HalSecureMalloc(size);
+    if (secureContext->stackLimit == NULL) {
+        HalSecureFree(secureContext);
+        return NULL;
+    }
+
+    secureContext->stackStart = secureContext->stackLimit + size;
+    secureContext->curStackPointer = secureContext->stackStart;
+
+    return secureContext;
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextFree(OsSecureContext *secureContext)
+{
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return;
+    }
+
+    HalSecureFree(secureContext->stackLimit);
+    secureContext->stackLimit = NULL;
+    HalSecureFree(secureContext);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextLoad(OsSecureContext *secureContext)
+{
+    HalSecureContextLoadAsm(secureContext);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextSave(OsSecureContext *secureContext)
+{
+    HalSecureContextSaveAsm(secureContext);
+}
+

arch/arm/cortex-m33/gcc/TZ/secure/los_secure_context.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_SECURE_CONTEXT_H
+#define _LOS_SECURE_CONTEXT_H
+
+#include "los_config.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct {
+    UINT8 *curStackPointer;
+    UINT8 *stackLimit;
+    UINT8 *stackStart;
+} OsSecureContext;
+
+extern VOID HalSecureContextInit(VOID);
+extern OsSecureContext *HalSecureContextAlloc(UINT32 size);
+extern VOID HalSecureContextFree(OsSecureContext *secureContext);
+extern VOID HalSecureContextLoad(OsSecureContext *secureContext);
+extern VOID HalSecureContextSave(OsSecureContext *secureContext);
+
+extern VOID HalSecureContextInitAsm(VOID);
+extern VOID HalSecureContextLoadAsm(OsSecureContext *secureContext);
+extern VOID HalSecureContextSaveAsm(OsSecureContext *secureContext);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif

arch/arm/cortex-m33/gcc/TZ/secure/los_secure_context_asm.S

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .syntax unified
+ .arch armv7e-m
+ .thumb
+ .fpu fpv5-d16
+
+.equ OS_SECURE_SCB_AIRCR,    0xE000ED0C
+
+    .section .text
+    .thumb
+
+    .type HalSecureContextInitAsm, %function
+    .global HalSecureContextInitAsm
+HalSecureContextInitAsm:
+    .fnstart
+    .cantunwind
+    LDR     R0, =OS_SECURE_SCB_AIRCR
+    LDR     R1, [R0]
+
+    MOV     R2, #0xFFFF
+    LSL     R2, R2, #16
+    BIC     R1, R1, R2
+    MOV     R2, #0x05FA
+    LSL     R2, R2, #16
+    ORR     R1, R1, R2
+
+    BIC     R1, R1, #0x4000
+    MOV     R2, #0x4000
+    ORR     R1, R1, R2
+    STR     R1, [R0]
+
+    MOV     R0, #0
+    MSR     PSPLIM, R0
+    MSR     PSP, R0
+    MOV     R0, #2
+    MSR     CONTROL, R0 
+    BX      LR
+    .fnend
+
+    .type HalSecureContextLoadAsm, %function
+    .global HalSecureContextLoadAsm
+HalSecureContextLoadAsm:
+    .fnstart
+    .cantunwind
+    MRS     R1, IPSR
+    CBZ     R1, __ThreadMode
+
+    LDMIA   R0!, {R1, R2}               /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext->stackLimit. */
+    MSR     PSPLIM, R2                  /* Restore PSPLIM. */
+    MSR     PSP, R1                     /* Restore PSP. */
+    BX      LR
+    .fnend
+    
+    .type HalSecureContextSaveAsm, %function
+    .global HalSecureContextSaveAsm
+HalSecureContextSaveAsm:
+    .fnstart
+    .cantunwind
+    MRS     R0, IPSR
+    CBZ     R0, __ThreadMode
+
+    MRS     R0, PSP
+    STR     R0, [R1]                    /* g_secureContext->curStackPointer = R0. */
+    MOV     R0, #0
+    MSR     PSPLIM, R0                  /* No PSPLIM for the current task. */
+    MSR     PSP, R0                     /* No secure stack for the current task. */
+    .fnend
+
+__ThreadMode:
+    BX      LR

arch/arm/cortex-m33/gcc/TZ/secure/los_secure_heap.c

@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_secure_heap.h"
+#include "los_secure_macros.h"
+#include "los_config.h"
+#include "los_list.h"
+
+STATIC UINT8 __attribute__((aligned(0x4)))g_secureHeap[LOSCFG_SECURE_HEAP_SIZE] = {0};
+STATIC LOS_DL_LIST g_secureHeapFreeList = {NULL, NULL};
+
+struct OsSecureHeapNode {
+    LOS_DL_LIST freeNode;
+    struct OsSecureHeapNode *preNode;
+    UINT32 size : 24;
+    UINT32 used : 8;
+};
+
+#define OS_SECURE_HEAP_NODE_HEAD_SIZE   sizeof(struct OsSecureHeapNode)
+#define OS_SECURE_HEAP_ALIGN_SIZE       sizeof(UINTPTR)
+
+#define OS_SECURE_HEAP_NODE_USED        1
+#define OS_SECURE_HEAP_NODE_FREE        0
+
+#define OS_SECURE_HEAP_FIRST_NODE     ((struct OsSecureHeapNode *)g_secureHeap)
+#define OS_SECURE_HEAP_NEXT_NODE(node) \
+    ((struct OsSecureHeapNode *)((UINT8 *)(node) + (node)->size))
+#define OS_SECURE_HEAP_END_NODE \
+    ((struct OsSecureHeapNode *)((UINT8 *)g_secureHeap + LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE))
+
+STATIC INLINE VOID OsSecureHeapListInit(LOS_DL_LIST *head)
+{
+    head->pstPrev = head;
+    head->pstNext = head;
+}
+
+STATIC INLINE VOID OsSecureHeapListDelete(LOS_DL_LIST *node)
+{
+    node->pstNext->pstPrev = node->pstPrev;
+    node->pstPrev->pstNext = node->pstNext;
+    node->pstNext = NULL;
+    node->pstPrev = NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapListAdd(LOS_DL_LIST *listNode, LOS_DL_LIST *node)
+{
+    node->pstNext = listNode->pstNext;
+    node->pstPrev = listNode;
+    listNode->pstNext->pstPrev = node;
+    listNode->pstNext = node;
+}
+
+STATIC struct OsSecureHeapNode *OsSecureHeapFindSuitableFreeBlock(UINT32 allocSize)
+{
+    LOS_DL_LIST *listNodeHead = &g_secureHeapFreeList;
+    struct OsSecureHeapNode *tmpNode = NULL;
+
+    LOS_DL_LIST_FOR_EACH_ENTRY(tmpNode, listNodeHead, struct OsSecureHeapNode, freeNode) {
+        if (tmpNode->size >= allocSize) {
+            return tmpNode;
+        }
+    }
+
+    return NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapClearNode(struct OsSecureHeapNode *node)
+{
+    node->preNode = NULL;
+    node->size = 0;
+    node->used = 0;
+    node->freeNode.pstPrev = NULL;
+    node->freeNode.pstNext = NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapMergeNode(struct OsSecureHeapNode *node)
+{
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    node->preNode->size += node->size;
+    nextNode = (struct OsSecureHeapNode *)((UINTPTR)node + node->size);
+    nextNode->preNode = node->preNode;
+    OsSecureHeapClearNode(node);
+}
+
+STATIC INLINE VOID OsSecureHeapSplitNode(struct OsSecureHeapNode *allocNode, UINT32 allocSize)
+{
+    struct OsSecureHeapNode *newFreeNode = NULL;
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    newFreeNode = (struct OsSecureHeapNode *)((UINT8 *)allocNode + allocSize);
+    newFreeNode->preNode = allocNode;
+    newFreeNode->size = allocNode->size - allocSize;
+    newFreeNode->used = OS_SECURE_HEAP_NODE_FREE;
+    allocNode->size = allocSize;
+    nextNode = OS_SECURE_HEAP_NEXT_NODE(newFreeNode);
+    nextNode->preNode = newFreeNode;
+    if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+        OsSecureHeapListDelete(&nextNode->freeNode);
+        OsSecureHeapMergeNode(nextNode);
+    }
+
+    OsSecureHeapListAdd(&g_secureHeapFreeList, &newFreeNode->freeNode);
+}
+
+STATIC INLINE VOID OsSecureHeapFreeNode(struct OsSecureHeapNode *node)
+{
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    if ((node->preNode != NULL) && (node->preNode->used == OS_SECURE_HEAP_NODE_FREE)) {
+        struct OsSecureHeapNode *preNode = node->preNode;
+        OsSecureHeapMergeNode(node);
+        nextNode = OS_SECURE_HEAP_NEXT_NODE(preNode);
+        if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+            OsSecureHeapListDelete(&nextNode->freeNode);
+            OsSecureHeapMergeNode(nextNode);
+        }
+
+        OsSecureHeapListDelete(&preNode->freeNode);
+        preNode->used = OS_SECURE_HEAP_NODE_FREE;
+        OsSecureHeapListAdd(&g_secureHeapFreeList, &preNode->freeNode);
+    } else {
+        nextNode = OS_SECURE_HEAP_NEXT_NODE(node);
+        if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+            OsSecureHeapListDelete(&nextNode->freeNode);
+            OsSecureHeapMergeNode(nextNode);
+        }
+
+        node->used = OS_SECURE_HEAP_NODE_FREE;
+        OsSecureHeapListAdd(&g_secureHeapFreeList, &node->freeNode);
+    }
+}
+
+STATIC INLINE VOID *OsSecureHeapAllocNode(UINT32 size)
+{
+    struct OsSecureHeapNode *allocNode = NULL;
+    UINT32 allocSize;
+
+    allocSize = LOS_Align(size + OS_SECURE_HEAP_NODE_HEAD_SIZE, OS_SECURE_HEAP_ALIGN_SIZE);
+    allocNode = OsSecureHeapFindSuitableFreeBlock(allocSize);
+    if (allocNode == NULL) {
+        return NULL;
+    }
+    if ((allocSize + OS_SECURE_HEAP_NODE_HEAD_SIZE + OS_SECURE_HEAP_ALIGN_SIZE) <= allocNode->size) {
+        OsSecureHeapSplitNode(allocNode, allocSize);
+    }
+    OsSecureHeapListDelete(&allocNode->freeNode);
+    allocNode->used = OS_SECURE_HEAP_NODE_USED;
+
+    return (allocNode + 1);
+}
+
+STATIC INLINE VOID OsSecureHeapInit(VOID)
+{
+    struct OsSecureHeapNode *newNode = NULL;
+    struct OsSecureHeapNode *endNode = NULL;
+
+    newNode = OS_SECURE_HEAP_FIRST_NODE;
+    newNode->size = LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE;
+    newNode->preNode = OS_SECURE_HEAP_END_NODE;
+    newNode->used = OS_SECURE_HEAP_NODE_FREE;
+
+    OsSecureHeapListInit(&g_secureHeapFreeList);
+    OsSecureHeapListAdd(&g_secureHeapFreeList, &newNode->freeNode);
+
+    endNode = OS_SECURE_HEAP_END_NODE;
+    endNode->preNode = newNode;
+    endNode->size = OS_SECURE_HEAP_NODE_HEAD_SIZE;
+    endNode->used = OS_SECURE_HEAP_NODE_USED;
+}
+
+OS_CMSE_NS_ENTRY VOID *HalSecureMalloc(UINT32 size)
+{
+    if (size == 0) {
+        return NULL;
+    }
+
+    if ((g_secureHeapFreeList.pstPrev == NULL) &&
+        (g_secureHeapFreeList.pstNext == NULL)) {
+        OsSecureHeapInit();
+    }
+
+    return OsSecureHeapAllocNode(size);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureFree(VOID *ptr)
+{
+    struct OsSecureHeapNode *node = NULL;
+
+    if (ptr == NULL) {
+        return;
+    }
+
+    node = (struct OsSecureHeapNode *)((UINTPTR)ptr - OS_SECURE_HEAP_NODE_HEAD_SIZE);
+    if (node->used != OS_SECURE_HEAP_NODE_USED) {
+        return;
+    }
+
+    OsSecureHeapFreeNode(node);
+}
+

arch/arm/cortex-m33/gcc/TZ/secure/los_secure_heap.h

@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -29,10 +29,10 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _LOS_PRINTF_PRI_H
-#define _LOS_PRINTF_PRI_H
+#ifndef _LOS_SECURE_HEAP_H
+#define _LOS_SECURE_HEAP_H
 
-#include "los_printf.h"
+#include "los_config.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -40,10 +40,8 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-
-VOID _dprintf(const CHAR *fmt, va_list ap);
-INT32 __dprintf(const CHAR *fmt, va_list ap, VOID (*uart_fputc)(UINT32 n, VOID *cookie), CHAR *cookie);
-
+VOID *HalSecureMalloc(UINT32 size);
+VOID HalSecureFree(VOID *ptr);
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -51,4 +49,5 @@ INT32 __dprintf(const CHAR *fmt, va_list ap, VOID (*uart_fputc)(UINT32 n, VOID *
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-#endif /* _LOS_PRINTF_PRI_H */
+#endif
+

arch/arm/cortex-m33/gcc/TZ/secure/los_secure_macros.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_SECURE_MACROS_H
+#define _LOS_SECURE_MACROS_H
+
+#include "los_config.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#define OS_CMSE_NS_ENTRY      __attribute__((cmse_nonsecure_entry))
+#define OS_CMSE_NS_CALL       __attribute__((cmse_nonsecure_call))
+#define OS_IPSR_READ(ipsr)    __asm volatile("MRS %0, IPSR" : "=r" (ipsr))
+
+#define OS_SVC_ALLOCATE_SECURE_CONTEXT  0
+#define OS_SVC_FREE_SECURE_CONTEXT      1
+#define OS_SVC_START_SCHEDULE           2
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
+

arch/arm/cortex-m33/iar/NTZ/los_arch_atomic.h

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    asm volatile("ldrex %0, [%1]\n"
+                 : "=&r"(val)
+                 : "r"(v)
+                 : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %0, [%1]\n"
+                     "strex %0, %2, [%1]\n"
+                     : "=&r"(status)
+                     : "r"(v), "r"(setVal)
+                     : "cc");
+    } while (status != 0);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "add %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(addVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "sub %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(subVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        asm volatile("ldrex %0, [%2]\n"
+                     "strex %1, %3, [%2]"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        asm volatile("ldrex %0, [%2]\n"
+                     "mov %1, #0\n"
+                     "cmp %0, %3\n"
+                     "bne 1f\n"
+                     "strex %1, %4, [%2]\n"
+                     "1:"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(oldVal), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/arm/cortex-m33/iar/NTZ/los_arch_context.h

@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct TagTskContext {
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} TaskContext;
+
+/**
+ * @ingroup  los_config
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */
+

arch/arm/cortex-m33/iar/NTZ/los_arch_interrupt.h

@@ -0,0 +1,684 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_EXC_H
+#define _LOS_EXC_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_hwi
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_hwi
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST                   0
+#endif
+
+/* *
+ * @ingroup los_hwi
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST                    7
+#endif
+
+
+/* *
+ * @ingroup  los_hwi
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_hwi
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_hwi
+ * Count of M-Core system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT                     16
+
+/* *
+ * @ingroup los_hwi
+ * Count of M-Core interrupt vector.
+ */
+#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_hwi
+ * AIRCR register priority group parameter .
+ */
+#define OS_NVIC_AIRCR_PRIGROUP                7
+
+/* *
+ * @ingroup los_hwi
+ * Boot interrupt vector table.
+ */
+extern UINT32 _BootVectors[];
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+/* *
+ * @ingroup los_hwi
+ * SysTick control and status register.
+ */
+#define OS_SYSTICK_CONTROL_REG                0xE000E010
+
+/* *
+ * @ingroup los_hw
+ * SysTick current value register.
+ */
+#define OS_SYSTICK_CURRENT_REG                0xE000E018
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt Priority-Level Registers.
+ */
+#define OS_NVIC_PRI_BASE                      0xE000E400
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt enable register for 0-31.
+ */
+#define OS_NVIC_SETENA_BASE                   0xE000E100
+
+/* *
+ * @ingroup los_hwi
+ * interrupt pending register.
+ */
+#define OS_NVIC_SETPEND_BASE                  0xE000E200
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt active register.
+ */
+#define OS_NVIC_INT_ACT_BASE                  0xE000E300
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt disable register for 0-31.
+ */
+#define OS_NVIC_CLRENA_BASE                   0xE000E180
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt control and status register.
+ */
+#define OS_NVIC_INT_CTRL                      0xE000ED04
+
+/* *
+ * @ingroup los_hwi
+ * Vector table offset register.
+ */
+#define OS_NVIC_VTOR                          0xE000ED08
+
+/* *
+ * @ingroup los_hwi
+ * Application interrupt and reset control register
+ */
+#define OS_NVIC_AIRCR                         0xE000ED0C
+
+/* *
+ * @ingroup los_hwi
+ * System exception priority register.
+ */
+#define OS_NVIC_EXCPRI_BASE                   0xE000ED18
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 1 :reset.
+ */
+#define OS_EXC_RESET                          1
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 2 :Non-Maskable Interrupt.
+ */
+#define OS_EXC_NMI                            2
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 3 :(hard)fault.
+ */
+#define OS_EXC_HARD_FAULT                     3
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 4 :MemManage fault.
+ */
+#define OS_EXC_MPU_FAULT                      4
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 5 :Bus fault.
+ */
+#define OS_EXC_BUS_FAULT                      5
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 6 :Usage fault.
+ */
+#define OS_EXC_USAGE_FAULT                    6
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 11 :SVCall.
+ */
+#define OS_EXC_SVC_CALL                       11
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 12 :Debug monitor.
+ */
+#define OS_EXC_DBG_MONITOR                    12
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 14 :PendSV.
+ */
+#define OS_EXC_PEND_SV                        14
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 15 :SysTick.
+ */
+#define OS_EXC_SYS_TICK                       15
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li
+></ul>
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Reset the vector table.
+ *
+ * @par Description:
+ * This API is used to reset the vector table.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID Reset_Handler(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Pended System Call.
+ *
+ * @par Description:
+ * PendSV can be pended and is useful for an OS to pend an exception
+ * so that an action can be performed after other important tasks are completed.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalPendSV(VOID);
+
+
+#define OS_EXC_IN_INIT                      0
+#define OS_EXC_IN_TASK                      1
+#define OS_EXC_IN_HWI                       2
+
+#define OS_EXC_MAX_BUF_LEN                  25
+#define OS_EXC_MAX_NEST_DEPTH               1
+
+#define OS_NVIC_SHCSR                       0xE000ED24
+#define OS_NVIC_CCR                         0xE000ED14
+
+#define OS_NVIC_INT_ENABLE_SIZE             0x20
+#define OS_NVIC_INT_PRI_SIZE                0xF0
+#define OS_NVIC_EXCPRI_SIZE                 0xC
+#define OS_NVIC_INT_CTRL_SIZE               4
+#define OS_NVIC_SHCSR_SIZE                  4
+
+#define OS_NVIC_INT_PEND_SIZE               OS_NVIC_INT_ACT_SIZE
+#define OS_NVIC_INT_ACT_SIZE                OS_NVIC_INT_ENABLE_SIZE
+
+#define OS_EXC_FLAG_NO_FLOAT                0x10000000
+#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
+#define OS_EXC_FLAG_IN_HWI                  0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
+
+#define OS_EXC_EVENT                        0x00000001
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
+ */
+typedef struct TagExcContext {
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    /* auto save */
+    UINT32 uwSP;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED) && (__FPU_USED== 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+}EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+
+VOID HalExcNMI(VOID);
+VOID HalExcHardFault(VOID);
+VOID HalExcMemFault(VOID);
+VOID HalExcBusFault(VOID);
+VOID HalExcUsageFault(VOID);
+VOID HalSVCHandler(VOID);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was being pushed.
+ */
+#define OS_EXC_BF_STKERR           1
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was out of the stack.
+ */
+#define OS_EXC_BF_UNSTKERR         2
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register imprecise data access violation.
+ */
+#define OS_EXC_BF_IMPRECISERR      3
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register exact data access violation.
+ */
+#define OS_EXC_BF_PRECISERR        4
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register access violation while pointing.
+ */
+#define OS_EXC_BF_IBUSERR          5
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was being pushed.
+ */
+#define OS_EXC_MF_MSTKERR          6
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
+ */
+#define OS_EXC_MF_MUNSTKERR        7
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register data access violation.
+ */
+#define OS_EXC_MF_DACCVIOL         8
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register access violation.
+ */
+#define OS_EXC_MF_IACCVIOL         9
+
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
+ */
+#define OS_EXC_UF_DIVBYZERO        10
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error, error caused by unaligned access.
+ */
+#define OS_EXC_UF_UNALIGNED        11
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
+ */
+#define OS_EXC_UF_NOCP             12
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
+ */
+#define OS_EXC_UF_INVPC            13
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
+ */
+#define OS_EXC_UF_INVSTATE         14
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
+ */
+#define OS_EXC_UF_UNDEFINSTR       15
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: NMI
+ */
+
+#define OS_EXC_CAUSE_NMI           16
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: hard fault
+ */
+#define OS_EXC_CAUSE_HARDFAULT     17
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: The task handler exits.
+ */
+#define OS_EXC_CAUSE_TASK_EXIT     18
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A fatal error.
+ */
+#define OS_EXC_CAUSE_FATAL_ERR     19
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Hard Fault caused by a debug event.
+ */
+#define OS_EXC_CAUSE_DEBUGEVT      20
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
+ */
+#define OS_EXC_CAUSE_VECTBL        21
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
+ *
+ */
+typedef struct TagExcInfo {
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    UINT16 phase;
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
+    UINT16 type;
+    /**< If the exact address access error indicates the wrong access address when the exception occurred */
+    UINT32 faultAddr;
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    UINT32 thrdPid;
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
+    UINT16 nestCnt;
+    /**< reserve */
+    UINT16 reserved;
+    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+    EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_curNestCount;
+extern UINT32 g_intCount;
+extern UINT8 g_uwExcTbl[32];
+extern ExcInfo g_excInfo;
+
+#define MAX_INT_INFO_SIZE       (8 + 0x164)
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_EXC_H */

arch/arm/cortex-m33/iar/NTZ/los_arch_timer.h

@@ -1,52 +1,52 @@
-/*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _LOS_EVENT_PRI_H
-#define _LOS_EVENT_PRI_H
-
-#include "los_event.h"
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-extern UINT32 OsEventReadOnce(PEVENT_CB_S eventCB, UINT32 eventMask, UINT32 mode, UINT32 timeOut);
-extern UINT32 OsEventWriteOnce(PEVENT_CB_S eventCB, UINT32 events);
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-#endif /* _LOS_EVENT_PRI_H */
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */
+

arch/arm/cortex-m33/iar/NTZ/los_context.c

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
+
+/* ****************************************************************************
+ Function    : ArchInit
+ Description : arch init function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+    HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function    : ArchSysExit
+ Description : Task exit function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+    LOS_IntLock();
+    while (1) {
+    }
+}
+
+/* ****************************************************************************
+ Function    : ArchTskStackInit
+ Description : Task stack initialization function
+ Input       : taskID     --- TaskID
+               stackSize  --- Total size of the stack
+               topStack    --- Top of task's stack
+ Output      : None
+ Return      : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
+
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    context->S16 = 0xAA000010;
+    context->S17 = 0xAA000011;
+    context->S18 = 0xAA000012;
+    context->S19 = 0xAA000013;
+    context->S20 = 0xAA000014;
+    context->S21 = 0xAA000015;
+    context->S22 = 0xAA000016;
+    context->S23 = 0xAA000017;
+    context->S24 = 0xAA000018;
+    context->S25 = 0xAA000019;
+    context->S26 = 0xAA00001A;
+    context->S27 = 0xAA00001B;
+    context->S28 = 0xAA00001C;
+    context->S29 = 0xAA00001D;
+    context->S30 = 0xAA00001E;
+    context->S31 = 0xAA00001F;
+    context->S0 = 0xAA000000;
+    context->S1 = 0xAA000001;
+    context->S2 = 0xAA000002;
+    context->S3 = 0xAA000003;
+    context->S4 = 0xAA000004;
+    context->S5 = 0xAA000005;
+    context->S6 = 0xAA000006;
+    context->S7 = 0xAA000007;
+    context->S8 = 0xAA000008;
+    context->S9 = 0xAA000009;
+    context->S10 = 0xAA00000A;
+    context->S11 = 0xAA00000B;
+    context->S12 = 0xAA00000C;
+    context->S13 = 0xAA00000D;
+    context->S14 = 0xAA00000E;
+    context->S15 = 0xAA00000F;
+    context->FPSCR = 0x00000000;
+    context->NO_NAME = 0xAA000011;
+#endif
+
+    context->uwR4 = 0x04040404L;
+    context->uwR5 = 0x05050505L;
+    context->uwR6 = 0x06060606L;
+    context->uwR7 = 0x07070707L;
+    context->uwR8 = 0x08080808L;
+    context->uwR9 = 0x09090909L;
+    context->uwR10 = 0x10101010L;
+    context->uwR11 = 0x11111111L;
+    context->uwPriMask = 0;
+    context->uwR0 = taskID;
+    context->uwR1 = 0x01010101L;
+    context->uwR2 = 0x02020202L;
+    context->uwR3 = 0x03030303L;
+    context->uwR12 = 0x12121212L;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
+    context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
+    context->uwxPSR = 0x01000000L;
+
+    return (VOID *)context;
+}
+
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    UNUSED(stackTop);
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+    return LOS_OK; /* never return */
+}

arch/arm/cortex-m33/iar/NTZ/los_dispatch.S

@@ -0,0 +1,175 @@
+;
+; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this list of
+;    conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice, this list
+;    of conditions and the following disclaimer in the documentation and/or other materials
+;    provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without specific prior written
+;    permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+    PRESERVE8
+
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
+    EXPORT  HalStartToRun
+    EXPORT  ArchTaskSchedule
+    EXPORT  HalPendSV
+    IMPORT  OsSchedTaskSwitch
+    IMPORT  OsSignalTaskContextRestore
+    IMPORT  g_losTask
+
+OS_FPU_CPACR                EQU     0xE000ED88
+OS_FPU_CPACR_ENABLE         EQU     0x00F00000
+OS_NVIC_INT_CTRL            EQU     0xE000ED04
+OS_NVIC_SYSPRI2             EQU     0xE000ED20
+OS_NVIC_PENDSV_PRI          EQU     0xF0F00000
+OS_NVIC_PENDSVSET           EQU     0x10000000
+OS_TASK_STATUS_RUNNING      EQU     0x0010
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+
+    MACRO SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+    ENDM
+
+HalStartToRun
+    LDR     R4, =OS_NVIC_SYSPRI2
+    LDR     R5, =OS_NVIC_PENDSV_PRI
+    STR     R5, [R4]
+
+    MOV     R0, #2
+    MSR     CONTROL, R0
+
+    LDR     R1, =g_losTask
+    LDR     R0, [R1, #4]
+    LDR     R12, [R0]
+
+    LDR.W   R1, =OS_FPU_CPACR
+    LDR     R1, [R1]
+    AND     R1, R1, #OS_FPU_CPACR_ENABLE
+    CMP     R1, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU
+    ADD     R12, R12, #100
+
+    LDMFD   R12!, {R0-R7}
+    ADD     R12, R12, #72
+    MSR     PSP, R12
+    VPUSH   S0;
+    VPOP    S0;
+    MOV     LR, R5
+    CPSIE   I
+    BX      R6
+
+__DisabledFPU
+    ADD     R12, R12, #36
+
+    LDMFD   R12!, {R0-R7}
+    MSR     PSP, R12
+    MOV     LR, R5
+    CPSIE   I
+    BX      R6
+
+
+ArchIntLock
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+ArchIntUnLock
+    MRS     R0, PRIMASK
+    CPSIE   I
+    BX      LR
+
+ArchIntRestore
+    MSR     PRIMASK, R0
+    BX      LR
+
+ArchTaskSchedule
+    LDR     R0, =OS_NVIC_INT_CTRL
+    LDR     R1, =OS_NVIC_PENDSVSET
+    STR     R1, [R0]
+    DSB
+    ISB
+    BX      LR
+
+HalPendSV
+    MRS     R12, PRIMASK
+    CPSID   I
+
+HalTaskSwitch
+    PUSH    {R12, LR}
+    BLX     OsSchedTaskSwitch
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R0, LR
+    BNE     TaskContextSwitch
+    MSR     PRIMASK, R12
+    BX      LR
+
+TaskContextSwitch
+    MOV     LR, R0
+    MRS     R0, PSP
+
+    STMFD   R0!, {R4-R12}
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU1
+    VSTMDB  R0!, {D8-D15}
+
+__DisabledFPU1
+    LDR     R5, =g_losTask
+    LDR     R6, [R5]
+    STR     R0, [R6]
+
+    LDR     R0, [R5, #4]
+    STR     R0, [R5]
+    LDR     R1, [R0]
+
+SignalContextRestore
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU2
+    VLDMIA  R1!, {D8-D15}
+
+__DisabledFPU2
+    LDMFD   R1!, {R4-R12}
+    MSR     PSP,  R1
+
+    MSR     PRIMASK, R12
+    BX      LR
+
+    END

arch/arm/cortex-m33/iar/NTZ/los_exc.S

@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    PRESERVE8
+    SECTION    .text:CODE(2)
+    THUMB
+
+    EXPORT  HalExcNMI
+    EXPORT  HalExcHardFault
+    EXPORT  HalExcMemFault
+    EXPORT  HalExcBusFault
+    EXPORT  HalExcUsageFault
+    EXPORT  HalSVCHandler
+
+    IMPORT HalExcHandleEntry
+    IMPORT g_uwExcTbl
+    IMPORT g_taskScheduled
+
+OS_FLG_BGD_ACTIVE   EQU   0x0002
+
+OS_EXC_CAUSE_NMI            EQU   16
+OS_EXC_CAUSE_HARDFAULT      EQU   17
+
+HF_DEBUGEVT     EQU   20
+HF_VECTBL       EQU   21
+
+FLAG_ADDR_VALID             EQU   0x10000
+FLAG_HWI_ACTIVE             EQU   0x20000
+FLAG_NO_FLOAT               EQU   0x10000000
+
+OS_NVIC_FSR                 EQU   0xE000ED28      ;include BusFault/MemFault/UsageFault State Regeister
+OS_NVIC_HFSR                EQU   0xE000ED2C      ;HardFault State Regeister
+OS_NVIC_BFAR                EQU   0xE000ED38
+OS_NVIC_MMAR                EQU   0xE000ED34
+OS_NVIC_ACT_BASE            EQU   0xE000E300
+OS_NVIC_SHCSRS              EQU   0xE000ED24
+OS_NVIC_SHCSR_MASK          EQU   0xC00
+
+HalExcNMI
+    MOV  R0, #OS_EXC_CAUSE_NMI
+    MOV  R1, #0
+    B  osExcDispatch
+
+HalExcHardFault
+    MOV  R0, #OS_EXC_CAUSE_HARDFAULT
+    LDR  R2, =OS_NVIC_HFSR
+    LDR  R2, [R2]
+
+    MOV  R1, #HF_DEBUGEVT
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x80000000
+    BNE  osExcDispatch     ; DEBUGEVT
+
+    AND  R0, R0 , #0x000000FF
+    MOV  R1, #HF_VECTBL
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x00000002
+    BNE  osExcDispatch     ; VECTBL
+
+    ;if not DEBUGEVT and VECTBL then is FORCED
+    AND  R0, R0, #0x000000FF
+
+    LDR  R2, =OS_NVIC_FSR
+    LDR  R2, [R2]
+
+    TST  R2, #0x8000     ; BFARVALID
+    BNE  _HFBusFault     ; BusFault
+
+    TST  R2, #0x80       ; MMARVALID
+    BNE  _HFMemFault     ; MemFault
+
+    MOV  R12,#0
+    B    osHFExcCommonBMU
+
+_HFBusFault
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    B    osHFExcCommonBMU
+
+_HFMemFault
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+
+osHFExcCommonBMU
+    CLZ  R2, R2
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R2
+    LDRB R2, [R3]
+    ORR  R0, R0, R2, LSL #0x8
+    ORR  R0, R0 ,R12
+    B    osExcDispatch
+
+HalSVCHandler
+    TST   LR, #0x4
+    ITE   EQ
+    MRSEQ R0, MSP
+    MRSNE R0, PSP
+    LDR   R1, [R0,#24]
+    LDRB  R0, [R1,#-2]
+    MOV   R1, #0
+    B     osExcDispatch
+
+HalExcBusFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x8000 ; BFARVALID
+    BEQ  _ExcBusNoADDR
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1F00
+
+    B    osExcCommonBMU
+
+_ExcBusNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcMemFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x80 ; MMARVALID
+    BEQ  _ExcMemNoADDR
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1B
+
+    B    osExcCommonBMU
+
+_ExcMemNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcUsageFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    MOV  R1, #0x030F
+    LSL  R1, R1, #16
+    AND  R0, R0, R1
+    MOV  R12, #0
+
+osExcCommonBMU
+    CLZ  R0, R0
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R0
+    LDRB R0, [R3]
+    ORR  R0, R0, R12
+
+; R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid),  R1 -- EXCADDR
+osExcDispatch
+    LDR   R2, =OS_NVIC_ACT_BASE
+    MOV   R12, #8                       ; R12 is hwi check loop counter
+
+_hwiActiveCheck
+    LDR   R3, [R2]                      ; R3 store active hwi register when exc
+    CMP   R3, #0
+    BEQ   _hwiActiveCheckNext
+
+    ; exc occured in IRQ
+    ORR   R0, R0, #FLAG_HWI_ACTIVE
+    RBIT  R2, R3
+    CLZ   R2, R2
+    AND   R12, R12, #1
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as uwPid
+
+_ExcInMSP
+    CMP   LR, #0xFFFFFFE9
+    BNE   _NoFloatInMsp
+    ADD   R3, R13, #104
+    PUSH  {R3}
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    VPUSH {D8-D15}
+    B     _handleEntry
+
+_NoFloatInMsp
+    ADD   R3, R13, #32
+    PUSH  {R3} ; save IRQ SP            ; store message-->exc: MSP(R13)
+
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+    B     _handleEntry
+
+_hwiActiveCheckNext
+    ADD   R2, R2, #4                        ; next NVIC ACT ADDR
+    SUBS  R12, R12, #1
+    BNE   _hwiActiveCheck
+
+    ;/*NMI interrupt excption*/
+    LDR   R2, =OS_NVIC_SHCSRS
+    LDRH  R2,[R2]
+    LDR   R3,=OS_NVIC_SHCSR_MASK
+    AND   R2, R2,R3
+    CMP   R2,#0
+    BNE   _ExcInMSP
+    ; exc occured in Task or Init or exc
+    ; reserved for register info from task stack
+
+    LDR  R2, =g_taskScheduled
+    LDR  R2, [R2]
+    TST  R2, #1         ; OS_FLG_BGD_ACTIVE
+    BEQ  _ExcInMSP                      ; if exc occured in Init then branch
+
+
+    CMP   LR, #0xFFFFFFED               ;auto push floating registers
+    BNE   _NoFloatInPsp
+
+    ; exc occured in Task
+    MOV   R2,  R13
+    SUB   R13, #96                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #104
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+    VPUSH {D8-D15}
+
+    ; copy auto saved task register
+
+    LDMFD R3!, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    VLDMIA  R3!, {D8-D15}
+    VSTMDB  R2!, {D8-D15}
+    STMFD R2!, {R4-R11}
+    B     _handleEntry
+
+_NoFloatInPsp
+    MOV   R2,  R13                           ;no auto push floating registers
+    SUB   R13, #32                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #32
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+
+    LDMFD R3, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    STMFD R2!, {R4-R11}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+
+_handleEntry
+    MOV R3, R13                         ; R13:the 4th param
+    CPSID I
+    CPSID F
+    B  HalExcHandleEntry
+
+    NOP
+    END

arch/arm/cortex-m33/iar/NTZ/los_interrupt.c

@@ -0,0 +1,608 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_interrupt.h"
+#include "securec.h"
+#include <stdarg.h>
+#include "los_arch_interrupt.h"
+#include "los_context.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+
+/*lint -save -e40 -e522 -e533*/
+UINT32 g_intCount = 0;
+
+/*lint -restore*/
+#pragma location = ".data.vector"
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+    HWI_PROC_FUNC pfnHandler;
+    VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+    }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+    }
+}
+#endif
+
+WEAK VOID SysTick_Handler(VOID)
+{
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HwiNumGet
+ Description : Get an interrupt number
+ Input       : None
+ Output      : None
+ Return      : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+    return __get_IPSR();
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+    return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function    : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+/*lint -e529*/
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+    while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+    UINT32 hwiIndex;
+    UINT32 intSave;
+
+#if (LOSCFG_KERNEL_RUNSTOP == 1)
+    SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
+#endif
+
+    intSave = LOS_IntLock();
+
+    g_intCount++;
+
+    LOS_IntRestore(intSave);
+
+    hwiIndex = HwiNumGet();
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+
+    HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+        g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+    }
+#else
+    if (g_hwiHandlerForm[hwiIndex] != 0) {
+        g_hwiHandlerForm[hwiIndex]();
+    }
+#endif
+
+    HalAftInterruptHandler(hwiIndex);
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+    intSave = LOS_IntLock();
+    g_intCount--;
+    LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiCreate
+ Description : create hardware interrupt
+ Input       : hwiNum   --- hwi num to create
+               hwiPrio  --- priority of the hwi
+               hwiMode  --- unused
+               hwiHandler --- hwi handler
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T hwiMode,
+                                           HWI_PROC_FUNC hwiHandler,
+                                           HwiIrqParam *irqParam)
+{
+    (VOID)hwiMode;
+    UINTPTR intSave;
+
+    if (hwiHandler == NULL) {
+        return OS_ERRNO_HWI_PROC_FUNC_NULL;
+    }
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return OS_ERRNO_HWI_ALREADY_CREATED;
+    }
+
+    if (hwiPrio > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (irqParam != NULL) {
+        OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+    } else {
+        OsSetVector(hwiNum, hwiHandler, NULL);
+    }
+#else
+    (VOID)irqParam;
+    OsSetVector(hwiNum, hwiHandler);
+#endif
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input       : hwiNum   --- hwi num to delete
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+    (VOID)irqParam;
+    UINT32 intSave;
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    intSave = LOS_IntLock();
+
+    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+#define FAULT_STATUS_REG_BIT            32
+#define USGFAULT                        (1 << 18)
+#define BUSFAULT                        (1 << 17)
+#define MEMFAULT                        (1 << 16)
+#define DIV0FAULT                       (1 << 4)
+#define HARDFAULT_IRQN                  (-13)
+
+ExcInfo g_excInfo = {0};
+
+UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
+    0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
+    0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
+    0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
+    0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
+};
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcNvicDump(VOID)
+{
+#define OS_NR_NVIC_EXC_DUMP_TYPES   7
+    UINT32 *base = NULL;
+    UINT32 len, i, j;
+    UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
+        OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
+    };
+    UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
+        OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
+        OS_NVIC_INT_CTRL_SIZE
+    };
+    CHAR strRgEnable[] = "enable";
+    CHAR strRgPending[] = "pending";
+    CHAR strRgActive[] = "active";
+    CHAR strRgPriority[] = "priority";
+    CHAR strRgException[] = "exception";
+    CHAR strRgShcsr[] = "shcsr";
+    CHAR strRgIntCtrl[] = "control";
+    CHAR *strRgs[] = {
+        strRgEnable, strRgPending, strRgActive, strRgPriority,
+        strRgException, strRgShcsr, strRgIntCtrl
+    };
+
+    PRINTK("\r\nOS exception NVIC dump:\n");
+    for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
+        base = (UINT32 *)rgNvicBases[i];
+        len = rgNvicLens[i];
+        PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
+        len = (len >> 2); /* 2: Gets the next register offset */
+        for (j = 0; j < len; j++) {
+            PRINTK("0x%x ", *(base + j));
+            if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
+                PRINTK("\n");
+            }
+        }
+        PRINTK("\n");
+    }
+}
+
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+    CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+    PRINTK("Type      = %d\n", excInfo->type);
+    PRINTK("ThrdPid   = %d\n", excInfo->thrdPid);
+    PRINTK("Phase     = %s\n", phaseStr[excInfo->phase]);
+    PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Current task info:\n");
+    if (excInfo->phase == OS_EXC_IN_TASK) {
+        LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+        PRINTK("Task name = %s\n", taskCB->taskName);
+        PRINTK("Task ID   = %d\n", taskCB->taskID);
+        PRINTK("Task SP   = %p\n", taskCB->stackPointer);
+        PRINTK("Task ST   = 0x%x\n", taskCB->topOfStack);
+        PRINTK("Task SS   = 0x%x\n", taskCB->stackSize);
+    } else if (excInfo->phase == OS_EXC_IN_HWI) {
+        PRINTK("Exception occur in interrupt phase!\n");
+    } else {
+        PRINTK("Exception occur in system init phase!\n");
+    }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Exception reg dump:\n");
+    PRINTK("PC        = 0x%x\n", excInfo->context->uwPC);
+    PRINTK("LR        = 0x%x\n", excInfo->context->uwLR);
+    PRINTK("SP        = 0x%x\n", excInfo->context->uwSP);
+    PRINTK("R0        = 0x%x\n", excInfo->context->uwR0);
+    PRINTK("R1        = 0x%x\n", excInfo->context->uwR1);
+    PRINTK("R2        = 0x%x\n", excInfo->context->uwR2);
+    PRINTK("R3        = 0x%x\n", excInfo->context->uwR3);
+    PRINTK("R4        = 0x%x\n", excInfo->context->uwR4);
+    PRINTK("R5        = 0x%x\n", excInfo->context->uwR5);
+    PRINTK("R6        = 0x%x\n", excInfo->context->uwR6);
+    PRINTK("R7        = 0x%x\n", excInfo->context->uwR7);
+    PRINTK("R8        = 0x%x\n", excInfo->context->uwR8);
+    PRINTK("R9        = 0x%x\n", excInfo->context->uwR9);
+    PRINTK("R10       = 0x%x\n", excInfo->context->uwR10);
+    PRINTK("R11       = 0x%x\n", excInfo->context->uwR11);
+    PRINTK("R12       = 0x%x\n", excInfo->context->uwR12);
+    PRINTK("PriMask   = 0x%x\n", excInfo->context->uwPriMask);
+    PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+    UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+    UINT32 index;
+
+    OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
+
+    PRINTK("----- backtrace start -----\n");
+    for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+        if (LR[index] == 0) {
+            break;
+        }
+        PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
+    }
+    PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+    PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+    MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+    UINT32 errCnt;
+    UINT32 i;
+
+    (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+    errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+    if (errCnt < OS_SYS_MEM_NUM) {
+        errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+    }
+
+    if (errCnt == 0) {
+        PRINTK("all memory pool check passed!\n");
+        return;
+    }
+
+    for (i = 0; i < errCnt; i++) {
+        PRINTK("pool num    = %d\n", i);
+        PRINTK("pool type   = %d\n", memExcInfo[i].type);
+        PRINTK("pool addr   = 0x%x\n", memExcInfo[i].startAddr);
+        PRINTK("pool size   = 0x%x\n", memExcInfo[i].size);
+        PRINTK("pool free   = 0x%x\n", memExcInfo[i].free);
+        PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
+        PRINTK("pool error node addr  = 0x%x\n", memExcInfo[i].errorAddr);
+        PRINTK("pool error node len   = 0x%x\n", memExcInfo[i].errorLen);
+        PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
+    }
+#endif
+    UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+    if (ret == LOS_OK) {
+        PRINTK("system heap memcheck over, all passed!\n");
+    }
+
+    PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+    PRINTK("*************Exception Information**************\n");
+    OsExcTypeInfo(excInfo);
+    OsExcCurTaskInfo(excInfo);
+    OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+    OsExcBackTraceInfo(excInfo);
+#endif
+    OsGetAllTskInfo();
+    OsExcNvicDump();
+    OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+    UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
+    g_intCount++;
+    g_excInfo.nestCnt++;
+
+    g_excInfo.type = excType & OS_NULL_SHORT;
+
+    if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
+        g_excInfo.faultAddr = faultAddr;
+    } else {
+        g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+    }
+    if (g_losTask.runTask != NULL) {
+        if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
+            g_excInfo.phase = OS_EXC_IN_HWI;
+            g_excInfo.thrdPid = pid;
+        } else {
+            g_excInfo.phase = OS_EXC_IN_TASK;
+            g_excInfo.thrdPid = g_losTask.runTask->taskID;
+        }
+    } else {
+        g_excInfo.phase = OS_EXC_IN_INIT;
+        g_excInfo.thrdPid = OS_NULL_INT;
+    }
+    if (excType & OS_EXC_FLAG_NO_FLOAT) {
+        g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
+    } else {
+        g_excInfo.context = excBufAddr;
+    }
+
+    OsDoExcHook(EXC_INTERRUPT);
+    OsExcInfoDisplay(&g_excInfo);
+    ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function    : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    UINT32 index;
+    g_hwiForm[0] = 0;             /* [0] Top of Stack */
+    g_hwiForm[1] = Reset_Handler; /* [1] reset */
+    for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
+        g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+    }
+    /* Exception handler register */
+    g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT]   = HalExcNMI;
+    g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT]        = HalExcHardFault;
+    g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = HalExcMemFault;
+    g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT]         = HalExcBusFault;
+    g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT]       = HalExcUsageFault;
+    g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT]           = HalSVCHandler;
+    g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT]           = HalPendSV;
+    g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT]          = SysTick_Handler;
+
+    /* Interrupt vector table location */
+    SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
+#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
+    NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
+#endif
+
+    /* Enable USGFAULT, BUSFAULT, MEMFAULT */
+    *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+    /* Enable DIV 0 and unaligned exception */
+    *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
+
+    return;
+}
+

arch/arm/cortex-m33/iar/NTZ/los_timer.c

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "los_tick.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+    UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
+
+    tick->freq = OS_SYS_CLOCK;
+
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
+#else
+    OsSetVector(tick->irqNum, handler);
+#endif
+#endif
+
+    ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
+    if (ret == 1) {
+        return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
+    }
+
+    return LOS_OK;
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+    if (nextResponseTime > g_archTickTimer.periodMax) {
+        nextResponseTime = g_archTickTimer.periodMax;
+    }
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
+    SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+    UINT32 hwCycle = 0;
+    UINTPTR intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
+    *period = SysTick->LOAD;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
+    LOS_IntRestore(intSave);
+    return (UINT64)hwCycle;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+    __DSB();
+    __WFI();
+    __ISB();
+    return LOS_OK;
+}

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_atomic.h

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    asm volatile("ldrex %0, [%1]\n"
+                 : "=&r"(val)
+                 : "r"(v)
+                 : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %0, [%1]\n"
+                     "strex %0, %2, [%1]\n"
+                     : "=&r"(status)
+                     : "r"(v), "r"(setVal)
+                     : "cc");
+    } while (status != 0);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "add %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(addVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "sub %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(subVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        asm volatile("ldrex %0, [%2]\n"
+                     "strex %1, %3, [%2]"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        asm volatile("ldrex %0, [%2]\n"
+                     "mov %1, #0\n"
+                     "cmp %0, %3\n"
+                     "bne 1f\n"
+                     "strex %1, %4, [%2]\n"
+                     "1:"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(oldVal), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_context.h

@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef struct TagTskContext {
+    UINT32 secureContext;
+    UINT32 stackLmit;
+    UINT32 excReturn;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+} TaskContext;
+
+/**
+ * @ingroup  los_config
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */
+

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_interrupt.h

@@ -0,0 +1,684 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_EXC_H
+#define _LOS_EXC_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_hwi
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM                        LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_hwi
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST                   0
+#endif
+
+/* *
+ * @ingroup los_hwi
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST                    7
+#endif
+
+
+/* *
+ * @ingroup  los_hwi
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_hwi
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_hwi
+ * Count of M-Core system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT                     16
+
+/* *
+ * @ingroup los_hwi
+ * Count of M-Core interrupt vector.
+ */
+#define OS_VECTOR_CNT                         (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_hwi
+ * AIRCR register priority group parameter .
+ */
+#define OS_NVIC_AIRCR_PRIGROUP                7
+
+/* *
+ * @ingroup los_hwi
+ * Boot interrupt vector table.
+ */
+extern UINT32 _BootVectors[];
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE           LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY                LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED          LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_hwi
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+/* *
+ * @ingroup los_hwi
+ * SysTick control and status register.
+ */
+#define OS_SYSTICK_CONTROL_REG                0xE000E010
+
+/* *
+ * @ingroup los_hw
+ * SysTick current value register.
+ */
+#define OS_SYSTICK_CURRENT_REG                0xE000E018
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt Priority-Level Registers.
+ */
+#define OS_NVIC_PRI_BASE                      0xE000E400
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt enable register for 0-31.
+ */
+#define OS_NVIC_SETENA_BASE                   0xE000E100
+
+/* *
+ * @ingroup los_hwi
+ * interrupt pending register.
+ */
+#define OS_NVIC_SETPEND_BASE                  0xE000E200
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt active register.
+ */
+#define OS_NVIC_INT_ACT_BASE                  0xE000E300
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt disable register for 0-31.
+ */
+#define OS_NVIC_CLRENA_BASE                   0xE000E180
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt control and status register.
+ */
+#define OS_NVIC_INT_CTRL                      0xE000ED04
+
+/* *
+ * @ingroup los_hwi
+ * Vector table offset register.
+ */
+#define OS_NVIC_VTOR                          0xE000ED08
+
+/* *
+ * @ingroup los_hwi
+ * Application interrupt and reset control register
+ */
+#define OS_NVIC_AIRCR                         0xE000ED0C
+
+/* *
+ * @ingroup los_hwi
+ * System exception priority register.
+ */
+#define OS_NVIC_EXCPRI_BASE                   0xE000ED18
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 1 :reset.
+ */
+#define OS_EXC_RESET                          1
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 2 :Non-Maskable Interrupt.
+ */
+#define OS_EXC_NMI                            2
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 3 :(hard)fault.
+ */
+#define OS_EXC_HARD_FAULT                     3
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 4 :MemManage fault.
+ */
+#define OS_EXC_MPU_FAULT                      4
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 5 :Bus fault.
+ */
+#define OS_EXC_BUS_FAULT                      5
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 6 :Usage fault.
+ */
+#define OS_EXC_USAGE_FAULT                    6
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 11 :SVCall.
+ */
+#define OS_EXC_SVC_CALL                       11
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 12 :Debug monitor.
+ */
+#define OS_EXC_DBG_MONITOR                    12
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 14 :PendSV.
+ */
+#define OS_EXC_PEND_SV                        14
+
+/* *
+ * @ingroup los_hwi
+ * Interrupt No. 15 :SysTick.
+ */
+#define OS_EXC_SYS_TICK                       15
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li
+></ul>
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Reset the vector table.
+ *
+ * @par Description:
+ * This API is used to reset the vector table.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID Reset_Handler(VOID);
+
+/* *
+ * @ingroup  los_hwi
+ * @brief: Pended System Call.
+ *
+ * @par Description:
+ * PendSV can be pended and is useful for an OS to pend an exception
+ * so that an action can be performed after other important tasks are completed.
+ *
+ * @attention:
+ * <ul><li>None.</li></ul>
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
+ * @see None.
+ */
+extern VOID HalPendSV(VOID);
+
+
+#define OS_EXC_IN_INIT                      0
+#define OS_EXC_IN_TASK                      1
+#define OS_EXC_IN_HWI                       2
+
+#define OS_EXC_MAX_BUF_LEN                  25
+#define OS_EXC_MAX_NEST_DEPTH               1
+
+#define OS_NVIC_SHCSR                       0xE000ED24
+#define OS_NVIC_CCR                         0xE000ED14
+
+#define OS_NVIC_INT_ENABLE_SIZE             0x20
+#define OS_NVIC_INT_PRI_SIZE                0xF0
+#define OS_NVIC_EXCPRI_SIZE                 0xC
+#define OS_NVIC_INT_CTRL_SIZE               4
+#define OS_NVIC_SHCSR_SIZE                  4
+
+#define OS_NVIC_INT_PEND_SIZE               OS_NVIC_INT_ACT_SIZE
+#define OS_NVIC_INT_ACT_SIZE                OS_NVIC_INT_ENABLE_SIZE
+
+#define OS_EXC_FLAG_NO_FLOAT                0x10000000
+#define OS_EXC_FLAG_FAULTADDR_VALID         0x01
+#define OS_EXC_FLAG_IN_HWI                  0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR        0xABABABAB
+
+#define OS_EXC_EVENT                        0x00000001
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw'  correspond to the registers in the cpu  data sheet.
+ */
+typedef struct TagExcContext {
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    UINT32 S16;
+    UINT32 S17;
+    UINT32 S18;
+    UINT32 S19;
+    UINT32 S20;
+    UINT32 S21;
+    UINT32 S22;
+    UINT32 S23;
+    UINT32 S24;
+    UINT32 S25;
+    UINT32 S26;
+    UINT32 S27;
+    UINT32 S28;
+    UINT32 S29;
+    UINT32 S30;
+    UINT32 S31;
+#endif
+    UINT32 uwR4;
+    UINT32 uwR5;
+    UINT32 uwR6;
+    UINT32 uwR7;
+    UINT32 uwR8;
+    UINT32 uwR9;
+    UINT32 uwR10;
+    UINT32 uwR11;
+    UINT32 uwPriMask;
+    /* auto save */
+    UINT32 uwSP;
+    UINT32 uwR0;
+    UINT32 uwR1;
+    UINT32 uwR2;
+    UINT32 uwR3;
+    UINT32 uwR12;
+    UINT32 uwLR;
+    UINT32 uwPC;
+    UINT32 uwxPSR;
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED) && (__FPU_USED== 1U)))
+    UINT32 S0;
+    UINT32 S1;
+    UINT32 S2;
+    UINT32 S3;
+    UINT32 S4;
+    UINT32 S5;
+    UINT32 S6;
+    UINT32 S7;
+    UINT32 S8;
+    UINT32 S9;
+    UINT32 S10;
+    UINT32 S11;
+    UINT32 S12;
+    UINT32 S13;
+    UINT32 S14;
+    UINT32 S15;
+    UINT32 FPSCR;
+    UINT32 NO_NAME;
+#endif
+}EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+
+VOID HalExcNMI(VOID);
+VOID HalExcHardFault(VOID);
+VOID HalExcMemFault(VOID);
+VOID HalExcBusFault(VOID);
+VOID HalExcUsageFault(VOID);
+VOID HalSVCHandler(VOID);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was being pushed.
+ */
+#define OS_EXC_BF_STKERR           1
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the bus status register was out of the stack.
+ */
+#define OS_EXC_BF_UNSTKERR         2
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register imprecise data access violation.
+ */
+#define OS_EXC_BF_IMPRECISERR      3
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register exact data access violation.
+ */
+#define OS_EXC_BF_PRECISERR        4
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Bus status register access violation while pointing.
+ */
+#define OS_EXC_BF_IBUSERR          5
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was being pushed.
+ */
+#define OS_EXC_MF_MSTKERR          6
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
+ */
+#define OS_EXC_MF_MUNSTKERR        7
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register data access violation.
+ */
+#define OS_EXC_MF_DACCVIOL         8
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Memory management status register access violation.
+ */
+#define OS_EXC_MF_IACCVIOL         9
+
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
+ */
+#define OS_EXC_UF_DIVBYZERO        10
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error, error caused by unaligned access.
+ */
+#define OS_EXC_UF_UNALIGNED        11
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
+ */
+#define OS_EXC_UF_NOCP             12
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
+ */
+#define OS_EXC_UF_INVPC            13
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
+ */
+#define OS_EXC_UF_INVSTATE         14
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
+ */
+#define OS_EXC_UF_UNDEFINSTR       15
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: NMI
+ */
+
+#define OS_EXC_CAUSE_NMI           16
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: hard fault
+ */
+#define OS_EXC_CAUSE_HARDFAULT     17
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: The task handler exits.
+ */
+#define OS_EXC_CAUSE_TASK_EXIT     18
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A fatal error.
+ */
+#define OS_EXC_CAUSE_FATAL_ERR     19
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: Hard Fault caused by a debug event.
+ */
+#define OS_EXC_CAUSE_DEBUGEVT      20
+
+/**
+ * @ingroup los_exc
+ * Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
+ */
+#define OS_EXC_CAUSE_VECTBL        21
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
+ *
+ */
+typedef struct TagExcInfo {
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    UINT16 phase;
+    /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
+    UINT16 type;
+    /**< If the exact address access error indicates the wrong access address when the exception occurred */
+    UINT32 faultAddr;
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    UINT32 thrdPid;
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
+    UINT16 nestCnt;
+    /**< reserve */
+    UINT16 reserved;
+    /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+    EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_curNestCount;
+extern UINT32 g_intCount;
+extern UINT8 g_uwExcTbl[32];
+extern ExcInfo g_excInfo;
+
+#define MAX_INT_INFO_SIZE       (8 + 0x164)
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_EXC_H */

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_timer.h

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */
+

arch/arm/cortex-m33/iar/TZ/non_secure/los_context.c

@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -29,75 +29,43 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "los_base.h"
-#include "los_task_pri.h"
-#include "los_hw.h"
-#include "los_priqueue_pri.h"
+#include "los_context.h"
 #include "securec.h"
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#endif /* __cplusplus */
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
 
 /* ****************************************************************************
- Function    : OsSchedule
- Description : task scheduling
+ Function    : ArchInit
+ Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-VOID OsSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    osTaskSchedule();
+    HalHwiInit();
 }
 
 /* ****************************************************************************
- Function    : LOS_Schedule
- Description : Function to determine whether task scheduling is required.
- Input       : None
- Output      : None
- Return      : None
- **************************************************************************** */
-VOID LOS_Schedule(VOID)
-{
-    UINTPTR intSave;
-
-    intSave = LOS_IntLock();
-
-    /* Find the highest task */
-    g_losTask.newTask = LOS_DL_LIST_ENTRY(OsPriqueueTop(), LosTaskCB, pendList);
-
-    /* In case that running is not highest then reschedule */
-    if (g_losTask.runTask != g_losTask.newTask) {
-        if (!g_losTaskLock) {
-            LOS_IntRestore(intSave);
-
-            osTaskSchedule();
-
-            return;
-        }
-    }
-
-    LOS_IntRestore(intSave);
-}
-
-/* ****************************************************************************
- Function    : OsTaskExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID OsTaskExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
-    __disable_irq();
-    while (1) {}
+    LOS_IntLock();
+    while (1) {
+    }
 }
 
 /* ****************************************************************************
- Function    : OsTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -105,19 +73,9 @@ LITE_OS_SEC_TEXT_MINOR VOID OsTaskExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *OsTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -157,6 +115,10 @@ LITE_OS_SEC_TEXT_INIT VOID *OsTskStackInit(UINT32 taskID, UINT32 stackSize, VOID
     context->NO_NAME = 0xAA000011;
 #endif
 
+    context->secureContext = 0UL;
+    context->stackLmit = (UINT32)topStack;
+    context->excReturn = 0xFFFFFFBC;
+
     context->uwR4 = 0x04040404L;
     context->uwR5 = 0x05050505L;
     context->uwR6 = 0x06060606L;
@@ -171,24 +133,31 @@ LITE_OS_SEC_TEXT_INIT VOID *OsTskStackInit(UINT32 taskID, UINT32 stackSize, VOID
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)OsTaskExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT VOID OsEnterSleep(VOID)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
 {
-    __DSB();
-    __WFI();
-    __ISB();
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->stackLimit = (UINT32)stackTop;
+    context->excReturn = 0xFFFFFFBC;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
 }
 
-#ifdef __cplusplus
-#if __cplusplus
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+    return LOS_OK; /* never return */
 }
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-

arch/arm/cortex-m33/iar/TZ/non_secure/los_dispatch.S

@@ -0,0 +1,237 @@
+;
+; Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+; Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this list of
+;    conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice, this list
+;    of conditions and the following disclaimer in the documentation and/or other materials
+;    provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without specific prior written
+;    permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+    PRESERVE8
+
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
+    EXPORT  ArchTaskSchedule
+    EXPORT  HalPendSV
+    EXPORT  HalSVCHandler
+    EXPORT  HalStartFirstTask
+    EXPORT  HalSVCStartSchedule
+    EXPORT  HalSVCSecureContextAlloc
+    EXPORT  HalSVCSecureContextFree
+    IMPORT  OsSignalTaskContextRestore
+    IMPORT  OsSchedTaskSwitch
+    IMPORT  g_losTask
+
+    EXTERN  HalSecureSVCHandler
+    EXTERN  HalSecureContextSave
+    EXTERN  HalSecureContextLoad
+    EXTERN  g_secureContext
+
+OS_FPU_CPACR                EQU     0xE000ED88
+OS_FPU_CPACR_ENABLE         EQU     0x00F00000
+OS_NVIC_INT_CTRL            EQU     0xE000ED04
+OS_NVIC_SYSPRI2             EQU     0xE000ED20
+OS_NVIC_PENDSV_PRI          EQU     0xF0F00000
+OS_NVIC_PENDSVSET           EQU     0x10000000
+OS_TASK_STATUS_RUNNING      EQU     0x0010
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+
+    MACRO SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+    ENDM
+
+HalStartFirstTask
+    MOV     R0, #2
+    MSR     CONTROL, R0
+
+    LDR     R1, =g_losTask
+    LDR     R0, [R1, #4]
+
+    LDR     R12, [R0]                  /* Get the stack pointer of the current task. */
+    LDMFD   R12!, {R1-R3}              /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 = excReturn.*/
+    LDR     R4, =g_secureContext
+    STR     R1, [R4]                   /* Set the secureContext to g_secureContext handler. */
+    MSR     PSPLIM, R2                 /* Set the stackLmit for the PSPLIM about current task. */
+    ISB
+
+    LDR.W   R1, =OS_FPU_CPACR
+    LDR     R1, [R1]
+    AND     R1, R1, #OS_FPU_CPACR_ENABLE
+    CMP     R1, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU1
+    ADD     R12, R12, #64
+    VPUSH   S0;
+    VPOP    S0;
+
+__DisabledFPU1
+    ADD     R12, R12, #36
+    MSR     PSP, R12
+    CPSIE   I
+    BX      R3
+
+ArchIntLock
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+ArchIntUnLock
+    MRS     R0, PRIMASK
+    CPSIE   I
+    BX      LR
+
+ArchIntRestore
+    MSR     PRIMASK, R0
+    BX      LR
+
+ArchTaskSchedule
+    LDR     R0, =OS_NVIC_INT_CTRL
+    LDR     R1, =OS_NVIC_PENDSVSET
+    STR     R1, [R0]
+    DSB
+    ISB
+    BX      LR
+
+HalPendSV
+    MRS     R12, PRIMASK
+    CPSID   I
+
+HalTaskSwitch
+    SIGNAL_CONTEXT_RESTORE
+
+    PUSH    {R12, LR}
+    BLX     OsSchedTaskSwitch
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R0, LR
+    BNE     TaskContextSwitch
+    MSR     PRIMASK, R12
+    BX      LR
+
+TaskContextSwitch
+    MOV     LR, R0
+    MRS     R0, PSP
+
+    LDR     R2, =g_secureContext
+    LDR     R1, [R2]
+    CBZ     R1, __SaveNSContext               /* If the g_secureContext is NULL, so no secure context to save. */
+
+    PUSH    {R0-R1, R12, R14}                 /* Store registers, include LR, PRIMASK. */
+    BL      HalSecureContextSave              /* Store the secure context to g_secureContext->curStackPointer. */
+    POP     {R0-R3}
+    MOV     LR, R3
+    MOV     R12, R2                           /* R2 = PRIMASK. */
+
+__SaveNSContext
+    STMFD   R0!, {R4-R12}
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU2
+    VSTMDB  R0!, {D8-D15}
+
+__DisabledFPU2
+    LDR     R5, =g_losTask
+    LDR     R6, [R5]                          /* Get the stackPointer handler of the current task. */
+    SUBS    R0, R0, #12
+    STR     R0, [R6]                          /* Save the new top of stack in TCB. */
+    MRS     R2, PSPLIM
+    MOV     R3, LR
+    STMIA   R0!, {R1, R2-R3}                  /* Store g_secureContext, PSPLIM and LR on the stack of current task. */
+
+    LDR     R0, [R5, #4]
+    STR     R0, [R5]
+    LDR     R1, [R0]
+
+SignalContextRestore
+    LDMIA   R1!, {R0, R2-R3}                  /* Restore secureContext, PSPLIM and LR from the current task stack. */
+    MSR     PSPLIM, R2
+    MOV     LR, R3
+    LDR     R2, =g_secureContext
+    STR     R0, [R2]                          /* Set the secureContext of the new task to g_secureContext. */
+    CBZ     R0, __RestoreNSContext            /* If there is no secure context for the new task, so restore from the non-secure context. */
+    PUSH    {R1, R3}
+    BL      HalSecureContextLoad              /* Restore the secure context. */
+    POP     {R1, R3}
+    MOV     LR, R3
+
+__RestoreNSContext
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
+    AND     R3, R3, #OS_FPU_CPACR_ENABLE
+    CMP     R3, #OS_FPU_CPACR_ENABLE
+    BNE     __DisabledFPU3
+    VLDMIA  R1!, {D8-D15}
+
+__DisabledFPU3
+    LDMFD   R1!, {R4-R12}
+    MSR     PSP,  R1
+
+    MSR     PRIMASK, R12
+    BX      LR
+
+HalSVCStartSchedule
+    LDR     R4, =OS_NVIC_SYSPRI2
+    LDR     R5, =OS_NVIC_PENDSV_PRI
+    STR     R5, [R4]
+    CPSIE   I
+    DSB
+    ISB
+    SVC     2
+
+HalSVCSecureContextAlloc
+    SVC     0
+    BX      LR
+
+HalSVCSecureContextFree
+    SVC     1
+    BX      LR
+
+HalSVCHandler
+    TST     LR, #0x04
+    ITE     EQ
+    MRSEQ   R1, MSP
+    MRSNE   R1, PSP
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]                     /* Get the SVC number. */
+
+    PUSH    {LR}
+    MOV     R2, R1                            /* Get the stack for R2. */
+    LDMFD   R2!, {R1}                         /* Get the input arg for HalSecureSVCHandler. */
+    STMFD   R2!, {R1}
+    BL      HalSecureSVCHandler
+    POP     {LR}
+    BX      LR
+
+    END

arch/arm/cortex-m33/iar/TZ/non_secure/los_exc.S

@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    PRESERVE8
+    SECTION    .text:CODE(2)
+    THUMB
+
+    EXPORT  HalExcNMI
+    EXPORT  HalExcHardFault
+    EXPORT  HalExcMemFault
+    EXPORT  HalExcBusFault
+    EXPORT  HalExcUsageFault
+
+    IMPORT HalExcHandleEntry
+    IMPORT g_uwExcTbl
+    IMPORT g_taskScheduled
+
+OS_FLG_BGD_ACTIVE   EQU   0x0002
+
+OS_EXC_CAUSE_NMI            EQU   16
+OS_EXC_CAUSE_HARDFAULT      EQU   17
+
+HF_DEBUGEVT     EQU   20
+HF_VECTBL       EQU   21
+
+FLAG_ADDR_VALID             EQU   0x10000
+FLAG_HWI_ACTIVE             EQU   0x20000
+FLAG_NO_FLOAT               EQU   0x10000000
+
+OS_NVIC_FSR                 EQU   0xE000ED28      ;include BusFault/MemFault/UsageFault State Regeister
+OS_NVIC_HFSR                EQU   0xE000ED2C      ;HardFault State Regeister
+OS_NVIC_BFAR                EQU   0xE000ED38
+OS_NVIC_MMAR                EQU   0xE000ED34
+OS_NVIC_ACT_BASE            EQU   0xE000E300
+OS_NVIC_SHCSRS              EQU   0xE000ED24
+OS_NVIC_SHCSR_MASK          EQU   0xC00
+
+HalExcNMI
+    MOV  R0, #OS_EXC_CAUSE_NMI
+    MOV  R1, #0
+    B  osExcDispatch
+
+HalExcHardFault
+    MOV  R0, #OS_EXC_CAUSE_HARDFAULT
+    LDR  R2, =OS_NVIC_HFSR
+    LDR  R2, [R2]
+
+    MOV  R1, #HF_DEBUGEVT
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x80000000
+    BNE  osExcDispatch     ; DEBUGEVT
+
+    AND  R0, R0 , #0x000000FF
+    MOV  R1, #HF_VECTBL
+    ORR  R0, R0, R1, LSL #0x8
+    TST  R2, #0x00000002
+    BNE  osExcDispatch     ; VECTBL
+
+    ;if not DEBUGEVT and VECTBL then is FORCED
+    AND  R0, R0, #0x000000FF
+
+    LDR  R2, =OS_NVIC_FSR
+    LDR  R2, [R2]
+
+    TST  R2, #0x8000     ; BFARVALID
+    BNE  _HFBusFault     ; BusFault
+
+    TST  R2, #0x80       ; MMARVALID
+    BNE  _HFMemFault     ; MemFault
+
+    MOV  R12,#0
+    B    osHFExcCommonBMU
+
+_HFBusFault
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    B    osHFExcCommonBMU
+
+_HFMemFault
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+
+osHFExcCommonBMU
+    CLZ  R2, R2
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R2
+    LDRB R2, [R3]
+    ORR  R0, R0, R2, LSL #0x8
+    ORR  R0, R0 ,R12
+    B    osExcDispatch
+
+HalExcBusFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x8000 ; BFARVALID
+    BEQ  _ExcBusNoADDR
+    LDR  R1, =OS_NVIC_BFAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1F00
+
+    B    osExcCommonBMU
+
+_ExcBusNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcMemFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    TST  R0, #0x80 ; MMARVALID
+    BEQ  _ExcMemNoADDR
+    LDR  R1, =OS_NVIC_MMAR
+    LDR  R1, [R1]
+    MOV  R12, #FLAG_ADDR_VALID
+    AND  R0, R0, #0x1B
+
+    B    osExcCommonBMU
+
+_ExcMemNoADDR
+    MOV  R12,#0
+    B    osExcCommonBMU
+
+HalExcUsageFault
+    LDR  R0, =OS_NVIC_FSR
+    LDR  R0, [R0]
+
+    MOV  R1, #0x030F
+    LSL  R1, R1, #16
+    AND  R0, R0, R1
+    MOV  R12, #0
+
+osExcCommonBMU
+    CLZ  R0, R0
+    LDR  R3, =g_uwExcTbl
+    ADD  R3, R3, R0
+    LDRB R0, [R3]
+    ORR  R0, R0, R12
+
+; R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid),  R1 -- EXCADDR
+osExcDispatch
+    LDR   R2, =OS_NVIC_ACT_BASE
+    MOV   R12, #8                       ; R12 is hwi check loop counter
+
+_hwiActiveCheck
+    LDR   R3, [R2]                      ; R3 store active hwi register when exc
+    CMP   R3, #0
+    BEQ   _hwiActiveCheckNext
+
+    ; exc occured in IRQ
+    ORR   R0, R0, #FLAG_HWI_ACTIVE
+    RBIT  R2, R3
+    CLZ   R2, R2
+    AND   R12, R12, #1
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as pid
+
+_ExcInMSP
+    CMP   LR, #0xFFFFFFE9
+    BNE   _NoFloatInMsp
+    ADD   R3, R13, #104
+    PUSH  {R3}
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    VPUSH {D8-D15}
+    B     _handleEntry
+
+_NoFloatInMsp
+    ADD   R3, R13, #32
+    PUSH  {R3} ; save IRQ SP            ; store message-->exc: MSP(R13)
+
+    MRS   R12, PRIMASK                  ; store message-->exc: disable int?
+    PUSH {R4-R12}                       ; store message-->exc: {R4-R12}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+    B     _handleEntry
+
+_hwiActiveCheckNext
+    ADD   R2, R2, #4                        ; next NVIC ACT ADDR
+    SUBS  R12, R12, #1
+    BNE   _hwiActiveCheck
+
+    ;/*NMI interrupt excption*/
+    LDR   R2, =OS_NVIC_SHCSRS
+    LDRH  R2,[R2]
+    LDR   R3,=OS_NVIC_SHCSR_MASK
+    AND   R2, R2,R3
+    CMP   R2,#0
+    BNE   _ExcInMSP
+    ; exc occured in Task or Init or exc
+    ; reserved for register info from task stack
+
+    LDR  R2, =g_taskScheduled
+    LDR  R2, [R2]
+    TST  R2, #1         ; OS_FLG_BGD_ACTIVE
+    BEQ  _ExcInMSP                      ; if exc occured in Init then branch
+
+
+    CMP   LR, #0xFFFFFFED               ;auto push floating registers
+    BNE   _NoFloatInPsp
+
+    ; exc occured in Task
+    MOV   R2,  R13
+    SUB   R13, #96                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #104
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+    VPUSH {D8-D15}
+
+    ; copy auto saved task register
+
+    LDMFD R3!, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    VLDMIA  R3!, {D8-D15}
+    VSTMDB  R2!, {D8-D15}
+    STMFD R2!, {R4-R11}
+    B     _handleEntry
+
+_NoFloatInPsp
+    MOV   R2,  R13                           ;no auto push floating registers
+    SUB   R13, #32                      ; add 8 Bytes reg(for STMFD)
+
+    MRS   R3,  PSP
+    ADD   R12, R3, #32
+    PUSH  {R12}    ; save task SP
+
+    MRS   R12, PRIMASK
+    PUSH {R4-R12}
+
+    LDMFD R3, {R4-R11}                  ; R4-R11 store PSP reg(auto push when exc in task)
+    STMFD R2!, {R4-R11}
+    ORR   R0, R0, #FLAG_NO_FLOAT
+
+_handleEntry
+    MOV R3, R13                         ; R13:the 4th param
+    CPSID I
+    CPSID F
+    B  HalExcHandleEntry
+
+    NOP
+    END

arch/arm/cortex-m33/iar/TZ/non_secure/los_interrupt.c

@@ -0,0 +1,608 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_interrupt.h"
+#include "securec.h"
+#include <stdarg.h>
+#include "los_arch_interrupt.h"
+#include "los_context.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+
+/*lint -save -e40 -e522 -e533*/
+UINT32 g_intCount = 0;
+
+/*lint -restore*/
+#pragma location = ".data.vector"
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+    HWI_PROC_FUNC pfnHandler;
+    VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+    }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+    if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+        g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+        g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+    }
+}
+#endif
+
+WEAK VOID SysTick_Handler(VOID)
+{
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HwiNumGet
+ Description : Get an interrupt number
+ Input       : None
+ Output      : None
+ Return      : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+    return __get_IPSR();
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+    return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function    : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+/*lint -e529*/
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+    while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+    (VOID)arg;
+    return;
+}
+
+/* ****************************************************************************
+ Function    : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+    UINT32 hwiIndex;
+    UINT32 intSave;
+
+#if (LOSCFG_KERNEL_RUNSTOP == 1)
+    SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
+#endif
+
+    intSave = LOS_IntLock();
+
+    g_intCount++;
+
+    LOS_IntRestore(intSave);
+
+    hwiIndex = HwiNumGet();
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+
+    HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+        g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+    }
+#else
+    if (g_hwiHandlerForm[hwiIndex] != 0) {
+        g_hwiHandlerForm[hwiIndex]();
+    }
+#endif
+
+    HalAftInterruptHandler(hwiIndex);
+
+    OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+    intSave = LOS_IntLock();
+    g_intCount--;
+    LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiCreate
+ Description : create hardware interrupt
+ Input       : hwiNum   --- hwi num to create
+               hwiPrio  --- priority of the hwi
+               hwiMode  --- unused
+               hwiHandler --- hwi handler
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T hwiMode,
+                                           HWI_PROC_FUNC hwiHandler,
+                                           HwiIrqParam *irqParam)
+{
+    (VOID)hwiMode;
+    UINTPTR intSave;
+
+    if (hwiHandler == NULL) {
+        return OS_ERRNO_HWI_PROC_FUNC_NULL;
+    }
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+        return OS_ERRNO_HWI_ALREADY_CREATED;
+    }
+
+    if (hwiPrio > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    if (irqParam != NULL) {
+        OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+    } else {
+        OsSetVector(hwiNum, hwiHandler, NULL);
+    }
+#else
+    (VOID)irqParam;
+    OsSetVector(hwiNum, hwiHandler);
+#endif
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function    : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input       : hwiNum   --- hwi num to delete
+               irqParam --- param of the hwi handler
+ Output      : None
+ Return      : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+    (VOID)irqParam;
+    UINT32 intSave;
+
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    intSave = LOS_IntLock();
+
+    g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+
+    LOS_IntRestore(intSave);
+
+    return LOS_OK;
+}
+
+#define FAULT_STATUS_REG_BIT            32
+#define USGFAULT                        (1 << 18)
+#define BUSFAULT                        (1 << 17)
+#define MEMFAULT                        (1 << 16)
+#define DIV0FAULT                       (1 << 4)
+#define HARDFAULT_IRQN                  (-13)
+
+ExcInfo g_excInfo = {0};
+
+UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
+    0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
+    0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
+    0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
+    0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
+};
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcNvicDump(VOID)
+{
+#define OS_NR_NVIC_EXC_DUMP_TYPES   7
+    UINT32 *base = NULL;
+    UINT32 len, i, j;
+    UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
+        OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
+    };
+    UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
+        OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
+        OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
+        OS_NVIC_INT_CTRL_SIZE
+    };
+    CHAR strRgEnable[] = "enable";
+    CHAR strRgPending[] = "pending";
+    CHAR strRgActive[] = "active";
+    CHAR strRgPriority[] = "priority";
+    CHAR strRgException[] = "exception";
+    CHAR strRgShcsr[] = "shcsr";
+    CHAR strRgIntCtrl[] = "control";
+    CHAR *strRgs[] = {
+        strRgEnable, strRgPending, strRgActive, strRgPriority,
+        strRgException, strRgShcsr, strRgIntCtrl
+    };
+
+    PRINTK("\r\nOS exception NVIC dump:\n");
+    for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
+        base = (UINT32 *)rgNvicBases[i];
+        len = rgNvicLens[i];
+        PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
+        len = (len >> 2); /* 2: Gets the next register offset */
+        for (j = 0; j < len; j++) {
+            PRINTK("0x%x ", *(base + j));
+            if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
+                PRINTK("\n");
+            }
+        }
+        PRINTK("\n");
+    }
+}
+
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+    CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+    PRINTK("Type      = %d\n", excInfo->type);
+    PRINTK("ThrdPid   = %d\n", excInfo->thrdPid);
+    PRINTK("Phase     = %s\n", phaseStr[excInfo->phase]);
+    PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Current task info:\n");
+    if (excInfo->phase == OS_EXC_IN_TASK) {
+        LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+        PRINTK("Task name = %s\n", taskCB->taskName);
+        PRINTK("Task ID   = %d\n", taskCB->taskID);
+        PRINTK("Task SP   = %p\n", taskCB->stackPointer);
+        PRINTK("Task ST   = 0x%x\n", taskCB->topOfStack);
+        PRINTK("Task SS   = 0x%x\n", taskCB->stackSize);
+    } else if (excInfo->phase == OS_EXC_IN_HWI) {
+        PRINTK("Exception occur in interrupt phase!\n");
+    } else {
+        PRINTK("Exception occur in system init phase!\n");
+    }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+    PRINTK("Exception reg dump:\n");
+    PRINTK("PC        = 0x%x\n", excInfo->context->uwPC);
+    PRINTK("LR        = 0x%x\n", excInfo->context->uwLR);
+    PRINTK("SP        = 0x%x\n", excInfo->context->uwSP);
+    PRINTK("R0        = 0x%x\n", excInfo->context->uwR0);
+    PRINTK("R1        = 0x%x\n", excInfo->context->uwR1);
+    PRINTK("R2        = 0x%x\n", excInfo->context->uwR2);
+    PRINTK("R3        = 0x%x\n", excInfo->context->uwR3);
+    PRINTK("R4        = 0x%x\n", excInfo->context->uwR4);
+    PRINTK("R5        = 0x%x\n", excInfo->context->uwR5);
+    PRINTK("R6        = 0x%x\n", excInfo->context->uwR6);
+    PRINTK("R7        = 0x%x\n", excInfo->context->uwR7);
+    PRINTK("R8        = 0x%x\n", excInfo->context->uwR8);
+    PRINTK("R9        = 0x%x\n", excInfo->context->uwR9);
+    PRINTK("R10       = 0x%x\n", excInfo->context->uwR10);
+    PRINTK("R11       = 0x%x\n", excInfo->context->uwR11);
+    PRINTK("R12       = 0x%x\n", excInfo->context->uwR12);
+    PRINTK("PriMask   = 0x%x\n", excInfo->context->uwPriMask);
+    PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+    UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+    UINT32 index;
+
+    OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
+
+    PRINTK("----- backtrace start -----\n");
+    for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+        if (LR[index] == 0) {
+            break;
+        }
+        PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
+    }
+    PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+    PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+    MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+    UINT32 errCnt;
+    UINT32 i;
+
+    (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+    errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+    if (errCnt < OS_SYS_MEM_NUM) {
+        errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+    }
+
+    if (errCnt == 0) {
+        PRINTK("all memory pool check passed!\n");
+        return;
+    }
+
+    for (i = 0; i < errCnt; i++) {
+        PRINTK("pool num    = %d\n", i);
+        PRINTK("pool type   = %d\n", memExcInfo[i].type);
+        PRINTK("pool addr   = 0x%x\n", memExcInfo[i].startAddr);
+        PRINTK("pool size   = 0x%x\n", memExcInfo[i].size);
+        PRINTK("pool free   = 0x%x\n", memExcInfo[i].free);
+        PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
+        PRINTK("pool error node addr  = 0x%x\n", memExcInfo[i].errorAddr);
+        PRINTK("pool error node len   = 0x%x\n", memExcInfo[i].errorLen);
+        PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
+    }
+#endif
+    UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+    if (ret == LOS_OK) {
+        PRINTK("system heap memcheck over, all passed!\n");
+    }
+
+    PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+    PRINTK("*************Exception Information**************\n");
+    OsExcTypeInfo(excInfo);
+    OsExcCurTaskInfo(excInfo);
+    OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+    OsExcBackTraceInfo(excInfo);
+#endif
+    OsGetAllTskInfo();
+    OsExcNvicDump();
+    OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+    UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
+    g_intCount++;
+    g_excInfo.nestCnt++;
+
+    g_excInfo.type = excType & OS_NULL_SHORT;
+
+    if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
+        g_excInfo.faultAddr = faultAddr;
+    } else {
+        g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+    }
+    if (g_losTask.runTask != NULL) {
+        if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
+            g_excInfo.phase = OS_EXC_IN_HWI;
+            g_excInfo.thrdPid = pid;
+        } else {
+            g_excInfo.phase = OS_EXC_IN_TASK;
+            g_excInfo.thrdPid = g_losTask.runTask->taskID;
+        }
+    } else {
+        g_excInfo.phase = OS_EXC_IN_INIT;
+        g_excInfo.thrdPid = OS_NULL_INT;
+    }
+    if (excType & OS_EXC_FLAG_NO_FLOAT) {
+        g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
+    } else {
+        g_excInfo.context = excBufAddr;
+    }
+
+    OsDoExcHook(EXC_INTERRUPT);
+    OsExcInfoDisplay(&g_excInfo);
+    ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function    : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+    UINT32 index;
+    g_hwiForm[0] = 0;             /* [0] Top of Stack */
+    g_hwiForm[1] = Reset_Handler; /* [1] reset */
+    for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
+        g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+    }
+    /* Exception handler register */
+    g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT]   = HalExcNMI;
+    g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT]        = HalExcHardFault;
+    g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = HalExcMemFault;
+    g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT]         = HalExcBusFault;
+    g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT]       = HalExcUsageFault;
+    g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT]           = HalSVCHandler;
+    g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT]           = HalPendSV;
+    g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT]          = SysTick_Handler;
+
+    /* Interrupt vector table location */
+    SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
+#endif
+#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
+    NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
+#endif
+
+    /* Enable USGFAULT, BUSFAULT, MEMFAULT */
+    *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+    /* Enable DIV 0 and unaligned exception */
+    *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
+
+    return;
+}
+

arch/arm/cortex-m33/iar/TZ/non_secure/los_timer.c

@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "los_tick.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+    UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
+
+    tick->freq = OS_SYS_CLOCK;
+
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
+#else
+    OsSetVector(tick->irqNum, handler);
+#endif
+#endif
+
+    ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
+    if (ret == 1) {
+        return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
+    }
+
+    return LOS_OK;
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+    if (nextResponseTime > g_archTickTimer.periodMax) {
+        nextResponseTime = g_archTickTimer.periodMax;
+    }
+
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
+    SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+    NVIC_ClearPendingIRQ(SysTick_IRQn);
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+    UINT32 hwCycle = 0;
+    UINTPTR intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
+    *period = SysTick->LOAD;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
+    LOS_IntRestore(intSave);
+    return (UINT64)hwCycle;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return LOS_OK;
+}

arch/arm/cortex-m33/iar/TZ/non_secure/los_trustzone.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_trustzone.h"
+#include "los_secure_macros.h"
+#include "los_secure_context.h"
+#include "los_debug.h"
+#include "los_arch_context.h"
+#include "los_interrupt.h"
+
+OsSecureContext *g_secureContext = NULL;
+
+VOID HalSecureSVCHandler(UINT32 svcID, UINTPTR arg)
+{
+    switch (svcID) {
+        case OS_SVC_START_SCHEDULE:
+            HalSecureContextInit();
+            HalStartFirstTask();
+            break;
+        case OS_SVC_ALLOCATE_SECURE_CONTEXT:
+            g_secureContext = HalSecureContextAlloc(arg);
+            LOS_ASSERT(g_secureContext != NULL);
+            HalSecureContextLoad(g_secureContext);
+            break;
+        case OS_SVC_FREE_SECURE_CONTEXT:
+            HalSecureContextFree(g_secureContext);
+            break;
+        default:
+            PRINT_ERR("Incorrect svc id = %u\n", svcID);
+            break;
+    }
+}
+
+VOID HalStartToRun(VOID)
+{
+    HalSVCStartSchedule();
+}
+
+VOID LOS_SecureContextAlloc(UINT32 secureStackSize)
+{
+    if (secureStackSize == 0) {
+        return;
+    }
+
+    LOS_ASSERT((__get_IPSR() == 0) && (__get_PRIMASK() == 0));
+    secureStackSize = LOS_Align(secureStackSize, sizeof(UINTPTR));
+    HalSVCSecureContextAlloc(secureStackSize);
+}
+
+VOID LOS_SecureContextFree(VOID)
+{
+    HalSVCSecureContextFree();
+}
+

arch/arm/cortex-m33/iar/TZ/non_secure/los_trustzone.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_TRUSTZONE_H
+#define _LOS_TRUSTZONE_H
+
+#include "los_config.h"
+#include "los_task.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+extern VOID LOS_SecureContextAlloc(UINT32 secureStackSize);
+extern VOID LOS_SecureContextFree(VOID);
+
+extern VOID HalStartFirstTask(VOID);
+extern VOID HalSVCStartSchedule(VOID);
+extern VOID HalSVCSecureContextAlloc(UINT32 secureStackSize);
+extern VOID HalSVCSecureContextFree(VOID);
+extern VOID HalSVCHandler(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif
+

arch/arm/cortex-m33/iar/TZ/secure/los_secure_context.c

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_secure_context.h"
+#include "los_secure_macros.h"
+#include "los_secure_heap.h"
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextInit(VOID)
+{
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return;
+    }
+
+    HalSecureContextInitAsm();
+}
+
+OS_CMSE_NS_ENTRY OsSecureContext *HalSecureContextAlloc(UINT32 size)
+{
+    OsSecureContext *secureContext = NULL;
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return NULL;
+    }
+
+    secureContext = HalSecureMalloc(sizeof(OsSecureContext));
+    if (secureContext == NULL) {
+        return NULL;
+    }
+
+    secureContext->stackLimit = HalSecureMalloc(size);
+    if (secureContext->stackLimit == NULL) {
+        HalSecureFree(secureContext);
+        return NULL;
+    }
+
+    secureContext->stackStart = secureContext->stackLimit + size;
+    secureContext->curStackPointer = secureContext->stackStart;
+
+    return secureContext;
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextFree(OsSecureContext *secureContext)
+{
+    UINT32 ipsr;
+
+    OS_IPSR_READ(ipsr);
+    if (!ipsr) {
+        return;
+    }
+
+    HalSecureFree(secureContext->stackLimit);
+    secureContext->stackLimit = NULL;
+    HalSecureFree(secureContext);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextLoad(OsSecureContext *secureContext)
+{
+    HalSecureContextLoadAsm(secureContext);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureContextSave(OsSecureContext *secureContext)
+{
+    HalSecureContextSaveAsm(secureContext);
+}
+

arch/arm/cortex-m33/iar/TZ/secure/los_secure_context.h

@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -29,25 +29,10 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _LOS_MEMBOX_PRI_H
-#define _LOS_MEMBOX_PRI_H
-
-#include "los_membox.h"
-
-#define OS_MEMBOX_NEXT(addr, blkSize) (LOS_MEMBOX_NODE *)((UINT8 *)(addr) + (blkSize))
-
-#ifdef LOS_MEMBOX_CHECK
-#define OS_MEMBOX_MAGIC 0xa55a5aa5
-#define OS_MEMBOX_SET_MAGIC(addr) (*((UINT32 *)(addr)) = OS_MEMBOX_MAGIC)
-#define OS_MEMBOX_CHECK_MAGIC(addr) ((*((UINT32 *)(addr)) == OS_MEMBOX_MAGIC) ? LOS_OK : LOS_NOK)
-#else
-#define OS_MEMBOX_SET_MAGIC(addr)
-#define OS_MEMBOX_CHECK_MAGIC(addr) LOS_OK
-#endif
-
-#define OS_MEMBOX_USER_ADDR(addr) ((VOID *)((UINT8 *)(addr) + LOS_MEMBOX_MAGIC_SIZE))
-#define OS_MEMBOX_NODE_ADDR(addr) ((LOS_MEMBOX_NODE *)((UINT8 *)(addr) - LOS_MEMBOX_MAGIC_SIZE))
+#ifndef _LOS_SECURE_CONTEXT_H
+#define _LOS_SECURE_CONTEXT_H
 
+#include "los_config.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -55,6 +40,21 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+typedef struct {
+    UINT8 *curStackPointer;
+    UINT8 *stackLimit;
+    UINT8 *stackStart;
+} OsSecureContext;
+
+extern VOID HalSecureContextInit(VOID);
+extern OsSecureContext *HalSecureContextAlloc(UINT32 size);
+extern VOID HalSecureContextFree(OsSecureContext *secureContext);
+extern VOID HalSecureContextLoad(OsSecureContext *secureContext);
+extern VOID HalSecureContextSave(OsSecureContext *secureContext);
+
+extern VOID HalSecureContextInitAsm(VOID);
+extern VOID HalSecureContextLoadAsm(OsSecureContext *secureContext);
+extern VOID HalSecureContextSaveAsm(OsSecureContext *secureContext);
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -62,4 +62,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-#endif /* _LOS_MEMBOX_PRI_H */
+#endif
+
+

arch/arm/cortex-m33/iar/TZ/secure/los_secure_context_asm.S

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    PRESERVE8
+
+    EXPORT HalSecureContextInitAsm
+    EXPORT HalSecureContextLoadAsm
+    EXPORT HalSecureContextSaveAsm
+
+OS_SECURE_SCB_AIRCR     EQU     0xE000ED0C
+
+    SECTION     .text:CODE(2)
+    THUMB
+    REQUIRE8
+
+HalSecureContextInitAsm
+    LDR     R0, =OS_SECURE_SCB_AIRCR
+    LDR     R1, [R0]
+
+    MOV     R2, #0xFFFF
+    LSL     R2, R2, #16
+    BIC     R1, R1, R2
+    MOV     R2, #0x05FA
+    LSL     R2, R2, #16
+    ORR     R1, R1, R2
+
+    BIC     R1, R1, #0x4000
+    MOV     R2, #0x4000
+    ORR     R1, R1, R2
+    STR     R1, [R0]
+
+    MOV     R0, #0
+    MSR     PSPLIM, R0
+    MSR     PSP, R0
+    MOV     R0, #2
+    MSR     CONTROL, R0 
+    BX      LR
+
+HalSecureContextLoadAsm
+    MRS     R1, IPSR
+    CBZ     R1, __ThreadMode
+
+    LDMIA   R0!, {R1, R2}               /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext->stackLimit. */
+    MSR     PSPLIM, R2                  /* Restore PSPLIM. */
+    MSR     PSP, R1                     /* Restore PSP. */
+    BX      LR
+
+HalSecureContextSaveAsm
+    MRS     R0, IPSR
+    CBZ     R0, __ThreadMode
+
+    MRS     R0, PSP
+    STR     R0, [R1]                    /* g_secureContext->curStackPointer = R0. */
+    MOV     R0, #0
+    MSR     PSPLIM, R0                  /* No PSPLIM for the current task. */
+    MSR     PSP, R0                     /* No secure stack for the current task. */
+
+__ThreadMode
+    BX      LR
+
+    END

arch/arm/cortex-m33/iar/TZ/secure/los_secure_heap.c

@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_secure_heap.h"
+#include "los_secure_macros.h"
+#include "los_config.h"
+#include "los_list.h"
+
+#pragma data_alignment=0x4
+STATIC UINT8 g_secureHeap[LOSCFG_SECURE_HEAP_SIZE] = {0};
+STATIC LOS_DL_LIST g_secureHeapFreeList = {NULL, NULL};
+
+struct OsSecureHeapNode {
+    LOS_DL_LIST freeNode;
+    struct OsSecureHeapNode *preNode;
+    UINT32 size : 24;
+    UINT32 used : 8;
+};
+
+#define OS_SECURE_HEAP_NODE_HEAD_SIZE   sizeof(struct OsSecureHeapNode)
+#define OS_SECURE_HEAP_ALIGN_SIZE       sizeof(UINTPTR)
+
+#define OS_SECURE_HEAP_NODE_USED        1
+#define OS_SECURE_HEAP_NODE_FREE        0
+
+#define OS_SECURE_HEAP_FIRST_NODE     ((struct OsSecureHeapNode *)g_secureHeap)
+#define OS_SECURE_HEAP_NEXT_NODE(node) \
+    ((struct OsSecureHeapNode *)((UINT8 *)(node) + (node)->size))
+#define OS_SECURE_HEAP_END_NODE \
+    ((struct OsSecureHeapNode *)((UINT8 *)g_secureHeap + LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE))
+
+STATIC INLINE VOID OsSecureHeapListInit(LOS_DL_LIST *head)
+{
+    head->pstPrev = head;
+    head->pstNext = head;
+}
+
+STATIC INLINE VOID OsSecureHeapListDelete(LOS_DL_LIST *node)
+{
+    node->pstNext->pstPrev = node->pstPrev;
+    node->pstPrev->pstNext = node->pstNext;
+    node->pstNext = NULL;
+    node->pstPrev = NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapListAdd(LOS_DL_LIST *listNode, LOS_DL_LIST *node)
+{
+    node->pstNext = listNode->pstNext;
+    node->pstPrev = listNode;
+    listNode->pstNext->pstPrev = node;
+    listNode->pstNext = node;
+}
+
+STATIC struct OsSecureHeapNode *OsSecureHeapFindSuitableFreeBlock(UINT32 allocSize)
+{
+    LOS_DL_LIST *listNodeHead = &g_secureHeapFreeList;
+    struct OsSecureHeapNode *tmpNode = NULL;
+
+    LOS_DL_LIST_FOR_EACH_ENTRY(tmpNode, listNodeHead, struct OsSecureHeapNode, freeNode) {
+        if (tmpNode->size >= allocSize) {
+            return tmpNode;
+        }
+    }
+
+    return NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapClearNode(struct OsSecureHeapNode *node)
+{
+    node->preNode = NULL;
+    node->size = 0;
+    node->used = 0;
+    node->freeNode.pstPrev = NULL;
+    node->freeNode.pstNext = NULL;
+}
+
+STATIC INLINE VOID OsSecureHeapMergeNode(struct OsSecureHeapNode *node)
+{
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    node->preNode->size += node->size;
+    nextNode = (struct OsSecureHeapNode *)((UINTPTR)node + node->size);
+    nextNode->preNode = node->preNode;
+    OsSecureHeapClearNode(node);
+}
+
+STATIC INLINE VOID OsSecureHeapSplitNode(struct OsSecureHeapNode *allocNode, UINT32 allocSize)
+{
+    struct OsSecureHeapNode *newFreeNode = NULL;
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    newFreeNode = (struct OsSecureHeapNode *)((UINT8 *)allocNode + allocSize);
+    newFreeNode->preNode = allocNode;
+    newFreeNode->size = allocNode->size - allocSize;
+    newFreeNode->used = OS_SECURE_HEAP_NODE_FREE;
+    allocNode->size = allocSize;
+    nextNode = OS_SECURE_HEAP_NEXT_NODE(newFreeNode);
+    nextNode->preNode = newFreeNode;
+    if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+        OsSecureHeapListDelete(&nextNode->freeNode);
+        OsSecureHeapMergeNode(nextNode);
+    }
+
+    OsSecureHeapListAdd(&g_secureHeapFreeList, &newFreeNode->freeNode);
+}
+
+STATIC INLINE VOID OsSecureHeapFreeNode(struct OsSecureHeapNode *node)
+{
+    struct OsSecureHeapNode *nextNode = NULL;
+
+    if ((node->preNode != NULL) && (node->preNode->used == OS_SECURE_HEAP_NODE_FREE)) {
+        struct OsSecureHeapNode *preNode = node->preNode;
+        OsSecureHeapMergeNode(node);
+        nextNode = OS_SECURE_HEAP_NEXT_NODE(preNode);
+        if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+            OsSecureHeapListDelete(&nextNode->freeNode);
+            OsSecureHeapMergeNode(nextNode);
+        }
+
+        OsSecureHeapListDelete(&preNode->freeNode);
+        preNode->used = OS_SECURE_HEAP_NODE_FREE;
+        OsSecureHeapListAdd(&g_secureHeapFreeList, &preNode->freeNode);
+    } else {
+        nextNode = OS_SECURE_HEAP_NEXT_NODE(node);
+        if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
+            OsSecureHeapListDelete(&nextNode->freeNode);
+            OsSecureHeapMergeNode(nextNode);
+        }
+
+        node->used = OS_SECURE_HEAP_NODE_FREE;
+        OsSecureHeapListAdd(&g_secureHeapFreeList, &node->freeNode);
+    }
+}
+
+STATIC INLINE VOID *OsSecureHeapAllocNode(UINT32 size)
+{
+    struct OsSecureHeapNode *allocNode = NULL;
+    UINT32 allocSize;
+
+    allocSize = LOS_Align(size + OS_SECURE_HEAP_NODE_HEAD_SIZE, OS_SECURE_HEAP_ALIGN_SIZE);
+    allocNode = OsSecureHeapFindSuitableFreeBlock(allocSize);
+    if (allocNode == NULL) {
+        return NULL;
+    }
+    if ((allocSize + OS_SECURE_HEAP_NODE_HEAD_SIZE + OS_SECURE_HEAP_ALIGN_SIZE) <= allocNode->size) {
+        OsSecureHeapSplitNode(allocNode, allocSize);
+    }
+    OsSecureHeapListDelete(&allocNode->freeNode);
+    allocNode->used = OS_SECURE_HEAP_NODE_USED;
+
+    return (allocNode + 1);
+}
+
+STATIC INLINE VOID OsSecureHeapInit(VOID)
+{
+    struct OsSecureHeapNode *newNode = NULL;
+    struct OsSecureHeapNode *endNode = NULL;
+
+    newNode = OS_SECURE_HEAP_FIRST_NODE;
+    newNode->size = LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE;
+    newNode->preNode = OS_SECURE_HEAP_END_NODE;
+    newNode->used = OS_SECURE_HEAP_NODE_FREE;
+
+    OsSecureHeapListInit(&g_secureHeapFreeList);
+    OsSecureHeapListAdd(&g_secureHeapFreeList, &newNode->freeNode);
+
+    endNode = OS_SECURE_HEAP_END_NODE;
+    endNode->preNode = newNode;
+    endNode->size = OS_SECURE_HEAP_NODE_HEAD_SIZE;
+    endNode->used = OS_SECURE_HEAP_NODE_USED;
+}
+
+OS_CMSE_NS_ENTRY VOID *HalSecureMalloc(UINT32 size)
+{
+    if (size == 0) {
+        return NULL;
+    }
+
+    if ((g_secureHeapFreeList.pstPrev == NULL) &&
+        (g_secureHeapFreeList.pstNext == NULL)) {
+        OsSecureHeapInit();
+    }
+
+    return OsSecureHeapAllocNode(size);
+}
+
+OS_CMSE_NS_ENTRY VOID HalSecureFree(VOID *ptr)
+{
+    struct OsSecureHeapNode *node = NULL;
+
+    if (ptr == NULL) {
+        return;
+    }
+
+    node = (struct OsSecureHeapNode *)((UINTPTR)ptr - OS_SECURE_HEAP_NODE_HEAD_SIZE);
+    if (node->used != OS_SECURE_HEAP_NODE_USED) {
+        return;
+    }
+
+    OsSecureHeapFreeNode(node);
+}
+

arch/arm/cortex-m33/iar/TZ/secure/los_secure_heap.h

@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2013-2019, Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020, Huawei Device Co., Ltd. All rights reserved.
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -29,15 +29,10 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/**
- * @defgroup los_slab Slab
- * @ingroup kernel
- */
+#ifndef _LOS_SECURE_HEAP_H
+#define _LOS_SECURE_HEAP_H
 
-#ifndef _LOS_SLAB_H
-#define _LOS_SLAB_H
-
-#include <los_typedef.h>
+#include "los_config.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -45,16 +40,8 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-// number of slab class
-#define SLAB_MEM_COUNT              4
-
-// step size of each class
-#define SLAB_MEM_CALSS_STEP_SIZE    0x10
-
-// max size of each class
-#define SLAB_MEM_ALLOCATOR_SIZE     512
-
-#define SLAB_BASIC_NEED_SIZE        0x1000
+VOID *HalSecureMalloc(UINT32 size);
+VOID HalSecureFree(VOID *ptr);
 
 #ifdef __cplusplus
 #if __cplusplus