commit
fe06d0cbb9
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@ -67,7 +67,7 @@ static_library("kernel") {
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} else {
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deps = [ "arch/arm/cortex-m33/gcc/NTZ:arch" ]
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}
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} else if ("$board_cpu" == "ck802") {
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} else if ("$board_cpu" == "ck802" || "$board_cpu" == "e802") {
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deps = [ "arch/csky/v2/gcc:arch" ]
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} else if ("$board_cpu" == "") {
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if ("$board_arch" == "rv32imac" || "$board_arch" == "rv32imafdc") {
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@ -145,7 +145,6 @@ VOID HalTaskSchedule(VOID)
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BOOL isSwitch = OsSchedTaskSwitch();
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if (isSwitch) {
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HalTaskContextSwitch();
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return;
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}
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LOS_IntRestore(intSave);
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return;
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@ -56,6 +56,7 @@
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#define OS_USER_HWI_MIN 0
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#define OS_USER_HWI_MAX (LOSCFG_PLATFORM_HWI_LIMIT - 1)
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#define HWI_ALIGNSIZE 0x400
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UINT32 g_intCount = 0;
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CHAR g_trapStackBase[OS_TRAP_STACK_SIZE];
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@ -92,7 +93,7 @@ UINT32 HalIntLock(VOID)
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return intSave;
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}
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UINT32 HalIntUnlock(VOID)
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UINT32 HalIntUnLock(VOID)
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{
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UINT32 intSave;
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__asm__ __volatile__(
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@ -181,7 +182,7 @@ UINT32 HalIrqClear(UINT32 hwiNum)
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* @ingroup los_hwi
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* Hardware interrupt form mapping handling function array.
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*/
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STATIC HWI_PROC_FUNC __attribute__((aligned(0x100))) g_hwiForm[OS_VECTOR_CNT] = {0};
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STATIC HWI_PROC_FUNC __attribute__((aligned(HWI_ALIGNSIZE))) g_hwiForm[OS_VECTOR_CNT] = {0};
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#if (OS_HWI_WITH_ARG == 1)
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@ -52,8 +52,15 @@ typedef struct {
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UINT32 lbeg;
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UINT32 lend;
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UINT32 lcount;
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UINT32 temp[4];
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UINT32 res[8];
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#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
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UINT32 temp;
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UINT16 cpenable;
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UINT16 cpstored;
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UINT32 fcr;
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UINT32 fsr;
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UINT32 regF[16];
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#endif
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UINT32 res[4];
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} TaskContext;
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#ifdef __cplusplus
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@ -52,8 +52,15 @@ typedef struct {
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UINT32 lbeg;
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UINT32 lend;
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UINT32 lcount;
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UINT32 temp[4];
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UINT32 res[8];
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#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
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UINT32 temp;
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UINT16 cpenable;
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UINT16 cpstored;
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UINT32 fcr;
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UINT32 fsr;
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UINT32 regF[16];
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#endif
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UINT32 res[4];
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} EXC_CONTEXT_S;
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#define VECTOR_START _init_start
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@ -38,7 +38,40 @@ extern "C" {
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#endif /* __cplusplus */
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#endif /* __cplusplus */
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.macro POP_ALL_REG SP
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.macro POP_ALL_REG SP PC PState
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#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
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l16ui a3, \SP, CONTEXT_OFF_CPENABLE
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wsr a3, CPENABLE
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rsync
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l16ui a3, \SP, CONTEXT_OFF_CPSTORED
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bbci.l a3, 0, 2f
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l32i a3, \SP, CONTEXT_OFF_FCR
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wur.FCR a3
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l32i a3, \SP, CONTEXT_OFF_FSR
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wur.FSR a3
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lsi f0, \SP, CONTEXT_OFF_F0
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lsi f1, \SP, CONTEXT_OFF_F1
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lsi f2, \SP, CONTEXT_OFF_F2
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lsi f3, \SP, CONTEXT_OFF_F3
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lsi f4, \SP, CONTEXT_OFF_F4
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lsi f5, \SP, CONTEXT_OFF_F5
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lsi f6, \SP, CONTEXT_OFF_F6
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lsi f7, \SP, CONTEXT_OFF_F7
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lsi f8, \SP, CONTEXT_OFF_F8
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lsi f9, \SP, CONTEXT_OFF_F9
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lsi f10, \SP, CONTEXT_OFF_F10
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lsi f11, \SP, CONTEXT_OFF_F11
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lsi f12, \SP, CONTEXT_OFF_F12
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lsi f13, \SP, CONTEXT_OFF_F13
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lsi f14, \SP, CONTEXT_OFF_F14
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lsi f15, \SP, CONTEXT_OFF_F15
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2:
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movi a4, 0
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s16i a4, \SP, CONTEXT_OFF_CPSTORED
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#endif
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l32i a3, \SP, CONTEXT_OFF_LBEG
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l32i a4, \SP, CONTEXT_OFF_LEND
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wsr a3, LBEG
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@ -62,12 +95,11 @@ extern "C" {
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l32i a14, \SP, CONTEXT_OFF_A14
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l32i a15, \SP, CONTEXT_OFF_A15
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l32i a0, \SP, CONTEXT_OFF_PS
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wsr a0, PS
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wsr a0, \PState
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l32i a0, \SP, CONTEXT_OFF_PC
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wsr a0, EPC1
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wsr a0, \PC
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l32i a0, \SP, CONTEXT_OFF_A0
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l32i a2, \SP, CONTEXT_OFF_A2
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rsync
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.endm
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.macro PUSH_ALL_REG SP
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@ -97,6 +129,36 @@ extern "C" {
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s32i a3, \SP, CONTEXT_OFF_LCOUNT
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rsr a3, PS
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s32i a3, \SP, CONTEXT_OFF_PS
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#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
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rsr a3, CPENABLE
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beqz a3, 1f
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s16i a3, \SP, CONTEXT_OFF_CPSTORED
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s16i a3, \SP, CONTEXT_OFF_CPENABLE
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bbci.l a3, 0, 1f
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rur.FCR a3
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s32i a3, \SP, CONTEXT_OFF_FCR
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rur.FSR a3
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s32i a3, \SP, CONTEXT_OFF_FSR
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ssi f0, \SP, CONTEXT_OFF_F0
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ssi f1, \SP, CONTEXT_OFF_F1
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ssi f2, \SP, CONTEXT_OFF_F2
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ssi f3, \SP, CONTEXT_OFF_F3
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ssi f4, \SP, CONTEXT_OFF_F4
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ssi f5, \SP, CONTEXT_OFF_F5
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ssi f6, \SP, CONTEXT_OFF_F6
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ssi f7, \SP, CONTEXT_OFF_F7
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ssi f8, \SP, CONTEXT_OFF_F8
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ssi f9, \SP, CONTEXT_OFF_F9
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ssi f10, \SP, CONTEXT_OFF_F10
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ssi f11, \SP, CONTEXT_OFF_F11
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ssi f12, \SP, CONTEXT_OFF_F12
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ssi f13, \SP, CONTEXT_OFF_F13
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ssi f14, \SP, CONTEXT_OFF_F14
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ssi f15, \SP, CONTEXT_OFF_F15
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1:
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#endif
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.endm
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#ifdef __cplusplus
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@ -49,7 +49,7 @@ extern "C" {
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#define SPREG_PS_DEPC SPREG_PS_DEPC_MASK
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/* PS register -- interrupt part */
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#define SPREG_PS_DI_SHIFT 3
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#define SPREG_PS_DI_MASK 0x00000008
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#define SPREG_PS_DI_MASK 0x0000000F
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#define SPREG_PS_DI SPREG_PS_DI_MASK
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#define SPREG_PS_DI_DEPC 0x0000000C
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/* PS register -- stack part */
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@ -115,19 +115,41 @@ extern "C" {
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#define CONTEXT_OFF_LBEG 84
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#define CONTEXT_OFF_LEND 88
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#define CONTEXT_OFF_LCOUNT 92
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#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
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#define CONTEXT_OFF_TMP0 96
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#define CONTEXT_OFF_TMP1 100
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#define CONTEXT_OFF_TMP2 104
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#define CONTEXT_OFF_EXIT 108
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#define CONTEXT_SIZE 144
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#define CONTEXT_OFF_CPENABLE 100
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#define CONTEXT_OFF_CPSTORED 102
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#define CONTEXT_OFF_FCR 104
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#define CONTEXT_OFF_FSR 108
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#define CONTEXT_OFF_F0 112
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#define CONTEXT_OFF_F1 116
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#define CONTEXT_OFF_F2 120
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#define CONTEXT_OFF_F3 124
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#define CONTEXT_OFF_F4 128
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#define CONTEXT_OFF_F5 132
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#define CONTEXT_OFF_F6 136
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#define CONTEXT_OFF_F7 140
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#define CONTEXT_OFF_F8 144
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#define CONTEXT_OFF_F9 148
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#define CONTEXT_OFF_F10 152
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#define CONTEXT_OFF_F11 156
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#define CONTEXT_OFF_F12 160
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#define CONTEXT_OFF_F13 164
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#define CONTEXT_OFF_F14 168
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#define CONTEXT_OFF_F15 172
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#define CONTEXT_SIZE 192
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#else
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#define CONTEXT_SIZE 112
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#endif
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#define EXCCAUSE_LEVEL1INTERRUPT 4
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#define XTENSA_LOGREG_NUM 16
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#define INDEX_OF_SP 1
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#define INDEX_OF_ARGS0 6
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#define WINDOWSTARTBITS 16
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#define WINDOWBASEBITS 4
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#define WINDOWSTARTMASK ((1 << WINDOWSTARTBITS) - 1)
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#define WINDOWSTARTBITS 16
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#define WINDOWBASEBITS 4
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#define WINDOWSTARTMASK ((1 << WINDOWSTARTBITS) - 1)
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#define WOE_ENABLE 0x40000
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#define BIT_CALLINC 16
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@ -68,14 +68,28 @@ UINT32 g_stackDefault[] = {
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0x00000000, /* REG_OFF_LCOUNT */
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0x00000000, /* REG_OFF_LEND */
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0x00000000, /* REG_OFF_LBEG */
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0x00000000, /* REG_OFF_TMP */
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0x00000000, /* REG_OFF_TMP */
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0x00000000, /* REG_OFF_TMP */
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0x00000000, /* REG_OFF_TMP */
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0x00000000, /* REG_OFF_SPILL_RESERVED */
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0x00000000, /* REG_OFF_SPILL_RESERVED */
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0x00000000, /* REG_OFF_SPILL_RESERVED */
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0x00000000, /* REG_OFF_SPILL_RESERVED */
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#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
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0x00000000, /* REG_OFF_TMP0 */
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0x00000001, /* REG_OFF_CPENABLE | CONTEXT_OFF_CPSTORED */
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0x00000000, /* REG_OFF_FCR */
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0x00000000, /* REG_OFF_FSR */
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0x00000000, /* REG_OFF_F0 */
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0x00000000, /* REG_OFF_F1 */
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0x00000000, /* REG_OFF_F2 */
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0x00000000, /* REG_OFF_F3 */
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0x00000000, /* REG_OFF_F4 */
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0x00000000, /* REG_OFF_F5 */
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0x00000000, /* REG_OFF_F6 */
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0x00000000, /* REG_OFF_F7 */
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0x00000000, /* REG_OFF_F8 */
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0x00000000, /* REG_OFF_F9 */
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0x00000000, /* REG_OFF_F10 */
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0x00000000, /* REG_OFF_F11 */
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0x00000000, /* REG_OFF_F12 */
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0x00000000, /* REG_OFF_F13 */
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0x00000000, /* REG_OFF_F14 */
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0x00000000, /* REG_OFF_F15 */
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#endif
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0x00000000, /* REG_OFF_SPILL_RESERVED */
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0x00000000, /* REG_OFF_SPILL_RESERVED */
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0x00000000, /* REG_OFF_SPILL_RESERVED */
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@ -157,7 +171,6 @@ VOID HalTaskSchedule(VOID)
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BOOL isSwitch = OsSchedTaskSwitch();
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if (isSwitch) {
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HalTaskContextSwitch();
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return;
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}
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LOS_IntRestore(intSave);
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@ -39,27 +39,27 @@
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.global HalTaskContextSwitch
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HalTaskContextSwitch:
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entry sp, 16
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addi a2, sp, -CONTEXT_SIZE
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PUSH_ALL_REG a2
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call0 SaveRetAddr
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beqi a3, 1, .switchdone
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entry sp, 16
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addi a2, sp, -CONTEXT_SIZE
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PUSH_ALL_REG a2
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call0 SaveRetAddr
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beqi a3, 1, .switchdone
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movi a4, g_losTask
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l32i a5, a4, 0 /* get run task */
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s32i a2, a5, 0 /* store sp */
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s32i a2, a5, 0 /* store sp */
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l32i a5, a4, 4 /* get new task */
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s32i a5, a4, 0 /* run task = new task */
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l32i a4, a5, 0 /* get new sp */
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l32i a4, a5, 0 /* get new sp */
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rsr a5, PS
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movi a3, ~(WOE_ENABLE | LEVEL_MASK)
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and a2, a5, a3
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and a2, a5, a3
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addi a2, a2, 3
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wsr a2, PS
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rsync
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call0 SpillWindow
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mov a2, a4
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POP_ALL_REG a2
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rfe
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POP_ALL_REG a2 EPC5 EPS5
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rfi 5
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.switchdone:
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retw
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@ -68,14 +68,14 @@ HalTaskContextSwitch:
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.global HakSpillWindow
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HakSpillWindow:
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entry sp, 16
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entry sp, 32
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addi a2, sp, -CONTEXT_SIZE
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PUSH_ALL_REG a2
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rsr a5, PS
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movi a3, ~(WOE_ENABLE | LEVEL_MASK) /* disable woe and int */
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and a3, a5, a3
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and a3, a5, a3
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addi a3, a3, LEVEL3
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wsr a3, PS
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rsync
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@ -84,10 +84,10 @@ HakSpillWindow:
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call0 SpillWindow
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l32i a5, a4, CONTEXT_OFF_PS /* restroe PS */
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wsr a5, PS
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wsr a5, PS
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rsync
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l32i a0, a4, CONTEXT_OFF_A0
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l32i a1, a4, CONTEXT_OFF_A1
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l32i a0, a4, CONTEXT_OFF_A0
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l32i a1, a4, CONTEXT_OFF_A1
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retw
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@ -101,7 +101,7 @@ OsStartToRun:
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rsr a4, PS
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movi a3, ~(WOE_ENABLE | LEVEL_MASK)
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and a2, a4, a3
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and a2, a4, a3
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addi a2, a2, LEVEL3
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wsr a2, PS
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rsync
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@ -111,8 +111,8 @@ OsStartToRun:
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call0 SpillWindow
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mov a2, a5
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POP_ALL_REG a2
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rfe
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POP_ALL_REG a2 EPC5 EPS5
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rfi 5
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.global SaveRetAddr
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.type SaveRetAddr, @function
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@ -121,8 +121,8 @@ OsStartToRun:
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SaveRetAddr:
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movi a3, 1
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s32i a3, a2, CONTEXT_OFF_A3
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s32i a0, a2, CONTEXT_OFF_PC /* save pc */
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movi a3, 1
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s32i a3, a2, CONTEXT_OFF_A3
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s32i a0, a2, CONTEXT_OFF_PC /* save pc */
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movi a3, 0
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ret
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@ -177,7 +177,7 @@ InterruptEntry1:
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call4 HalInterrupt
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mov a2, a1
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POP_ALL_REG a2
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POP_ALL_REG a2 EPC1 PS
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rfe
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.begin literal_prefix .InterruptEntry2
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@ -294,7 +294,7 @@ UnderFlowGroup2:
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l32i a3, a9, 12
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l32i a2, a9, 8
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l32i a1, a9, 4
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l32i a0, a9, 0
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l32i a0, a9, 0
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addi a9, a9, 16
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addi a1, a1, -12
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@ -329,7 +329,7 @@ OverFlowGroup3:
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s32i a10, a0, 24
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s32i a9, a0, 20
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s32i a8, a0, 16
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s32i a7, a0, 12
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s32i a7, a0, 12
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s32i a6, a0, 8
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s32i a5, a0, 4
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s32i a4, a0, 0
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@ -343,7 +343,7 @@ UnderFlowGroup3:
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l32i a3, a13, 12
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l32i a2, a13, 8
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l32i a1, a13, 4
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l32i a0, a13, 0
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l32i a0, a13, 0
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addi a13, a13, 16
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addi a1, a1, -12
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@ -355,8 +355,16 @@ UnderFlowGroup3:
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l32i a10, a0, 24
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l32i a9, a0, 20
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l32i a8, a0, 16
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l32i a7, a4, 12
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l32i a7, a4, 12
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l32i a6, a4, 8
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l32i a5, a4, 4
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l32i a4, a4, 0
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rfwu
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.global EnableExceptionInterface
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.section .iram,"ax"
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.type EnableExceptionInterface,@function
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.align 4
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EnableExceptionInterface:
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entry a1,16
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retw
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@ -544,6 +544,7 @@ WEAK VOID __stack_chk_fail(VOID)
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**************************************************************************** */
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VOID HalHwiInit(VOID)
|
||||
{
|
||||
EnableExceptionInterface();
|
||||
for (UINT32 i = 0; i < OS_HWI_MAX_NUM; i++) {
|
||||
g_hwiForm[i + OS_SYS_VECTOR_CNT] = HalHwiDefaultHandler;
|
||||
HalIrqMask(i);
|
||||
|
@ -551,4 +552,3 @@ VOID HalHwiInit(VOID)
|
|||
asm volatile ("wsr %0, vecbase" : : "r"(INIT_VECTOR_START));
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
@ -38,14 +38,10 @@
|
|||
#include "los_sched.h"
|
||||
#include "los_debug.h"
|
||||
|
||||
#define OVERFLOW_MAX 0xFFFFFFFF
|
||||
|
||||
UINT32 GetCcount(VOID)
|
||||
{
|
||||
UINT32 intSave;
|
||||
|
||||
__asm__ __volatile__("rsr %0, ccount" : "=a"(intSave) :);
|
||||
|
||||
return intSave;
|
||||
}
|
||||
|
||||
|
@ -57,9 +53,7 @@ VOID ResetCcount(VOID)
|
|||
UINT32 GetCcompare(VOID)
|
||||
{
|
||||
UINT32 intSave;
|
||||
|
||||
__asm__ __volatile__("rsr %0, ccompare0" : "=a"(intSave) :);
|
||||
|
||||
return intSave;
|
||||
}
|
||||
|
||||
|
@ -68,12 +62,6 @@ VOID SetCcompare(UINT32 newCompareVal)
|
|||
__asm__ __volatile__("wsr %0, ccompare0; rsync" : : "a"(newCompareVal));
|
||||
}
|
||||
|
||||
VOID HalUpdateTimerCmpVal(UINT32 newCompareVal)
|
||||
{
|
||||
SetCcompare(newCompareVal);
|
||||
ResetCcount();
|
||||
}
|
||||
|
||||
/* ****************************************************************************
|
||||
Function : HalTickStart
|
||||
Description : Configure Tick Interrupt Start
|
||||
|
@ -104,8 +92,8 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
|
|||
g_sysClock = OS_SYS_CLOCK;
|
||||
g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
|
||||
|
||||
SetCcompare(g_cyclesPerTick);
|
||||
ResetCcount();
|
||||
SetCcompare(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
|
||||
|
||||
__asm__ __volatile__("wsr %0, ccompare1; rsync" : : "a"(0));
|
||||
__asm__ __volatile__("wsr %0, ccompare2; rsync" : : "a"(0));
|
||||
|
@ -116,20 +104,32 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
|
|||
|
||||
WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
|
||||
{
|
||||
HalUpdateTimerCmpVal(nextResponseTime);
|
||||
UINT32 timerL;
|
||||
timerL = GetCcount();
|
||||
timerL += nextResponseTime;
|
||||
SetCcompare(timerL);
|
||||
}
|
||||
|
||||
WEAK UINT64 HalGetTickCycle(UINT32 *period)
|
||||
{
|
||||
UINT32 ccount;
|
||||
UINT32 intSave = LOS_IntLock();
|
||||
UINT32 tickCycleH;
|
||||
UINT32 tickCycleL;
|
||||
UINT32 temp;
|
||||
static UINT64 tickCycle = 0;
|
||||
|
||||
ccount = GetCcount();
|
||||
*period = g_cyclesPerTick;
|
||||
(VOID)period;
|
||||
UINT32 intSave = LOS_IntLock();
|
||||
temp = tickCycle & 0xFFFFFFFF;
|
||||
tickCycleH = tickCycle >> SHIFT_32_BIT;
|
||||
tickCycleL = GetCcount();
|
||||
if (tickCycleL < temp) {
|
||||
tickCycleH++;
|
||||
}
|
||||
tickCycle = (((UINT64)tickCycleH) << SHIFT_32_BIT) | tickCycleL;
|
||||
|
||||
LOS_IntRestore(intSave);
|
||||
|
||||
return ccount;
|
||||
return tickCycle;
|
||||
}
|
||||
|
||||
WEAK VOID HalTickLock(VOID)
|
||||
|
|
|
@ -158,13 +158,13 @@ SpillWindow:
|
|||
or a2, a2, a3
|
||||
rsr a3, WINDOWBASE
|
||||
|
||||
1:
|
||||
bbsi.l a2, WINDOWSTARTBITS-1, 2f
|
||||
.RestoreWindowBase:
|
||||
bbsi.l a2, WINDOWSTARTBITS - 1, .RestoreWindow
|
||||
slli a2, a2, 1
|
||||
addi a3, a3, -1
|
||||
j 1b
|
||||
j .RestoreWindowBase
|
||||
|
||||
2:
|
||||
.RestoreWindow:
|
||||
extui a3, a3, 0, WINDOWSTARTBITS /* the original bit */
|
||||
|
||||
addi a3, a3, 1
|
||||
|
|
Loading…
Reference in New Issue