riscv-lab/chisel
Liphen e1639e6f8b fix(tlb): 修复数据宽度问题 2023-12-25 14:01:31 +08:00
..
difftest@c84c78ef6d docs: 增加AXI文档 2023-12-23 20:44:37 +08:00
playground fix(tlb): 修复数据宽度问题 2023-12-25 14:01:31 +08:00
.gitignore Add Signal.md to playground/doc directory 2023-12-10 22:33:46 +08:00
.scalafmt.conf 增加指令定义 2023-11-16 16:17:49 +08:00
Makefile Add count target to Makefile 2023-12-13 14:19:53 +08:00
README.md 增加chisel框架 2023-11-07 13:41:15 +08:00
build.sc fix: 修复了不能生成代码的问题 2023-11-07 18:42:06 +08:00

README.md

Chisel Project Template

Another version of the Chisel template supporting mill. mill is another Scala/Java build tool without obscure DSL like SBT. It is much faster than SBT.

Contents at a glance:

  • .gitignore - helps Git ignore junk like generated files, build products, and temporary files.
  • build.sc - instructs mill to build the Chisel project
  • Makefile - rules to call mill
  • playground/src/GCD.scala - GCD source file
  • playground/src/DecoupledGCD.scala - another GCD source file
  • playground/src/Elaborate.scala - wrapper file to call chisel command with the GCD module
  • playground/test/src/GCDSpec.scala - GCD tester

Feel free to rename or delete files under playground/ or use them as a reference/template.

Getting Started

First, install mill by referring to the documentation here.

To run all tests in this design (recommended for test-driven development):

make test

To generate Verilog:

make verilog

Change FIRRTL Compiler

You can change the FIRRTL compiler between SFC (Scala-based FIRRTL compiler) and MFC (MLIR-based FIRRTL compiler) by modifying the useMFC variable in playground/src/Elaborate.scala. The latter one requires firtool, which is included under utils/.