增加指令定义
This commit is contained in:
Liphen
parent
9d777a6a13
commit
dafbea5ee6
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@ -18,6 +18,9 @@ align.tokens.add = [
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},
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{
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code = "="
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},
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{
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code = "->"
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}
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]
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@ -3,19 +3,20 @@ package cpu
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import chisel3.util._
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case class CpuConfig(
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val build: Boolean = false, // 是否为build模式
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val hasCommitBuffer: Boolean = false, // 是否有提交缓存
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val decoderNum: Int = 1, // 同时访问寄存器的指令数
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val commitNum: Int = 1, // 同时提交的指令数
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val fuNum: Int = 1, // 功能单元数
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val instFetchNum: Int = 1, // iCache取到的指令数量
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val instFifoDepth: Int = 8, // 指令缓存深度
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val mulClockNum: Int = 2, // 乘法器的时钟周期数
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val divClockNum: Int = 8, // 除法器的时钟周期数
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val branchPredictor: String = "adaptive",// adaptive, pesudo, global
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val build: Boolean = false, // 是否为build模式
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val isRV32: Boolean = false, // 是否为RV32
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val hasMDU: Boolean = false, // 是否有乘除法单元
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val hasCommitBuffer: Boolean = false, // 是否有提交缓存
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val decoderNum: Int = 1, // 同时访问寄存器的指令数
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val commitNum: Int = 1, // 同时提交的指令数
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val fuNum: Int = 1, // 功能单元数
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val instFetchNum: Int = 1, // iCache取到的指令数量
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val instFifoDepth: Int = 8, // 指令缓存深度
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val mulClockNum: Int = 2, // 乘法器的时钟周期数
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val divClockNum: Int = 8, // 除法器的时钟周期数
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val branchPredictor: String = "adaptive" // adaptive, pesudo, global
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)
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case class BranchPredictorConfig(
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val bhtDepth: Int = 5,
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val phtDepth: Int = 6,
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)
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val bhtDepth: Int = 5,
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val phtDepth: Int = 6)
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@ -2,266 +2,229 @@ package cpu.defines
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import chisel3._
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import chisel3.util._
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import cpu.defines.Instructions
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import cpu.CpuConfig
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trait Constants {
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val config = new CpuConfig
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val XLEN = 64
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trait CoreParameter {
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def config = new CpuConfig
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val XLEN = if (config.isRV32) 32 else 64
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}
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trait Constants extends CoreParameter {
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def config = new CpuConfig
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// 全局
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val PC_WID = XLEN
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val PC_INIT = "h60000000".U(PC_WID.W)
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def PC_WID = XLEN
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def PC_INIT = "h60000000".U(PC_WID.W)
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val EXT_INT_WID = 6
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val HILO_WID = 64
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def EXT_INT_WID = 6
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def HILO_WID = 64
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val WRITE_ENABLE = true.B
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val WRITE_DISABLE = false.B
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val READ_ENABLE = true.B
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val READ_DISABLE = false.B
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val INST_VALID = false.B
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val INST_INVALID = true.B
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val SINGLE_ISSUE = false.B
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val DUAL_ISSUE = true.B
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// AluOp
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private val OP_NUM = 77
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val OP_WID = log2Ceil(OP_NUM)
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// NOP
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val EXE_NOP = 0.U(OP_WID.W)
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// 位操作
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val EXE_AND = 1.U(OP_WID.W)
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val EXE_OR = 2.U(OP_WID.W)
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val EXE_XOR = 3.U(OP_WID.W)
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val EXE_NOR = 4.U(OP_WID.W)
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// 移位
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val EXE_SLL = 5.U(OP_WID.W)
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val EXE_SLLV = 6.U(OP_WID.W)
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val EXE_SRL = 7.U(OP_WID.W)
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val EXE_SRLV = 8.U(OP_WID.W)
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val EXE_SRA = 9.U(OP_WID.W)
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val EXE_SRAV = 10.U(OP_WID.W)
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// Move
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val EXE_MOVZ = 11.U(OP_WID.W)
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val EXE_MOVN = 12.U(OP_WID.W)
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// HILO
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val EXE_MFHI = 13.U(OP_WID.W)
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val EXE_MTHI = 14.U(OP_WID.W)
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val EXE_MFLO = 15.U(OP_WID.W)
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val EXE_MTLO = 16.U(OP_WID.W)
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// CSR Move
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val EXE_MFC0 = 17.U(OP_WID.W)
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val EXE_MTC0 = 18.U(OP_WID.W)
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// 比较
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val EXE_SLT = 19.U(OP_WID.W)
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val EXE_SLTU = 20.U(OP_WID.W)
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// 算数
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val EXE_ADD = 21.U(OP_WID.W)
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val EXE_ADDU = 22.U(OP_WID.W)
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val EXE_SUB = 23.U(OP_WID.W)
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val EXE_SUBU = 24.U(OP_WID.W)
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val EXE_CLZ = 25.U(OP_WID.W)
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val EXE_CLO = 26.U(OP_WID.W)
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val EXE_MULT = 27.U(OP_WID.W)
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val EXE_MULTU = 28.U(OP_WID.W)
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val EXE_MUL = 29.U(OP_WID.W)
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val EXE_MADD = 30.U(OP_WID.W)
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val EXE_MADDU = 31.U(OP_WID.W)
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val EXE_MSUB = 32.U(OP_WID.W)
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val EXE_MSUBU = 33.U(OP_WID.W)
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val EXE_DIV = 34.U(OP_WID.W)
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val EXE_DIVU = 35.U(OP_WID.W)
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// 跳转
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val EXE_J = 36.U(OP_WID.W)
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val EXE_JAL = 37.U(OP_WID.W)
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val EXE_JALR = 38.U(OP_WID.W)
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val EXE_JR = 39.U(OP_WID.W)
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val EXE_BEQ = 40.U(OP_WID.W)
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val EXE_BGEZ = 41.U(OP_WID.W)
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val EXE_BGEZAL = 42.U(OP_WID.W)
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val EXE_BGTZ = 43.U(OP_WID.W)
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val EXE_BLEZ = 44.U(OP_WID.W)
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val EXE_BLTZ = 45.U(OP_WID.W)
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val EXE_BLTZAL = 46.U(OP_WID.W)
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val EXE_BNE = 47.U(OP_WID.W)
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// 访存
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val EXE_LB = 48.U(OP_WID.W)
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val EXE_LBU = 49.U(OP_WID.W)
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val EXE_LH = 50.U(OP_WID.W)
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val EXE_LHU = 51.U(OP_WID.W)
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val EXE_LL = 52.U(OP_WID.W)
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val EXE_LW = 53.U(OP_WID.W)
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val EXE_LWL = 54.U(OP_WID.W)
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val EXE_LWR = 55.U(OP_WID.W)
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val EXE_SB = 56.U(OP_WID.W)
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val EXE_SC = 57.U(OP_WID.W)
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val EXE_SH = 58.U(OP_WID.W)
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val EXE_SW = 59.U(OP_WID.W)
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val EXE_SWL = 60.U(OP_WID.W)
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val EXE_SWR = 61.U(OP_WID.W)
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// Trap
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val EXE_TEQ = 62.U(OP_WID.W)
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val EXE_TGE = 63.U(OP_WID.W)
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val EXE_TGEU = 64.U(OP_WID.W)
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val EXE_TLT = 65.U(OP_WID.W)
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val EXE_TLTU = 66.U(OP_WID.W)
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val EXE_TNE = 67.U(OP_WID.W)
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// 例外
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val EXE_SYSCALL = 68.U(OP_WID.W)
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val EXE_BREAK = 69.U(OP_WID.W)
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val EXE_ERET = 70.U(OP_WID.W)
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val EXE_WAIT = 71.U(OP_WID.W)
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// tlb
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val EXE_TLBP = 72.U(OP_WID.W)
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val EXE_TLBR = 73.U(OP_WID.W)
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val EXE_TLBWI = 74.U(OP_WID.W)
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val EXE_TLBWR = 75.U(OP_WID.W)
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// cache
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val EXE_CACHE = 76.U(OP_WID.W)
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// FUSel
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val FU_SEL_NUM = 8
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val FU_SEL_WID = log2Ceil(FU_SEL_NUM)
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val FU_ALU = 0.U(FU_SEL_WID.W)
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val FU_MEM = 1.U(FU_SEL_WID.W)
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val FU_BR = 2.U(FU_SEL_WID.W)
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val FU_EX = 3.U(FU_SEL_WID.W)
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val FU_MTHILO = 4.U(FU_SEL_WID.W)
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val FU_MFHILO = 5.U(FU_SEL_WID.W)
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val FU_MUL = 6.U(FU_SEL_WID.W)
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val FU_DIV = 7.U(FU_SEL_WID.W)
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def WRITE_ENABLE = true.B
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def WRITE_DISABLE = false.B
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def READ_ENABLE = true.B
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def READ_DISABLE = false.B
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def INST_defID = false.B
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def INST_INdefID = true.B
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def SINGLE_ISSUE = false.B
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def DUAL_ISSUE = true.B
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// div
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val DIV_CTRL_WID = 2
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val DIV_FREE = 0.U(DIV_CTRL_WID.W)
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val DIV_BY_ZERO = 1.U(DIV_CTRL_WID.W)
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val DIV_ON = 2.U(DIV_CTRL_WID.W)
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val DIV_END = 3.U(DIV_CTRL_WID.W)
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val DIV_RESULT_READY = true.B
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val DIV_RESULT_NOT_READY = false.B
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val DIV_START = true.B
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val DIV_STOP = false.B
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def DIV_CTRL_WID = 2
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def DIV_FREE = 0.U(DIV_CTRL_WID.W)
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def DIV_BY_ZERO = 1.U(DIV_CTRL_WID.W)
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def DIV_ON = 2.U(DIV_CTRL_WID.W)
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def DIV_END = 3.U(DIV_CTRL_WID.W)
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def DIV_RESULT_READY = true.B
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def DIV_RESULT_NOT_READY = false.B
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def DIV_START = true.B
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def DIV_STOP = false.B
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// inst rom
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val INST_WID = 32
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val INST_ADDR_WID = PC_WID
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def INST_WID = 32
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def INST_ADDR_WID = PC_WID
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// data ram
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val DATA_ADDR_WID = PC_WID
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def DATA_ADDR_WID = PC_WID
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// GPR RegFile
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val AREG_NUM = 32
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val REG_ADDR_WID = 5
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val DATA_WID = XLEN
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def AREG_NUM = 32
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def REG_ADDR_WID = 5
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def DATA_WID = XLEN
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// CSR寄存器
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// CSR Register (5.w), Select (3.w)
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val CSR_INDEX_ADDR = "b00000_000".U(8.W) // 0,0
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val CSR_RANDOM_ADDR = "b00001_000".U(8.W) // 1,0
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val CSR_ENTRYLO0_ADDR = "b00010_000".U(8.W) // 2,0
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val CSR_ENTRYLO1_ADDR = "b00011_000".U(8.W) // 3,0
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val CSR_CONTEXT_ADDR = "b00100_000".U(8.W) // 4,0
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// val CSR_CONTEXT_CONFIG_ADDR = "b00100_001".U(8.W) // 4,1
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// val CSR_USER_LOCAL_ADDR = "b00100_010".U(8.W) // 4,2
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val CSR_PAGE_MASK_ADDR = "b00101_000".U(8.W) // 5,0
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// val CSR_PAGE_GRAIN_ADDR = "b00101_001".U(8.W) // 5,1
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val CSR_WIRED_ADDR = "b00110_000".U(8.W) // 6,0
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// val CSR_HWRENA_ADDR = "b00111_000".U(8.W) // 7,0
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val CSR_BADV_ADDR = "b01000_000".U(8.W) // 8,0
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val CSR_COUNT_ADDR = "b01001_000".U(8.W) // 9,0 (sel保留 6or7)
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val CSR_ENTRYHI_ADDR = "b01010_000".U(8.W) // 10,0
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val CSR_COMPARE_ADDR = "b01011_000".U(8.W) // 11,0 (sel保留 6or7)
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val CSR_STATUS_ADDR = "b01100_000".U(8.W) // 12,0
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// val CSR_INTCTL_ADDR = "b01100_001".U(8.W) // 12,1
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// val CSR_SRSCTL_ADDR = "b01100_010".U(8.W) // 12,2
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// val CSR_SRSMAP_ADDR = "b01100_011".U(8.W) // 12,3
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val CSR_CAUSE_ADDR = "b01101_000".U(8.W) // 13,0
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val CSR_EPC_ADDR = "b01110_000".U(8.W) // 14,0
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val CSR_PRID_ADDR = "b01111_000".U(8.W) // 15,0
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val CSR_EBASE_ADDR = "b01111_001".U(8.W) // 15,1
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// val CSR_CDMMBASE_ADDR = "b01111_010".U(8.W) // 15,2
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// val CSR_CMGCRBASE_ADDR = "b01111_011".U(8.W) // 15,3
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val CSR_CONFIG_ADDR = "b10000_000".U(8.W) // 16,0
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val CSR_CONFIG1_ADDR = "b10000_001".U(8.W) // 16,1
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// val CSR_CONFIG2_ADDR = "b10000_010".U(8.W) // 16,2
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// val CSR_CONFIG3_ADDR = "b10000_011".U(8.W) // 16,3
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// val CSR_CONFIG4_ADDR = "b10000_100".U(8.W) // 16,4 (sel保留 6or7)
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// val CSR_LOAD_LINKED_ADDR = "b10001_000".U(8.W) // 17,0
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val CSR_TAGLO_ADDR = "b11100_000".U(8.W) // 28,0
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val CSR_TAGHI_ADDR = "b11101_000".U(8.W) // 29,0
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val CSR_ERROR_EPC_ADDR = "b11110_000".U(8.W) // 30,0
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def CSR_INDEX_ADDR = "b00000_000".U(8.W) // 0,0
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def CSR_RANDOM_ADDR = "b00001_000".U(8.W) // 1,0
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def CSR_ENTRYLO0_ADDR = "b00010_000".U(8.W) // 2,0
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def CSR_ENTRYLO1_ADDR = "b00011_000".U(8.W) // 3,0
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def CSR_CONTEXT_ADDR = "b00100_000".U(8.W) // 4,0
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// def CSR_CONTEXT_CONFIG_ADDR = "b00100_001".U(8.W) // 4,1
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// def CSR_USER_LOCAL_ADDR = "b00100_010".U(8.W) // 4,2
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def CSR_PAGE_MASK_ADDR = "b00101_000".U(8.W) // 5,0
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// def CSR_PAGE_GRAIN_ADDR = "b00101_001".U(8.W) // 5,1
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def CSR_WIRED_ADDR = "b00110_000".U(8.W) // 6,0
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// def CSR_HWRENA_ADDR = "b00111_000".U(8.W) // 7,0
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def CSR_BADV_ADDR = "b01000_000".U(8.W) // 8,0
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def CSR_COUNT_ADDR = "b01001_000".U(8.W) // 9,0 (sel保留 6or7)
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def CSR_ENTRYHI_ADDR = "b01010_000".U(8.W) // 10,0
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def CSR_COMPARE_ADDR = "b01011_000".U(8.W) // 11,0 (sel保留 6or7)
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def CSR_STATUS_ADDR = "b01100_000".U(8.W) // 12,0
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// def CSR_INTCTL_ADDR = "b01100_001".U(8.W) // 12,1
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// def CSR_SRSCTL_ADDR = "b01100_010".U(8.W) // 12,2
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// def CSR_SRSMAP_ADDR = "b01100_011".U(8.W) // 12,3
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def CSR_CAUSE_ADDR = "b01101_000".U(8.W) // 13,0
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def CSR_EPC_ADDR = "b01110_000".U(8.W) // 14,0
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def CSR_PRID_ADDR = "b01111_000".U(8.W) // 15,0
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def CSR_EBASE_ADDR = "b01111_001".U(8.W) // 15,1
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// def CSR_CDMMBASE_ADDR = "b01111_010".U(8.W) // 15,2
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// def CSR_CMGCRBASE_ADDR = "b01111_011".U(8.W) // 15,3
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def CSR_CONFIG_ADDR = "b10000_000".U(8.W) // 16,0
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def CSR_CONFIG1_ADDR = "b10000_001".U(8.W) // 16,1
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// def CSR_CONFIG2_ADDR = "b10000_010".U(8.W) // 16,2
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// def CSR_CONFIG3_ADDR = "b10000_011".U(8.W) // 16,3
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// def CSR_CONFIG4_ADDR = "b10000_100".U(8.W) // 16,4 (sel保留 6or7)
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// def CSR_LOAD_LINKED_ADDR = "b10001_000".U(8.W) // 17,0
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def CSR_TAGLO_ADDR = "b11100_000".U(8.W) // 28,0
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def CSR_TAGHI_ADDR = "b11101_000".U(8.W) // 29,0
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def CSR_ERROR_EPC_ADDR = "b11110_000".U(8.W) // 30,0
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val CSR_ADDR_WID = 8
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def CSR_ADDR_WID = 8
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val PTEBASE_WID = 9
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def PTEBASE_WID = 9
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}
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// 例外类型
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val EXCODE_WID = 5
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object FuType {
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def num = 5
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def alu = "b000".U
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def lsu = "b001".U
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def mdu = "b010".U
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def csr = "b011".U
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def mou = "b100".U
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def bru = alu
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def apply() = UInt(log2Up(num).W)
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}
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val EX_NO = 0.U(EXCODE_WID.W) // 无异常
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val EX_INT = 1.U(EXCODE_WID.W) // 中断异常
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val EX_MOD = 2.U(EXCODE_WID.W) // TLB 条目修改异常
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val EX_TLBL = 3.U(EXCODE_WID.W) // TLB 非法取指令或访问异常
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val EX_TLBS = 4.U(EXCODE_WID.W) // TLB 非法存储访问异常
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val EX_ADEL = 5.U(EXCODE_WID.W) // 地址未对齐异常（取指令或访问异常）
|
||||
val EX_ADES = 6.U(EXCODE_WID.W) // 地址未对齐异常（存储访问异常）
|
||||
val EX_SYS = 7.U(EXCODE_WID.W) // 系统调用异常
|
||||
val EX_BP = 8.U(EXCODE_WID.W) // 断点异常
|
||||
val EX_RI = 9.U(EXCODE_WID.W) // 保留指令异常
|
||||
val EX_CPU = 10.U(EXCODE_WID.W) // 协处理器不可用异常
|
||||
val EX_OV = 11.U(EXCODE_WID.W) // 算术溢出异常
|
||||
object BTBtype {
|
||||
def B = "b00".U // branch
|
||||
def J = "b01".U // jump
|
||||
def I = "b10".U // indirect
|
||||
def R = "b11".U // return
|
||||
|
||||
val EXC_INT = "h00".U(EXCODE_WID.W) // 中断异常
|
||||
val EXC_MOD = "h01".U(EXCODE_WID.W) // TLB 条目修改异常
|
||||
val EXC_TLBL = "h02".U(EXCODE_WID.W) // TLB 非法取指令或访问异常
|
||||
val EXC_TLBS = "h03".U(EXCODE_WID.W) // TLB 非法存储访问异常
|
||||
val EXC_ADEL = "h04".U(EXCODE_WID.W) // 地址未对齐异常（取指令或访问异常）
|
||||
val EXC_ADES = "h05".U(EXCODE_WID.W) // 地址未对齐异常（存储访问异常）
|
||||
val EXC_SYS = "h08".U(EXCODE_WID.W) // 系统调用异常
|
||||
val EXC_BP = "h09".U(EXCODE_WID.W) // 断点异常
|
||||
val EXC_RI = "h0a".U(EXCODE_WID.W) // 保留指令异常
|
||||
val EXC_CPU = "h0b".U(EXCODE_WID.W) // 协处理器不可用异常
|
||||
val EXC_OV = "h0c".U(EXCODE_WID.W) // 算术溢出异常
|
||||
val EXC_NO = "h1f".U(EXCODE_WID.W) // 无异常
|
||||
def apply() = UInt(2.W)
|
||||
}
|
||||
|
||||
val EX_ENTRY = "h_bfc00380".U(32.W)
|
||||
val EX_TLB_REFILL_ENTRY = "h_bfc00200".U(32.W)
|
||||
object ALUOpType {
|
||||
def add = "b1000000".U
|
||||
def sll = "b0000001".U
|
||||
def slt = "b0000010".U
|
||||
def sltu = "b0000011".U
|
||||
def xor = "b0000100".U
|
||||
def srl = "b0000101".U
|
||||
def or = "b0000110".U
|
||||
def and = "b0000111".U
|
||||
def sub = "b0001000".U
|
||||
def sra = "b0001101".U
|
||||
|
||||
// TLB MMU
|
||||
val TLB_NUM = if (config.build) 8 else 32 // for sys 32, other 8
|
||||
val PFN_WID = 20
|
||||
val C_WID = 3
|
||||
val ASID_WID = 8
|
||||
val VPN2_WID = 19
|
||||
def addw = "b1100000".U
|
||||
def subw = "b0101000".U
|
||||
def sllw = "b0100001".U
|
||||
def srlw = "b0100101".U
|
||||
def sraw = "b0101101".U
|
||||
|
||||
def isWordOp(func: UInt) = func(5)
|
||||
|
||||
def jal = "b1011000".U
|
||||
def jalr = "b1011010".U
|
||||
def beq = "b0010000".U
|
||||
def bne = "b0010001".U
|
||||
def blt = "b0010100".U
|
||||
def bge = "b0010101".U
|
||||
def bltu = "b0010110".U
|
||||
def bgeu = "b0010111".U
|
||||
|
||||
// for RAS
|
||||
def call = "b1011100".U
|
||||
def ret = "b1011110".U
|
||||
|
||||
def isAdd(func: UInt) = func(6)
|
||||
def pcPlus2(func: UInt) = func(5)
|
||||
def isBru(func: UInt) = func(4)
|
||||
def isBranch(func: UInt) = !func(3)
|
||||
def isJump(func: UInt) = isBru(func) && !isBranch(func)
|
||||
def getBranchType(func: UInt) = func(2, 1)
|
||||
def isBranchInvert(func: UInt) = func(0)
|
||||
}
|
||||
|
||||
object LSUOpType { //TODO: refactor LSU fuop
|
||||
def lb = "b0000000".U
|
||||
def lh = "b0000001".U
|
||||
def lw = "b0000010".U
|
||||
def ld = "b0000011".U
|
||||
def lbu = "b0000100".U
|
||||
def lhu = "b0000101".U
|
||||
def lwu = "b0000110".U
|
||||
def sb = "b0001000".U
|
||||
def sh = "b0001001".U
|
||||
def sw = "b0001010".U
|
||||
def sd = "b0001011".U
|
||||
|
||||
def lr = "b0100000".U
|
||||
def sc = "b0100001".U
|
||||
def amoswap = "b0100010".U
|
||||
def amoadd = "b1100011".U
|
||||
def amoxor = "b0100100".U
|
||||
def amoand = "b0100101".U
|
||||
def amoor = "b0100110".U
|
||||
def amomin = "b0110111".U
|
||||
def amomax = "b0110000".U
|
||||
def amominu = "b0110001".U
|
||||
def amomaxu = "b0110010".U
|
||||
|
||||
def isAdd(func: UInt) = func(6)
|
||||
def isAtom(func: UInt): Bool = func(5)
|
||||
def isStore(func: UInt): Bool = func(3)
|
||||
def isLoad(func: UInt): Bool = !isStore(func) & !isAtom(func)
|
||||
def isLR(func: UInt): Bool = func === lr
|
||||
def isSC(func: UInt): Bool = func === sc
|
||||
def isAMO(func: UInt): Bool = isAtom(func) && !isLR(func) && !isSC(func)
|
||||
|
||||
def needMemRead(func: UInt): Bool = isLoad(func) || isAMO(func) || isLR(func)
|
||||
def needMemWrite(func: UInt): Bool = isStore(func) || isAMO(func) || isSC(func)
|
||||
|
||||
def atomW = "010".U
|
||||
def atomD = "011".U
|
||||
}
|
||||
|
||||
object MDUOpType {
|
||||
def mul = "b0000".U
|
||||
def mulh = "b0001".U
|
||||
def mulhsu = "b0010".U
|
||||
def mulhu = "b0011".U
|
||||
def div = "b0100".U
|
||||
def divu = "b0101".U
|
||||
def rem = "b0110".U
|
||||
def remu = "b0111".U
|
||||
|
||||
def mulw = "b1000".U
|
||||
def divw = "b1100".U
|
||||
def divuw = "b1101".U
|
||||
def remw = "b1110".U
|
||||
def remuw = "b1111".U
|
||||
|
||||
def isDiv(op: UInt) = op(2)
|
||||
def isDivSign(op: UInt) = isDiv(op) && !op(0)
|
||||
def isW(op: UInt) = op(3)
|
||||
}
|
||||
|
||||
trait AXIConst {
|
||||
// AXI
|
||||
val BURST_FIXED = 0
|
||||
val BURST_INCR = 1
|
||||
val BURST_WRAP = 2
|
||||
val BURST_RESERVED = 3
|
||||
def BURST_FIXED = 0
|
||||
def BURST_INCR = 1
|
||||
def BURST_WRAP = 2
|
||||
def BURST_RESERVED = 3
|
||||
|
||||
val RESP_OKEY = 0
|
||||
val RESP_EXOKEY = 1
|
||||
val RESP_SLVERR = 2
|
||||
val RESP_DECERR = 3
|
||||
def RESP_OKEY = 0
|
||||
def RESP_EXOKEY = 1
|
||||
def RESP_SLVERR = 2
|
||||
def RESP_DECERR = 3
|
||||
}
|
||||
trait OptionConst {
|
||||
|
||||
// 写寄存器目标 Write Register Address type
|
||||
val WRA_T1 = 0.U(2.W) // 取inst(15,11)
|
||||
val WRA_T2 = 1.U(2.W) // 取inst(20,16)
|
||||
val WRA_T3 = 2.U(2.W) // 取"b11111", 即31号寄存器
|
||||
val WRA_X = 0.U(2.W) // not care
|
||||
val AREG_31 = "b11111".U(5.W)
|
||||
|
||||
// 立即数类型
|
||||
private val IL = 3
|
||||
val IMM_N = 0.U(IL.W)
|
||||
val IMM_LSE = 1.U(IL.W) // 立即数取inst(15,0)作为低16位，符号扩展，适用于ADDI，ADDIU，SLTI，和SLTIU
|
||||
val IMM_LZE = 2.U(IL.W) // 立即数取inst(15,0)作为低16位，零扩展，适用于位操作指令
|
||||
val IMM_HZE = 3.U(IL.W) // 立即数取inst(15,0)作为高16位，零扩展，适用于LUI （是否有必要？）
|
||||
val IMM_SHT = 4.U(IL.W) // 立即数取inst(10,6)作为低5位，不关心扩展，适用于SLL，SRL，SRA
|
||||
}
|
||||
|
||||
object Const extends Constants with Instructions with OptionConst
|
||||
object Const extends Constants with AXIConst
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,165 @@
|
|||
package cpu.defines
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
trait HasInstrType {
|
||||
def InstrN = "b0000".U
|
||||
def InstrI = "b0100".U
|
||||
def InstrR = "b0101".U
|
||||
def InstrS = "b0010".U
|
||||
def InstrB = "b0001".U
|
||||
def InstrU = "b0110".U
|
||||
def InstrJ = "b0111".U
|
||||
def InstrA = "b1110".U
|
||||
def InstrSA = "b1111".U // Atom Inst: SC
|
||||
|
||||
def isrfWen(instrType: UInt): Bool = instrType(2)
|
||||
}
|
||||
|
||||
object RV32I_ALUInstr extends HasInstrType with CoreParameter {
|
||||
def ADDI = BitPat("b????????????_?????_000_?????_0010011")
|
||||
def SLLI = if (XLEN == 32) BitPat("b0000000?????_?????_001_?????_0010011")
|
||||
else BitPat("b000000??????_?????_001_?????_0010011")
|
||||
def SLTI = BitPat("b????????????_?????_010_?????_0010011")
|
||||
def SLTIU = BitPat("b????????????_?????_011_?????_0010011")
|
||||
def XORI = BitPat("b????????????_?????_100_?????_0010011")
|
||||
def SRLI = if (XLEN == 32) BitPat("b0000000?????_?????_101_?????_0010011")
|
||||
else BitPat("b000000??????_?????_101_?????_0010011")
|
||||
def ORI = BitPat("b????????????_?????_110_?????_0010011")
|
||||
def ANDI = BitPat("b????????????_?????_111_?????_0010011")
|
||||
def SRAI = if (XLEN == 32) BitPat("b0100000?????_?????_101_?????_0010011")
|
||||
else BitPat("b010000??????_?????_101_?????_0010011")
|
||||
|
||||
def ADD = BitPat("b0000000_?????_?????_000_?????_0110011")
|
||||
def SLL = BitPat("b0000000_?????_?????_001_?????_0110011")
|
||||
def SLT = BitPat("b0000000_?????_?????_010_?????_0110011")
|
||||
def SLTU = BitPat("b0000000_?????_?????_011_?????_0110011")
|
||||
def XOR = BitPat("b0000000_?????_?????_100_?????_0110011")
|
||||
def SRL = BitPat("b0000000_?????_?????_101_?????_0110011")
|
||||
def OR = BitPat("b0000000_?????_?????_110_?????_0110011")
|
||||
def AND = BitPat("b0000000_?????_?????_111_?????_0110011")
|
||||
def SUB = BitPat("b0100000_?????_?????_000_?????_0110011")
|
||||
def SRA = BitPat("b0100000_?????_?????_101_?????_0110011")
|
||||
|
||||
def AUIPC = BitPat("b????????????????????_?????_0010111")
|
||||
def LUI = BitPat("b????????????????????_?????_0110111")
|
||||
|
||||
val table = Array(
|
||||
ADDI -> List(InstrI, FuType.alu, ALUOpType.add),
|
||||
SLLI -> List(InstrI, FuType.alu, ALUOpType.sll),
|
||||
SLTI -> List(InstrI, FuType.alu, ALUOpType.slt),
|
||||
SLTIU -> List(InstrI, FuType.alu, ALUOpType.sltu),
|
||||
XORI -> List(InstrI, FuType.alu, ALUOpType.xor),
|
||||
SRLI -> List(InstrI, FuType.alu, ALUOpType.srl),
|
||||
ORI -> List(InstrI, FuType.alu, ALUOpType.or),
|
||||
ANDI -> List(InstrI, FuType.alu, ALUOpType.and),
|
||||
SRAI -> List(InstrI, FuType.alu, ALUOpType.sra),
|
||||
ADD -> List(InstrR, FuType.alu, ALUOpType.add),
|
||||
SLL -> List(InstrR, FuType.alu, ALUOpType.sll),
|
||||
SLT -> List(InstrR, FuType.alu, ALUOpType.slt),
|
||||
SLTU -> List(InstrR, FuType.alu, ALUOpType.sltu),
|
||||
XOR -> List(InstrR, FuType.alu, ALUOpType.xor),
|
||||
SRL -> List(InstrR, FuType.alu, ALUOpType.srl),
|
||||
OR -> List(InstrR, FuType.alu, ALUOpType.or),
|
||||
AND -> List(InstrR, FuType.alu, ALUOpType.and),
|
||||
SUB -> List(InstrR, FuType.alu, ALUOpType.sub),
|
||||
SRA -> List(InstrR, FuType.alu, ALUOpType.sra),
|
||||
AUIPC -> List(InstrU, FuType.alu, ALUOpType.add),
|
||||
LUI -> List(InstrU, FuType.alu, ALUOpType.add)
|
||||
)
|
||||
}
|
||||
|
||||
object RV32I_BRUInstr extends HasInstrType {
|
||||
def JAL = BitPat("b????????????????????_?????_1101111")
|
||||
def JALR = BitPat("b????????????_?????_000_?????_1100111")
|
||||
|
||||
def BNE = BitPat("b???????_?????_?????_001_?????_1100011")
|
||||
def BEQ = BitPat("b???????_?????_?????_000_?????_1100011")
|
||||
def BLT = BitPat("b???????_?????_?????_100_?????_1100011")
|
||||
def BGE = BitPat("b???????_?????_?????_101_?????_1100011")
|
||||
def BLTU = BitPat("b???????_?????_?????_110_?????_1100011")
|
||||
def BGEU = BitPat("b???????_?????_?????_111_?????_1100011")
|
||||
|
||||
val table = Array(
|
||||
JAL -> List(InstrJ, FuType.bru, ALUOpType.jal),
|
||||
JALR -> List(InstrI, FuType.bru, ALUOpType.jalr),
|
||||
BEQ -> List(InstrB, FuType.bru, ALUOpType.beq),
|
||||
BNE -> List(InstrB, FuType.bru, ALUOpType.bne),
|
||||
BLT -> List(InstrB, FuType.bru, ALUOpType.blt),
|
||||
BGE -> List(InstrB, FuType.bru, ALUOpType.bge),
|
||||
BLTU -> List(InstrB, FuType.bru, ALUOpType.bltu),
|
||||
BGEU -> List(InstrB, FuType.bru, ALUOpType.bgeu)
|
||||
)
|
||||
|
||||
val bruFuncTobtbTypeTable = List(
|
||||
ALUOpType.beq -> BTBtype.B,
|
||||
ALUOpType.bne -> BTBtype.B,
|
||||
ALUOpType.blt -> BTBtype.B,
|
||||
ALUOpType.bge -> BTBtype.B,
|
||||
ALUOpType.bltu -> BTBtype.B,
|
||||
ALUOpType.bgeu -> BTBtype.B,
|
||||
ALUOpType.call -> BTBtype.J,
|
||||
ALUOpType.ret -> BTBtype.R,
|
||||
ALUOpType.jal -> BTBtype.J,
|
||||
ALUOpType.jalr -> BTBtype.I
|
||||
)
|
||||
}
|
||||
|
||||
object RV32I_LSUInstr extends HasInstrType {
|
||||
def LB = BitPat("b????????????_?????_000_?????_0000011")
|
||||
def LH = BitPat("b????????????_?????_001_?????_0000011")
|
||||
def LW = BitPat("b????????????_?????_010_?????_0000011")
|
||||
def LBU = BitPat("b????????????_?????_100_?????_0000011")
|
||||
def LHU = BitPat("b????????????_?????_101_?????_0000011")
|
||||
def SB = BitPat("b???????_?????_?????_000_?????_0100011")
|
||||
def SH = BitPat("b???????_?????_?????_001_?????_0100011")
|
||||
def SW = BitPat("b???????_?????_?????_010_?????_0100011")
|
||||
|
||||
val table = Array(
|
||||
LB -> List(InstrI, FuType.lsu, LSUOpType.lb),
|
||||
LH -> List(InstrI, FuType.lsu, LSUOpType.lh),
|
||||
LW -> List(InstrI, FuType.lsu, LSUOpType.lw),
|
||||
LBU -> List(InstrI, FuType.lsu, LSUOpType.lbu),
|
||||
LHU -> List(InstrI, FuType.lsu, LSUOpType.lhu),
|
||||
SB -> List(InstrS, FuType.lsu, LSUOpType.sb),
|
||||
SH -> List(InstrS, FuType.lsu, LSUOpType.sh),
|
||||
SW -> List(InstrS, FuType.lsu, LSUOpType.sw)
|
||||
)
|
||||
}
|
||||
|
||||
object RV64IInstr extends HasInstrType {
|
||||
def ADDIW = BitPat("b???????_?????_?????_000_?????_0011011")
|
||||
def SLLIW = BitPat("b0000000_?????_?????_001_?????_0011011")
|
||||
def SRLIW = BitPat("b0000000_?????_?????_101_?????_0011011")
|
||||
def SRAIW = BitPat("b0100000_?????_?????_101_?????_0011011")
|
||||
def SLLW = BitPat("b0000000_?????_?????_001_?????_0111011")
|
||||
def SRLW = BitPat("b0000000_?????_?????_101_?????_0111011")
|
||||
def SRAW = BitPat("b0100000_?????_?????_101_?????_0111011")
|
||||
def ADDW = BitPat("b0000000_?????_?????_000_?????_0111011")
|
||||
def SUBW = BitPat("b0100000_?????_?????_000_?????_0111011")
|
||||
|
||||
def LWU = BitPat("b???????_?????_?????_110_?????_0000011")
|
||||
def LD = BitPat("b???????_?????_?????_011_?????_0000011")
|
||||
def SD = BitPat("b???????_?????_?????_011_?????_0100011")
|
||||
|
||||
val table = Array(
|
||||
ADDIW -> List(InstrI, FuType.alu, ALUOpType.addw),
|
||||
SLLIW -> List(InstrI, FuType.alu, ALUOpType.sllw),
|
||||
SRLIW -> List(InstrI, FuType.alu, ALUOpType.srlw),
|
||||
SRAIW -> List(InstrI, FuType.alu, ALUOpType.sraw),
|
||||
SLLW -> List(InstrR, FuType.alu, ALUOpType.sllw),
|
||||
SRLW -> List(InstrR, FuType.alu, ALUOpType.srlw),
|
||||
SRAW -> List(InstrR, FuType.alu, ALUOpType.sraw),
|
||||
ADDW -> List(InstrR, FuType.alu, ALUOpType.addw),
|
||||
SUBW -> List(InstrR, FuType.alu, ALUOpType.subw),
|
||||
LWU -> List(InstrI, FuType.lsu, LSUOpType.lwu),
|
||||
LD -> List(InstrI, FuType.lsu, LSUOpType.ld),
|
||||
SD -> List(InstrS, FuType.lsu, LSUOpType.sd)
|
||||
)
|
||||
}
|
||||
|
||||
object RVIInstr extends CoreParameter {
|
||||
val table = RV32I_ALUInstr.table ++ RV32I_BRUInstr.table ++ RV32I_LSUInstr.table ++
|
||||
(if (XLEN == 64) RV64IInstr.table else Array.empty)
|
||||
}
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
package cpu.defines
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
object RV32MInstr extends HasInstrType with CoreParameter {
|
||||
def MUL = BitPat("b0000001_?????_?????_000_?????_0110011")
|
||||
def MULH = BitPat("b0000001_?????_?????_001_?????_0110011")
|
||||
def MULHSU = BitPat("b0000001_?????_?????_010_?????_0110011")
|
||||
def MULHU = BitPat("b0000001_?????_?????_011_?????_0110011")
|
||||
def DIV = BitPat("b0000001_?????_?????_100_?????_0110011")
|
||||
def DIVU = BitPat("b0000001_?????_?????_101_?????_0110011")
|
||||
def REM = BitPat("b0000001_?????_?????_110_?????_0110011")
|
||||
def REMU = BitPat("b0000001_?????_?????_111_?????_0110011")
|
||||
def MULW = BitPat("b0000001_?????_?????_000_?????_0111011")
|
||||
def DIVW = BitPat("b0000001_?????_?????_100_?????_0111011")
|
||||
def DIVUW = BitPat("b0000001_?????_?????_101_?????_0111011")
|
||||
def REMW = BitPat("b0000001_?????_?????_110_?????_0111011")
|
||||
def REMUW = BitPat("b0000001_?????_?????_111_?????_0111011")
|
||||
|
||||
val mulTable = Array(
|
||||
MUL -> List(InstrR, FuType.mdu, MDUOpType.mul),
|
||||
MULH -> List(InstrR, FuType.mdu, MDUOpType.mulh),
|
||||
MULHSU -> List(InstrR, FuType.mdu, MDUOpType.mulhsu),
|
||||
MULHU -> List(InstrR, FuType.mdu, MDUOpType.mulhu)
|
||||
)
|
||||
val divTable = Array(
|
||||
DIV -> List(InstrR, FuType.mdu, MDUOpType.div),
|
||||
DIVU -> List(InstrR, FuType.mdu, MDUOpType.divu),
|
||||
REM -> List(InstrR, FuType.mdu, MDUOpType.rem),
|
||||
REMU -> List(InstrR, FuType.mdu, MDUOpType.remu)
|
||||
)
|
||||
val table = mulTable ++ (if (config.hasMDU) divTable else Array.empty)
|
||||
}
|
||||
|
||||
object RV64MInstr extends HasInstrType with CoreParameter {
|
||||
def MULW = BitPat("b0000001_?????_?????_000_?????_0111011")
|
||||
def DIVW = BitPat("b0000001_?????_?????_100_?????_0111011")
|
||||
def DIVUW = BitPat("b0000001_?????_?????_101_?????_0111011")
|
||||
def REMW = BitPat("b0000001_?????_?????_110_?????_0111011")
|
||||
def REMUW = BitPat("b0000001_?????_?????_111_?????_0111011")
|
||||
|
||||
val mulTable = Array(
|
||||
MULW -> List(InstrR, FuType.mdu, MDUOpType.mulw)
|
||||
)
|
||||
val divTable = Array(
|
||||
DIVW -> List(InstrR, FuType.mdu, MDUOpType.divw),
|
||||
DIVUW -> List(InstrR, FuType.mdu, MDUOpType.divuw),
|
||||
REMW -> List(InstrR, FuType.mdu, MDUOpType.remw),
|
||||
REMUW -> List(InstrR, FuType.mdu, MDUOpType.remuw)
|
||||
)
|
||||
val table = mulTable ++ (if (config.hasMDU) divTable else Array.empty)
|
||||
}
|
||||
|
||||
object RVMInstr extends CoreParameter {
|
||||
val table = RV32MInstr.table ++ (if (XLEN == 64) RV64MInstr.table else Array.empty)
|
||||
}
|
||||
|
|
@ -16,137 +16,190 @@ class Decoder extends Module {
|
|||
})
|
||||
val inst = io.in.inst
|
||||
|
||||
val signals: List[UInt] = ListLookup(
|
||||
//@formatter:off
|
||||
inst,
|
||||
List(INST_INVALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
Array( /* inst_valid | reg1_ren | reg2_ren | fusel | op | reg_wen | reg_waddr | imm_type | dual_issue */
|
||||
// NOP
|
||||
NOP -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// 位操作
|
||||
OR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
AND -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
XOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
NOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_NOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// 移位
|
||||
SLLV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
SRLV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
SRAV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
SLL -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE),
|
||||
SRL -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE),
|
||||
SRA -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE),
|
||||
// 立即数
|
||||
ORI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE),
|
||||
ANDI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE),
|
||||
XORI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE),
|
||||
LUI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T2, IMM_HZE, DUAL_ISSUE),
|
||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||
BNE-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SNE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||
BEQ-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SEQ, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||
BLT-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||
BLTU-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||
BGE-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||
BGEU-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGEU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||
|
||||
// Move
|
||||
MOVN -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVN, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
MOVZ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVZ, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
JAL-> List(Y,N,N,N,Y,N,N,N,N,N,N,A2_SIZE,A1_PC, IMM_UJ,DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
JALR-> List(Y,N,N,N,N,Y,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
AUIPC-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
|
||||
// HI，LO的Move指令
|
||||
MFHI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFHI, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
MFLO -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFLO, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
MTHI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MTHILO, EXE_MTHI, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
MTLO -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MTHILO, EXE_MTLO, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
LB-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
LH-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
LW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
LBU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
LHU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
SB-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||
SH-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||
SW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||
|
||||
// C0的Move指令
|
||||
MFC0 -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_MFC0, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
MTC0 -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_MTC0, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
LUI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
ADDI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
SLTI -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
SLTIU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
ANDI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
ORI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
XORI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
ADD-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
SUB-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
SLT-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
SLTU-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
AND-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
OR-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
XOR-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
SLL-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
SRL-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
SRA-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||
|
||||
// 比较指令
|
||||
SLT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLT, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
SLTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// 立即数
|
||||
SLTI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLT, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
|
||||
SLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
|
||||
FENCE-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,Y,N,N),
|
||||
|
||||
// Trap
|
||||
TEQ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TEQ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
TEQI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TEQ, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
TGE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TGE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
TGEI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGE, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
TGEIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
TGEU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
TLT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TLT, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
TLTI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLT, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
TLTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
TLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
TNE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TNE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
TNEI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TNE, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
ECALL-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
||||
EBREAK-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
||||
MRET-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
||||
WFI-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
||||
CSRRW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
|
||||
CSRRS-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
|
||||
CSRRC-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N),
|
||||
CSRRWI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
|
||||
CSRRSI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
|
||||
CSRRCI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N))
|
||||
|
||||
// 算术指令
|
||||
ADD -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_ADD, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
ADDU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_ADDU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
SUB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SUB, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
SUBU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SUBU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
MUL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MUL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
MULT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MULT, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
MULTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MULTU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
MADD -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MADD, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
MADDU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MADDU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
MSUB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MSUB, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
MSUBU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MSUBU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
DIV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_DIV, EXE_DIV, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
DIVU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_DIV, EXE_DIVU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
CLO -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLO, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
CLZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLZ, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// 立即数
|
||||
ADDI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADD, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
|
||||
ADDIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADDU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
|
||||
// 跳转指令
|
||||
J -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_J, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
JAL -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_JAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE),
|
||||
JR -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_JR, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
JALR -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_JALR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
BEQ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_BR, EXE_BEQ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
BNE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_BR, EXE_BNE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
BGTZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGTZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
BLEZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLEZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
BGEZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGEZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
BGEZAL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGEZAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE),
|
||||
BLTZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLTZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
BLTZAL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLTZAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE),
|
||||
|
||||
// TLB
|
||||
TLBP -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBP, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
TLBR -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBR, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
TLBWI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWI, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
TLBWR -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWR, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
// val signals: List[UInt] = ListLookup(
|
||||
// //@formatter:off
|
||||
// inst,
|
||||
// List(INST_INVALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// Array( /* inst_valid | reg1_ren | reg2_ren | fusel | op | reg_wen | reg_waddr | imm_type | dual_issue */
|
||||
// // NOP
|
||||
// NOP -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// // 位操作
|
||||
// OR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// AND -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// XOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// NOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_NOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// // 移位
|
||||
// SLLV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// SRLV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// SRAV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// SLL -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE),
|
||||
// SRL -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE),
|
||||
// SRA -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE),
|
||||
// // 立即数
|
||||
// ORI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE),
|
||||
// ANDI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE),
|
||||
// XORI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE),
|
||||
// LUI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T2, IMM_HZE, DUAL_ISSUE),
|
||||
|
||||
// 例外指令
|
||||
SYSCALL -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_SYSCALL, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
BREAK -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_BREAK, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
ERET -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_ERET, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
WAIT -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
// // Move
|
||||
// MOVN -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVN, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// MOVZ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVZ, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
|
||||
// 访存指令
|
||||
LB -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LB, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
LBU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LBU, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
LH -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LH, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
LHU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LHU, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
LW -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LW, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
SB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SB, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
SH -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SH, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
SW -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SW, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
LWL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_LWL, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
LWR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_LWR, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
SWL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SWL, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
SWR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SWR, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// // HI，LO的Move指令
|
||||
// MFHI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFHI, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// MFLO -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFLO, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// MTHI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MTHILO, EXE_MTHI, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// MTLO -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MTHILO, EXE_MTLO, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
|
||||
// // C0的Move指令
|
||||
// MFC0 -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_MFC0, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
// MTC0 -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_MTC0, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
|
||||
// // 比较指令
|
||||
// SLT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLT, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// SLTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// // 立即数
|
||||
// SLTI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLT, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
|
||||
// SLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
|
||||
|
||||
// // Trap
|
||||
// TEQ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TEQ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// TEQI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TEQ, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
// TGE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TGE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// TGEI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGE, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
// TGEIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
// TGEU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// TLT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TLT, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// TLTI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLT, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
// TLTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// TLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
// TNE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TNE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// TNEI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TNE, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
|
||||
|
||||
// // 算术指令
|
||||
// ADD -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_ADD, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// ADDU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_ADDU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// SUB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SUB, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// SUBU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SUBU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// MUL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MUL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// MULT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MULT, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// MULTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MULTU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// MADD -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MADD, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// MADDU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MADDU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// MSUB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MSUB, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// MSUBU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MSUBU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// DIV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_DIV, EXE_DIV, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// DIVU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_DIV, EXE_DIVU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// CLO -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLO, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// CLZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLZ, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// // 立即数
|
||||
// ADDI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADD, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
|
||||
// ADDIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADDU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
|
||||
// // 跳转指令
|
||||
// J -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_J, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// JAL -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_JAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE),
|
||||
// JR -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_JR, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// JALR -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_JALR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
|
||||
// BEQ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_BR, EXE_BEQ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// BNE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_BR, EXE_BNE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// BGTZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGTZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// BLEZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLEZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// BGEZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGEZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// BGEZAL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGEZAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE),
|
||||
// BLTZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLTZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// BLTZAL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLTZAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE),
|
||||
|
||||
// // TLB
|
||||
// TLBP -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBP, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
// TLBR -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBR, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
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// TLBWI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWI, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
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// TLBWR -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWR, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
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// // 例外指令
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// SYSCALL -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_SYSCALL, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
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// BREAK -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_BREAK, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
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// ERET -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_ERET, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
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// WAIT -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
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// // 访存指令
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// LB -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LB, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
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// LBU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LBU, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
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// LH -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LH, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
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// LHU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LHU, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
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// LW -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LW, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
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// SB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SB, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
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||||
// SH -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SH, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
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// SW -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SW, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// LWL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_LWL, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
// LWR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_LWR, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
// SWL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SWL, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// SWR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SWR, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
|
||||
LL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LL, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
SC -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SC, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
// LL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LL, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
// SC -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SC, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE),
|
||||
|
||||
SYNC -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
PREF -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_ENABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
PREFX -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// SYNC -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// PREF -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_ENABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
// PREFX -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
|
||||
|
||||
// Cache
|
||||
CACHE -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CACHE, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
),
|
||||
// @formatter:on
|
||||
)
|
||||
// // Cache
|
||||
// CACHE -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CACHE, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
|
||||
// ),
|
||||
// // @formatter:on
|
||||
// )
|
||||
val inst_valid :: reg1_ren :: reg2_ren :: fusel :: op :: reg_wen :: reg_waddr_type :: imm_type :: dual_issue :: Nil =
|
||||
signals
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue