diff --git a/chisel/.scalafmt.conf b/chisel/.scalafmt.conf index 5b136d5..9806cf9 100644 --- a/chisel/.scalafmt.conf +++ b/chisel/.scalafmt.conf @@ -18,6 +18,9 @@ align.tokens.add = [ }, { code = "=" + }, + { + code = "->" } ] diff --git a/chisel/playground/src/CpuConfig.scala b/chisel/playground/src/CpuConfig.scala index d3606ec..e1db8c7 100644 --- a/chisel/playground/src/CpuConfig.scala +++ b/chisel/playground/src/CpuConfig.scala @@ -3,19 +3,20 @@ package cpu import chisel3.util._ case class CpuConfig( - val build: Boolean = false, // 是否为build模式 - val hasCommitBuffer: Boolean = false, // 是否有提交缓存 - val decoderNum: Int = 1, // 同时访问寄存器的指令数 - val commitNum: Int = 1, // 同时提交的指令数 - val fuNum: Int = 1, // 功能单元数 - val instFetchNum: Int = 1, // iCache取到的指令数量 - val instFifoDepth: Int = 8, // 指令缓存深度 - val mulClockNum: Int = 2, // 乘法器的时钟周期数 - val divClockNum: Int = 8, // 除法器的时钟周期数 - val branchPredictor: String = "adaptive",// adaptive, pesudo, global + val build: Boolean = false, // 是否为build模式 + val isRV32: Boolean = false, // 是否为RV32 + val hasMDU: Boolean = false, // 是否有乘除法单元 + val hasCommitBuffer: Boolean = false, // 是否有提交缓存 + val decoderNum: Int = 1, // 同时访问寄存器的指令数 + val commitNum: Int = 1, // 同时提交的指令数 + val fuNum: Int = 1, // 功能单元数 + val instFetchNum: Int = 1, // iCache取到的指令数量 + val instFifoDepth: Int = 8, // 指令缓存深度 + val mulClockNum: Int = 2, // 乘法器的时钟周期数 + val divClockNum: Int = 8, // 除法器的时钟周期数 + val branchPredictor: String = "adaptive" // adaptive, pesudo, global ) case class BranchPredictorConfig( - val bhtDepth: Int = 5, - val phtDepth: Int = 6, -) + val bhtDepth: Int = 5, + val phtDepth: Int = 6) diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala index a7b3cc5..de32f1b 100644 --- a/chisel/playground/src/defines/Const.scala +++ b/chisel/playground/src/defines/Const.scala @@ -2,266 +2,229 @@ package cpu.defines import chisel3._ import chisel3.util._ -import cpu.defines.Instructions import cpu.CpuConfig -trait Constants { - val config = new CpuConfig - val XLEN = 64 +trait CoreParameter { + def config = new CpuConfig + val XLEN = if (config.isRV32) 32 else 64 +} + +trait Constants extends CoreParameter { + def config = new CpuConfig // 全局 - val PC_WID = XLEN - val PC_INIT = "h60000000".U(PC_WID.W) + def PC_WID = XLEN + def PC_INIT = "h60000000".U(PC_WID.W) - val EXT_INT_WID = 6 - val HILO_WID = 64 + def EXT_INT_WID = 6 + def HILO_WID = 64 - val WRITE_ENABLE = true.B - val WRITE_DISABLE = false.B - val READ_ENABLE = true.B - val READ_DISABLE = false.B - val INST_VALID = false.B - val INST_INVALID = true.B - val SINGLE_ISSUE = false.B - val DUAL_ISSUE = true.B - - // AluOp - private val OP_NUM = 77 - val OP_WID = log2Ceil(OP_NUM) - // NOP - val EXE_NOP = 0.U(OP_WID.W) - // 位操作 - val EXE_AND = 1.U(OP_WID.W) - val EXE_OR = 2.U(OP_WID.W) - val EXE_XOR = 3.U(OP_WID.W) - val EXE_NOR = 4.U(OP_WID.W) - // 移位 - val EXE_SLL = 5.U(OP_WID.W) - val EXE_SLLV = 6.U(OP_WID.W) - val EXE_SRL = 7.U(OP_WID.W) - val EXE_SRLV = 8.U(OP_WID.W) - val EXE_SRA = 9.U(OP_WID.W) - val EXE_SRAV = 10.U(OP_WID.W) - // Move - val EXE_MOVZ = 11.U(OP_WID.W) - val EXE_MOVN = 12.U(OP_WID.W) - // HILO - val EXE_MFHI = 13.U(OP_WID.W) - val EXE_MTHI = 14.U(OP_WID.W) - val EXE_MFLO = 15.U(OP_WID.W) - val EXE_MTLO = 16.U(OP_WID.W) - // CSR Move - val EXE_MFC0 = 17.U(OP_WID.W) - val EXE_MTC0 = 18.U(OP_WID.W) - // 比较 - val EXE_SLT = 19.U(OP_WID.W) - val EXE_SLTU = 20.U(OP_WID.W) - // 算数 - val EXE_ADD = 21.U(OP_WID.W) - val EXE_ADDU = 22.U(OP_WID.W) - val EXE_SUB = 23.U(OP_WID.W) - val EXE_SUBU = 24.U(OP_WID.W) - val EXE_CLZ = 25.U(OP_WID.W) - val EXE_CLO = 26.U(OP_WID.W) - val EXE_MULT = 27.U(OP_WID.W) - val EXE_MULTU = 28.U(OP_WID.W) - val EXE_MUL = 29.U(OP_WID.W) - val EXE_MADD = 30.U(OP_WID.W) - val EXE_MADDU = 31.U(OP_WID.W) - val EXE_MSUB = 32.U(OP_WID.W) - val EXE_MSUBU = 33.U(OP_WID.W) - val EXE_DIV = 34.U(OP_WID.W) - val EXE_DIVU = 35.U(OP_WID.W) - // 跳转 - val EXE_J = 36.U(OP_WID.W) - val EXE_JAL = 37.U(OP_WID.W) - val EXE_JALR = 38.U(OP_WID.W) - val EXE_JR = 39.U(OP_WID.W) - val EXE_BEQ = 40.U(OP_WID.W) - val EXE_BGEZ = 41.U(OP_WID.W) - val EXE_BGEZAL = 42.U(OP_WID.W) - val EXE_BGTZ = 43.U(OP_WID.W) - val EXE_BLEZ = 44.U(OP_WID.W) - val EXE_BLTZ = 45.U(OP_WID.W) - val EXE_BLTZAL = 46.U(OP_WID.W) - val EXE_BNE = 47.U(OP_WID.W) - // 访存 - val EXE_LB = 48.U(OP_WID.W) - val EXE_LBU = 49.U(OP_WID.W) - val EXE_LH = 50.U(OP_WID.W) - val EXE_LHU = 51.U(OP_WID.W) - val EXE_LL = 52.U(OP_WID.W) - val EXE_LW = 53.U(OP_WID.W) - val EXE_LWL = 54.U(OP_WID.W) - val EXE_LWR = 55.U(OP_WID.W) - val EXE_SB = 56.U(OP_WID.W) - val EXE_SC = 57.U(OP_WID.W) - val EXE_SH = 58.U(OP_WID.W) - val EXE_SW = 59.U(OP_WID.W) - val EXE_SWL = 60.U(OP_WID.W) - val EXE_SWR = 61.U(OP_WID.W) - // Trap - val EXE_TEQ = 62.U(OP_WID.W) - val EXE_TGE = 63.U(OP_WID.W) - val EXE_TGEU = 64.U(OP_WID.W) - val EXE_TLT = 65.U(OP_WID.W) - val EXE_TLTU = 66.U(OP_WID.W) - val EXE_TNE = 67.U(OP_WID.W) - // 例外 - val EXE_SYSCALL = 68.U(OP_WID.W) - val EXE_BREAK = 69.U(OP_WID.W) - val EXE_ERET = 70.U(OP_WID.W) - val EXE_WAIT = 71.U(OP_WID.W) - // tlb - val EXE_TLBP = 72.U(OP_WID.W) - val EXE_TLBR = 73.U(OP_WID.W) - val EXE_TLBWI = 74.U(OP_WID.W) - val EXE_TLBWR = 75.U(OP_WID.W) - // cache - val EXE_CACHE = 76.U(OP_WID.W) - - // FUSel - val FU_SEL_NUM = 8 - val FU_SEL_WID = log2Ceil(FU_SEL_NUM) - - val FU_ALU = 0.U(FU_SEL_WID.W) - val FU_MEM = 1.U(FU_SEL_WID.W) - val FU_BR = 2.U(FU_SEL_WID.W) - val FU_EX = 3.U(FU_SEL_WID.W) - val FU_MTHILO = 4.U(FU_SEL_WID.W) - val FU_MFHILO = 5.U(FU_SEL_WID.W) - val FU_MUL = 6.U(FU_SEL_WID.W) - val FU_DIV = 7.U(FU_SEL_WID.W) + def WRITE_ENABLE = true.B + def WRITE_DISABLE = false.B + def READ_ENABLE = true.B + def READ_DISABLE = false.B + def INST_defID = false.B + def INST_INdefID = true.B + def SINGLE_ISSUE = false.B + def DUAL_ISSUE = true.B // div - val DIV_CTRL_WID = 2 - val DIV_FREE = 0.U(DIV_CTRL_WID.W) - val DIV_BY_ZERO = 1.U(DIV_CTRL_WID.W) - val DIV_ON = 2.U(DIV_CTRL_WID.W) - val DIV_END = 3.U(DIV_CTRL_WID.W) - val DIV_RESULT_READY = true.B - val DIV_RESULT_NOT_READY = false.B - val DIV_START = true.B - val DIV_STOP = false.B + def DIV_CTRL_WID = 2 + def DIV_FREE = 0.U(DIV_CTRL_WID.W) + def DIV_BY_ZERO = 1.U(DIV_CTRL_WID.W) + def DIV_ON = 2.U(DIV_CTRL_WID.W) + def DIV_END = 3.U(DIV_CTRL_WID.W) + def DIV_RESULT_READY = true.B + def DIV_RESULT_NOT_READY = false.B + def DIV_START = true.B + def DIV_STOP = false.B // inst rom - val INST_WID = 32 - val INST_ADDR_WID = PC_WID + def INST_WID = 32 + def INST_ADDR_WID = PC_WID // data ram - val DATA_ADDR_WID = PC_WID + def DATA_ADDR_WID = PC_WID // GPR RegFile - val AREG_NUM = 32 - val REG_ADDR_WID = 5 - val DATA_WID = XLEN + def AREG_NUM = 32 + def REG_ADDR_WID = 5 + def DATA_WID = XLEN // CSR寄存器 // CSR Register (5.w), Select (3.w) - val CSR_INDEX_ADDR = "b00000_000".U(8.W) // 0,0 - val CSR_RANDOM_ADDR = "b00001_000".U(8.W) // 1,0 - val CSR_ENTRYLO0_ADDR = "b00010_000".U(8.W) // 2,0 - val CSR_ENTRYLO1_ADDR = "b00011_000".U(8.W) // 3,0 - val CSR_CONTEXT_ADDR = "b00100_000".U(8.W) // 4,0 - // val CSR_CONTEXT_CONFIG_ADDR = "b00100_001".U(8.W) // 4,1 - // val CSR_USER_LOCAL_ADDR = "b00100_010".U(8.W) // 4,2 - val CSR_PAGE_MASK_ADDR = "b00101_000".U(8.W) // 5,0 - // val CSR_PAGE_GRAIN_ADDR = "b00101_001".U(8.W) // 5,1 - val CSR_WIRED_ADDR = "b00110_000".U(8.W) // 6,0 - // val CSR_HWRENA_ADDR = "b00111_000".U(8.W) // 7,0 - val CSR_BADV_ADDR = "b01000_000".U(8.W) // 8,0 - val CSR_COUNT_ADDR = "b01001_000".U(8.W) // 9,0 (sel保留 6or7) - val CSR_ENTRYHI_ADDR = "b01010_000".U(8.W) // 10,0 - val CSR_COMPARE_ADDR = "b01011_000".U(8.W) // 11,0 (sel保留 6or7) - val CSR_STATUS_ADDR = "b01100_000".U(8.W) // 12,0 - // val CSR_INTCTL_ADDR = "b01100_001".U(8.W) // 12,1 - // val CSR_SRSCTL_ADDR = "b01100_010".U(8.W) // 12,2 - // val CSR_SRSMAP_ADDR = "b01100_011".U(8.W) // 12,3 - val CSR_CAUSE_ADDR = "b01101_000".U(8.W) // 13,0 - val CSR_EPC_ADDR = "b01110_000".U(8.W) // 14,0 - val CSR_PRID_ADDR = "b01111_000".U(8.W) // 15,0 - val CSR_EBASE_ADDR = "b01111_001".U(8.W) // 15,1 - // val CSR_CDMMBASE_ADDR = "b01111_010".U(8.W) // 15,2 - // val CSR_CMGCRBASE_ADDR = "b01111_011".U(8.W) // 15,3 - val CSR_CONFIG_ADDR = "b10000_000".U(8.W) // 16,0 - val CSR_CONFIG1_ADDR = "b10000_001".U(8.W) // 16,1 - // val CSR_CONFIG2_ADDR = "b10000_010".U(8.W) // 16,2 - // val CSR_CONFIG3_ADDR = "b10000_011".U(8.W) // 16,3 - // val CSR_CONFIG4_ADDR = "b10000_100".U(8.W) // 16,4 (sel保留 6or7) - // val CSR_LOAD_LINKED_ADDR = "b10001_000".U(8.W) // 17,0 - val CSR_TAGLO_ADDR = "b11100_000".U(8.W) // 28,0 - val CSR_TAGHI_ADDR = "b11101_000".U(8.W) // 29,0 - val CSR_ERROR_EPC_ADDR = "b11110_000".U(8.W) // 30,0 + def CSR_INDEX_ADDR = "b00000_000".U(8.W) // 0,0 + def CSR_RANDOM_ADDR = "b00001_000".U(8.W) // 1,0 + def CSR_ENTRYLO0_ADDR = "b00010_000".U(8.W) // 2,0 + def CSR_ENTRYLO1_ADDR = "b00011_000".U(8.W) // 3,0 + def CSR_CONTEXT_ADDR = "b00100_000".U(8.W) // 4,0 + // def CSR_CONTEXT_CONFIG_ADDR = "b00100_001".U(8.W) // 4,1 + // def CSR_USER_LOCAL_ADDR = "b00100_010".U(8.W) // 4,2 + def CSR_PAGE_MASK_ADDR = "b00101_000".U(8.W) // 5,0 + // def CSR_PAGE_GRAIN_ADDR = "b00101_001".U(8.W) // 5,1 + def CSR_WIRED_ADDR = "b00110_000".U(8.W) // 6,0 + // def CSR_HWRENA_ADDR = "b00111_000".U(8.W) // 7,0 + def CSR_BADV_ADDR = "b01000_000".U(8.W) // 8,0 + def CSR_COUNT_ADDR = "b01001_000".U(8.W) // 9,0 (sel保留 6or7) + def CSR_ENTRYHI_ADDR = "b01010_000".U(8.W) // 10,0 + def CSR_COMPARE_ADDR = "b01011_000".U(8.W) // 11,0 (sel保留 6or7) + def CSR_STATUS_ADDR = "b01100_000".U(8.W) // 12,0 + // def CSR_INTCTL_ADDR = "b01100_001".U(8.W) // 12,1 + // def CSR_SRSCTL_ADDR = "b01100_010".U(8.W) // 12,2 + // def CSR_SRSMAP_ADDR = "b01100_011".U(8.W) // 12,3 + def CSR_CAUSE_ADDR = "b01101_000".U(8.W) // 13,0 + def CSR_EPC_ADDR = "b01110_000".U(8.W) // 14,0 + def CSR_PRID_ADDR = "b01111_000".U(8.W) // 15,0 + def CSR_EBASE_ADDR = "b01111_001".U(8.W) // 15,1 + // def CSR_CDMMBASE_ADDR = "b01111_010".U(8.W) // 15,2 + // def CSR_CMGCRBASE_ADDR = "b01111_011".U(8.W) // 15,3 + def CSR_CONFIG_ADDR = "b10000_000".U(8.W) // 16,0 + def CSR_CONFIG1_ADDR = "b10000_001".U(8.W) // 16,1 + // def CSR_CONFIG2_ADDR = "b10000_010".U(8.W) // 16,2 + // def CSR_CONFIG3_ADDR = "b10000_011".U(8.W) // 16,3 + // def CSR_CONFIG4_ADDR = "b10000_100".U(8.W) // 16,4 (sel保留 6or7) + // def CSR_LOAD_LINKED_ADDR = "b10001_000".U(8.W) // 17,0 + def CSR_TAGLO_ADDR = "b11100_000".U(8.W) // 28,0 + def CSR_TAGHI_ADDR = "b11101_000".U(8.W) // 29,0 + def CSR_ERROR_EPC_ADDR = "b11110_000".U(8.W) // 30,0 - val CSR_ADDR_WID = 8 + def CSR_ADDR_WID = 8 - val PTEBASE_WID = 9 + def PTEBASE_WID = 9 +} - // 例外类型 - val EXCODE_WID = 5 +object FuType { + def num = 5 + def alu = "b000".U + def lsu = "b001".U + def mdu = "b010".U + def csr = "b011".U + def mou = "b100".U + def bru = alu + def apply() = UInt(log2Up(num).W) +} - val EX_NO = 0.U(EXCODE_WID.W) // 无异常 - val EX_INT = 1.U(EXCODE_WID.W) // 中断异常 - val EX_MOD = 2.U(EXCODE_WID.W) // TLB 条目修改异常 - val EX_TLBL = 3.U(EXCODE_WID.W) // TLB 非法取指令或访问异常 - val EX_TLBS = 4.U(EXCODE_WID.W) // TLB 非法存储访问异常 - val EX_ADEL = 5.U(EXCODE_WID.W) // 地址未对齐异常（取指令或访问异常） - val EX_ADES = 6.U(EXCODE_WID.W) // 地址未对齐异常（存储访问异常） - val EX_SYS = 7.U(EXCODE_WID.W) // 系统调用异常 - val EX_BP = 8.U(EXCODE_WID.W) // 断点异常 - val EX_RI = 9.U(EXCODE_WID.W) // 保留指令异常 - val EX_CPU = 10.U(EXCODE_WID.W) // 协处理器不可用异常 - val EX_OV = 11.U(EXCODE_WID.W) // 算术溢出异常 +object BTBtype { + def B = "b00".U // branch + def J = "b01".U // jump + def I = "b10".U // indirect + def R = "b11".U // return - val EXC_INT = "h00".U(EXCODE_WID.W) // 中断异常 - val EXC_MOD = "h01".U(EXCODE_WID.W) // TLB 条目修改异常 - val EXC_TLBL = "h02".U(EXCODE_WID.W) // TLB 非法取指令或访问异常 - val EXC_TLBS = "h03".U(EXCODE_WID.W) // TLB 非法存储访问异常 - val EXC_ADEL = "h04".U(EXCODE_WID.W) // 地址未对齐异常（取指令或访问异常） - val EXC_ADES = "h05".U(EXCODE_WID.W) // 地址未对齐异常（存储访问异常） - val EXC_SYS = "h08".U(EXCODE_WID.W) // 系统调用异常 - val EXC_BP = "h09".U(EXCODE_WID.W) // 断点异常 - val EXC_RI = "h0a".U(EXCODE_WID.W) // 保留指令异常 - val EXC_CPU = "h0b".U(EXCODE_WID.W) // 协处理器不可用异常 - val EXC_OV = "h0c".U(EXCODE_WID.W) // 算术溢出异常 - val EXC_NO = "h1f".U(EXCODE_WID.W) // 无异常 + def apply() = UInt(2.W) +} - val EX_ENTRY = "h_bfc00380".U(32.W) - val EX_TLB_REFILL_ENTRY = "h_bfc00200".U(32.W) +object ALUOpType { + def add = "b1000000".U + def sll = "b0000001".U + def slt = "b0000010".U + def sltu = "b0000011".U + def xor = "b0000100".U + def srl = "b0000101".U + def or = "b0000110".U + def and = "b0000111".U + def sub = "b0001000".U + def sra = "b0001101".U - // TLB MMU - val TLB_NUM = if (config.build) 8 else 32 // for sys 32, other 8 - val PFN_WID = 20 - val C_WID = 3 - val ASID_WID = 8 - val VPN2_WID = 19 + def addw = "b1100000".U + def subw = "b0101000".U + def sllw = "b0100001".U + def srlw = "b0100101".U + def sraw = "b0101101".U + def isWordOp(func: UInt) = func(5) + + def jal = "b1011000".U + def jalr = "b1011010".U + def beq = "b0010000".U + def bne = "b0010001".U + def blt = "b0010100".U + def bge = "b0010101".U + def bltu = "b0010110".U + def bgeu = "b0010111".U + + // for RAS + def call = "b1011100".U + def ret = "b1011110".U + + def isAdd(func: UInt) = func(6) + def pcPlus2(func: UInt) = func(5) + def isBru(func: UInt) = func(4) + def isBranch(func: UInt) = !func(3) + def isJump(func: UInt) = isBru(func) && !isBranch(func) + def getBranchType(func: UInt) = func(2, 1) + def isBranchInvert(func: UInt) = func(0) +} + +object LSUOpType { //TODO: refactor LSU fuop + def lb = "b0000000".U + def lh = "b0000001".U + def lw = "b0000010".U + def ld = "b0000011".U + def lbu = "b0000100".U + def lhu = "b0000101".U + def lwu = "b0000110".U + def sb = "b0001000".U + def sh = "b0001001".U + def sw = "b0001010".U + def sd = "b0001011".U + + def lr = "b0100000".U + def sc = "b0100001".U + def amoswap = "b0100010".U + def amoadd = "b1100011".U + def amoxor = "b0100100".U + def amoand = "b0100101".U + def amoor = "b0100110".U + def amomin = "b0110111".U + def amomax = "b0110000".U + def amominu = "b0110001".U + def amomaxu = "b0110010".U + + def isAdd(func: UInt) = func(6) + def isAtom(func: UInt): Bool = func(5) + def isStore(func: UInt): Bool = func(3) + def isLoad(func: UInt): Bool = !isStore(func) & !isAtom(func) + def isLR(func: UInt): Bool = func === lr + def isSC(func: UInt): Bool = func === sc + def isAMO(func: UInt): Bool = isAtom(func) && !isLR(func) && !isSC(func) + + def needMemRead(func: UInt): Bool = isLoad(func) || isAMO(func) || isLR(func) + def needMemWrite(func: UInt): Bool = isStore(func) || isAMO(func) || isSC(func) + + def atomW = "010".U + def atomD = "011".U +} + +object MDUOpType { + def mul = "b0000".U + def mulh = "b0001".U + def mulhsu = "b0010".U + def mulhu = "b0011".U + def div = "b0100".U + def divu = "b0101".U + def rem = "b0110".U + def remu = "b0111".U + + def mulw = "b1000".U + def divw = "b1100".U + def divuw = "b1101".U + def remw = "b1110".U + def remuw = "b1111".U + + def isDiv(op: UInt) = op(2) + def isDivSign(op: UInt) = isDiv(op) && !op(0) + def isW(op: UInt) = op(3) +} + +trait AXIConst { // AXI - val BURST_FIXED = 0 - val BURST_INCR = 1 - val BURST_WRAP = 2 - val BURST_RESERVED = 3 + def BURST_FIXED = 0 + def BURST_INCR = 1 + def BURST_WRAP = 2 + def BURST_RESERVED = 3 - val RESP_OKEY = 0 - val RESP_EXOKEY = 1 - val RESP_SLVERR = 2 - val RESP_DECERR = 3 + def RESP_OKEY = 0 + def RESP_EXOKEY = 1 + def RESP_SLVERR = 2 + def RESP_DECERR = 3 } -trait OptionConst { - - // 写寄存器目标 Write Register Address type - val WRA_T1 = 0.U(2.W) // 取inst(15,11) - val WRA_T2 = 1.U(2.W) // 取inst(20,16) - val WRA_T3 = 2.U(2.W) // 取"b11111", 即31号寄存器 - val WRA_X = 0.U(2.W) // not care - val AREG_31 = "b11111".U(5.W) - - // 立即数类型 - private val IL = 3 - val IMM_N = 0.U(IL.W) - val IMM_LSE = 1.U(IL.W) // 立即数取inst(15,0)作为低16位，符号扩展，适用于ADDI，ADDIU，SLTI，和SLTIU - val IMM_LZE = 2.U(IL.W) // 立即数取inst(15,0)作为低16位，零扩展，适用于位操作指令 - val IMM_HZE = 3.U(IL.W) // 立即数取inst(15,0)作为高16位，零扩展，适用于LUI （是否有必要？） - val IMM_SHT = 4.U(IL.W) // 立即数取inst(10,6)作为低5位，不关心扩展，适用于SLL，SRL，SRA -} - -object Const extends Constants with Instructions with OptionConst +object Const extends Constants with AXIConst diff --git a/chisel/playground/src/defines/Instructions.scala b/chisel/playground/src/defines/Instructions.scala index 8d55dce..1d16478 100644 --- a/chisel/playground/src/defines/Instructions.scala +++ b/chisel/playground/src/defines/Instructions.scala @@ -3,836 +3,26 @@ package cpu.defines import chisel3._ import chisel3.util._ -object Instructions { - def ADD = BitPat("b0000000??????????000?????0110011") - def ADD_UW = BitPat("b0000100??????????000?????0111011") - def ADDI = BitPat("b?????????????????000?????0010011") - def ADDIW = BitPat("b?????????????????000?????0011011") - def ADDW = BitPat("b0000000??????????000?????0111011") - def AES64DS = BitPat("b0011101??????????000?????0110011") - def AES64DSM = BitPat("b0011111??????????000?????0110011") - def AES64ES = BitPat("b0011001??????????000?????0110011") - def AES64ESM = BitPat("b0011011??????????000?????0110011") - def AES64IM = BitPat("b001100000000?????001?????0010011") - def AES64KS1I = BitPat("b00110001?????????001?????0010011") - def AES64KS2 = BitPat("b0111111??????????000?????0110011") - def AMOADD_D = BitPat("b00000????????????011?????0101111") - def AMOADD_W = BitPat("b00000????????????010?????0101111") - def AMOAND_D = BitPat("b01100????????????011?????0101111") - def AMOAND_W = BitPat("b01100????????????010?????0101111") - def AMOMAX_D = BitPat("b10100????????????011?????0101111") - def AMOMAX_W = BitPat("b10100????????????010?????0101111") - def AMOMAXU_D = BitPat("b11100????????????011?????0101111") - def AMOMAXU_W = BitPat("b11100????????????010?????0101111") - def AMOMIN_D = BitPat("b10000????????????011?????0101111") - def AMOMIN_W = BitPat("b10000????????????010?????0101111") - def AMOMINU_D = BitPat("b11000????????????011?????0101111") - def AMOMINU_W = BitPat("b11000????????????010?????0101111") - def AMOOR_D = BitPat("b01000????????????011?????0101111") - def AMOOR_W = BitPat("b01000????????????010?????0101111") - def AMOSWAP_D = BitPat("b00001????????????011?????0101111") - def AMOSWAP_W = BitPat("b00001????????????010?????0101111") - def AMOXOR_D = BitPat("b00100????????????011?????0101111") - def AMOXOR_W = BitPat("b00100????????????010?????0101111") - def AND = BitPat("b0000000??????????111?????0110011") - def ANDI = BitPat("b?????????????????111?????0010011") - def ANDN = BitPat("b0100000??????????111?????0110011") - def AUIPC = BitPat("b?????????????????????????0010111") - def BCLR = BitPat("b0100100??????????001?????0110011") - def BCLRI = BitPat("b010010???????????001?????0010011") - def BEQ = BitPat("b?????????????????000?????1100011") - def BEXT = BitPat("b0100100??????????101?????0110011") - def BEXTI = BitPat("b010010???????????101?????0010011") - def BGE = BitPat("b?????????????????101?????1100011") - def BGEU = BitPat("b?????????????????111?????1100011") - def BINV = BitPat("b0110100??????????001?????0110011") - def BINVI = BitPat("b011010???????????001?????0010011") - def BLT = BitPat("b?????????????????100?????1100011") - def BLTU = BitPat("b?????????????????110?????1100011") - def BNE = BitPat("b?????????????????001?????1100011") - def BREV8 = BitPat("b011010000111?????101?????0010011") - def BSET = BitPat("b0010100??????????001?????0110011") - def BSETI = BitPat("b001010???????????001?????0010011") - def C_ADD = BitPat("b????????????????1001??????????10") - def C_ADDI = BitPat("b????????????????000???????????01") - def C_ADDI16SP = BitPat("b????????????????011?00010?????01") - def C_ADDI4SPN = BitPat("b????????????????000???????????00") - def C_ADDIW = BitPat("b????????????????001???????????01") - def C_ADDW = BitPat("b????????????????100111???01???01") - def C_AND = BitPat("b????????????????100011???11???01") - def C_ANDI = BitPat("b????????????????100?10????????01") - def C_BEQZ = BitPat("b????????????????110???????????01") - def C_BNEZ = BitPat("b????????????????111???????????01") - def C_EBREAK = BitPat("b????????????????1001000000000010") - def C_FLD = BitPat("b????????????????001???????????00") - def C_FLDSP = BitPat("b????????????????001???????????10") - def C_FSD = BitPat("b????????????????101???????????00") - def C_FSDSP = BitPat("b????????????????101???????????10") - def C_J = BitPat("b????????????????101???????????01") - def C_JALR = BitPat("b????????????????1001?????0000010") - def C_JR = BitPat("b????????????????1000?????0000010") - def C_LD = BitPat("b????????????????011???????????00") - def C_LDSP = BitPat("b????????????????011???????????10") - def C_LI = BitPat("b????????????????010???????????01") - def C_LUI = BitPat("b????????????????011???????????01") - def C_LW = BitPat("b????????????????010???????????00") - def C_LWSP = BitPat("b????????????????010???????????10") - def C_MV = BitPat("b????????????????1000??????????10") - def C_NOP = BitPat("b????????????????000?00000?????01") - def C_OR = BitPat("b????????????????100011???10???01") - def C_SD = BitPat("b????????????????111???????????00") - def C_SDSP = BitPat("b????????????????111???????????10") - def C_SLLI = BitPat("b????????????????000???????????10") - def C_SRAI = BitPat("b????????????????100?01????????01") - def C_SRLI = BitPat("b????????????????100?00????????01") - def C_SUB = BitPat("b????????????????100011???00???01") - def C_SUBW = BitPat("b????????????????100111???00???01") - def C_SW = BitPat("b????????????????110???????????00") - def C_SWSP = BitPat("b????????????????110???????????10") - def C_XOR = BitPat("b????????????????100011???01???01") - def CBO_CLEAN = BitPat("b000000000001?????010000000001111") - def CBO_FLUSH = BitPat("b000000000010?????010000000001111") - def CBO_INVAL = BitPat("b000000000000?????010000000001111") - def CBO_ZERO = BitPat("b000000000100?????010000000001111") - def CLMUL = BitPat("b0000101??????????001?????0110011") - def CLMULH = BitPat("b0000101??????????011?????0110011") - def CLMULR = BitPat("b0000101??????????010?????0110011") - def CLZ = BitPat("b011000000000?????001?????0010011") - def CLZW = BitPat("b011000000000?????001?????0011011") - def CPOP = BitPat("b011000000010?????001?????0010011") - def CPOPW = BitPat("b011000000010?????001?????0011011") - def CSRRC = BitPat("b?????????????????011?????1110011") - def CSRRCI = BitPat("b?????????????????111?????1110011") - def CSRRS = BitPat("b?????????????????010?????1110011") - def CSRRSI = BitPat("b?????????????????110?????1110011") - def CSRRW = BitPat("b?????????????????001?????1110011") - def CSRRWI = BitPat("b?????????????????101?????1110011") - def CZERO_EQZ = BitPat("b0000111??????????101?????0110011") - def CZERO_NEZ = BitPat("b0000111??????????111?????0110011") - def CTZ = BitPat("b011000000001?????001?????0010011") - def CTZW = BitPat("b011000000001?????001?????0011011") - def DIV = BitPat("b0000001??????????100?????0110011") - def DIVU = BitPat("b0000001??????????101?????0110011") - def DIVUW = BitPat("b0000001??????????101?????0111011") - def DIVW = BitPat("b0000001??????????100?????0111011") - def DRET = BitPat("b01111011001000000000000001110011") - def EBREAK = BitPat("b00000000000100000000000001110011") - def ECALL = BitPat("b00000000000000000000000001110011") - def FADD_D = BitPat("b0000001??????????????????1010011") - def FADD_H = BitPat("b0000010??????????????????1010011") - def FADD_Q = BitPat("b0000011??????????????????1010011") - def FADD_S = BitPat("b0000000??????????????????1010011") - def FCLASS_D = BitPat("b111000100000?????001?????1010011") - def FCLASS_H = BitPat("b111001000000?????001?????1010011") - def FCLASS_Q = BitPat("b111001100000?????001?????1010011") - def FCLASS_S = BitPat("b111000000000?????001?????1010011") - def FCVT_D_H = BitPat("b010000100010?????????????1010011") - def FCVT_D_L = BitPat("b110100100010?????????????1010011") - def FCVT_D_LU = BitPat("b110100100011?????????????1010011") - def FCVT_D_Q = BitPat("b010000100011?????????????1010011") - def FCVT_D_S = BitPat("b010000100000?????????????1010011") - def FCVT_D_W = BitPat("b110100100000?????????????1010011") - def FCVT_D_WU = BitPat("b110100100001?????????????1010011") - def FCVT_H_D = BitPat("b010001000001?????????????1010011") - def FCVT_H_L = BitPat("b110101000010?????????????1010011") - def FCVT_H_LU = BitPat("b110101000011?????????????1010011") - def FCVT_H_Q = BitPat("b010001000011?????????????1010011") - def FCVT_H_S = BitPat("b010001000000?????????????1010011") - def FCVT_H_W = BitPat("b110101000000?????????????1010011") - def FCVT_H_WU = BitPat("b110101000001?????????????1010011") - def FCVT_L_D = BitPat("b110000100010?????????????1010011") - def FCVT_L_H = BitPat("b110001000010?????????????1010011") - def FCVT_L_Q = BitPat("b110001100010?????????????1010011") - def FCVT_L_S = BitPat("b110000000010?????????????1010011") - def FCVT_LU_D = BitPat("b110000100011?????????????1010011") - def FCVT_LU_H = BitPat("b110001000011?????????????1010011") - def FCVT_LU_Q = BitPat("b110001100011?????????????1010011") - def FCVT_LU_S = BitPat("b110000000011?????????????1010011") - def FCVT_Q_D = BitPat("b010001100001?????????????1010011") - def FCVT_Q_H = BitPat("b010001100010?????????????1010011") - def FCVT_Q_L = BitPat("b110101100010?????????????1010011") - def FCVT_Q_LU = BitPat("b110101100011?????????????1010011") - def FCVT_Q_S = BitPat("b010001100000?????????????1010011") - def FCVT_Q_W = BitPat("b110101100000?????????????1010011") - def FCVT_Q_WU = BitPat("b110101100001?????????????1010011") - def FCVT_S_D = BitPat("b010000000001?????????????1010011") - def FCVT_S_H = BitPat("b010000000010?????????????1010011") - def FCVT_S_L = BitPat("b110100000010?????????????1010011") - def FCVT_S_LU = BitPat("b110100000011?????????????1010011") - def FCVT_S_Q = BitPat("b010000000011?????????????1010011") - def FCVT_S_W = BitPat("b110100000000?????????????1010011") - def FCVT_S_WU = BitPat("b110100000001?????????????1010011") - def FCVT_W_D = BitPat("b110000100000?????????????1010011") - def FCVT_W_H = BitPat("b110001000000?????????????1010011") - def FCVT_W_Q = BitPat("b110001100000?????????????1010011") - def FCVT_W_S = BitPat("b110000000000?????????????1010011") - def FCVT_WU_D = BitPat("b110000100001?????????????1010011") - def FCVT_WU_H = BitPat("b110001000001?????????????1010011") - def FCVT_WU_Q = BitPat("b110001100001?????????????1010011") - def FCVT_WU_S = BitPat("b110000000001?????????????1010011") - def FDIV_D = BitPat("b0001101??????????????????1010011") - def FDIV_H = BitPat("b0001110??????????????????1010011") - def FDIV_Q = BitPat("b0001111??????????????????1010011") - def FDIV_S = BitPat("b0001100??????????????????1010011") - def FENCE = BitPat("b?????????????????000?????0001111") - def FENCE_I = BitPat("b?????????????????001?????0001111") - def FEQ_D = BitPat("b1010001??????????010?????1010011") - def FEQ_H = BitPat("b1010010??????????010?????1010011") - def FEQ_Q = BitPat("b1010011??????????010?????1010011") - def FEQ_S = BitPat("b1010000??????????010?????1010011") - def FLD = BitPat("b?????????????????011?????0000111") - def FLE_D = BitPat("b1010001??????????000?????1010011") - def FLE_H = BitPat("b1010010??????????000?????1010011") - def FLE_Q = BitPat("b1010011??????????000?????1010011") - def FLE_S = BitPat("b1010000??????????000?????1010011") - def FLH = BitPat("b?????????????????001?????0000111") - def FLQ = BitPat("b?????????????????100?????0000111") - def FLT_D = BitPat("b1010001??????????001?????1010011") - def FLT_H = BitPat("b1010010??????????001?????1010011") - def FLT_Q = BitPat("b1010011??????????001?????1010011") - def FLT_S = BitPat("b1010000??????????001?????1010011") - def FLW = BitPat("b?????????????????010?????0000111") - def FMADD_D = BitPat("b?????01??????????????????1000011") - def FMADD_H = BitPat("b?????10??????????????????1000011") - def FMADD_Q = BitPat("b?????11??????????????????1000011") - def FMADD_S = BitPat("b?????00??????????????????1000011") - def FMAX_D = BitPat("b0010101??????????001?????1010011") - def FMAX_H = BitPat("b0010110??????????001?????1010011") - def FMAX_Q = BitPat("b0010111??????????001?????1010011") - def FMAX_S = BitPat("b0010100??????????001?????1010011") - def FMIN_D = BitPat("b0010101??????????000?????1010011") - def FMIN_H = BitPat("b0010110??????????000?????1010011") - def FMIN_Q = BitPat("b0010111??????????000?????1010011") - def FMIN_S = BitPat("b0010100??????????000?????1010011") - def FMSUB_D = BitPat("b?????01??????????????????1000111") - def FMSUB_H = BitPat("b?????10??????????????????1000111") - def FMSUB_Q = BitPat("b?????11??????????????????1000111") - def FMSUB_S = BitPat("b?????00??????????????????1000111") - def FMUL_D = BitPat("b0001001??????????????????1010011") - def FMUL_H = BitPat("b0001010??????????????????1010011") - def FMUL_Q = BitPat("b0001011??????????????????1010011") - def FMUL_S = BitPat("b0001000??????????????????1010011") - def FMV_D_X = BitPat("b111100100000?????000?????1010011") - def FMV_H_X = BitPat("b111101000000?????000?????1010011") - def FMV_W_X = BitPat("b111100000000?????000?????1010011") - def FMV_X_D = BitPat("b111000100000?????000?????1010011") - def FMV_X_H = BitPat("b111001000000?????000?????1010011") - def FMV_X_W = BitPat("b111000000000?????000?????1010011") - def FNMADD_D = BitPat("b?????01??????????????????1001111") - def FNMADD_H = BitPat("b?????10??????????????????1001111") - def FNMADD_Q = BitPat("b?????11??????????????????1001111") - def FNMADD_S = BitPat("b?????00??????????????????1001111") - def FNMSUB_D = BitPat("b?????01??????????????????1001011") - def FNMSUB_H = BitPat("b?????10??????????????????1001011") - def FNMSUB_Q = BitPat("b?????11??????????????????1001011") - def FNMSUB_S = BitPat("b?????00??????????????????1001011") - def FSD = BitPat("b?????????????????011?????0100111") - def FSGNJ_D = BitPat("b0010001??????????000?????1010011") - def FSGNJ_H = BitPat("b0010010??????????000?????1010011") - def FSGNJ_Q = BitPat("b0010011??????????000?????1010011") - def FSGNJ_S = BitPat("b0010000??????????000?????1010011") - def FSGNJN_D = BitPat("b0010001??????????001?????1010011") - def FSGNJN_H = BitPat("b0010010??????????001?????1010011") - def FSGNJN_Q = BitPat("b0010011??????????001?????1010011") - def FSGNJN_S = BitPat("b0010000??????????001?????1010011") - def FSGNJX_D = BitPat("b0010001??????????010?????1010011") - def FSGNJX_H = BitPat("b0010010??????????010?????1010011") - def FSGNJX_Q = BitPat("b0010011??????????010?????1010011") - def FSGNJX_S = BitPat("b0010000??????????010?????1010011") - def FSH = BitPat("b?????????????????001?????0100111") - def FSQ = BitPat("b?????????????????100?????0100111") - def FSQRT_D = BitPat("b010110100000?????????????1010011") - def FSQRT_H = BitPat("b010111000000?????????????1010011") - def FSQRT_Q = BitPat("b010111100000?????????????1010011") - def FSQRT_S = BitPat("b010110000000?????????????1010011") - def FSUB_D = BitPat("b0000101??????????????????1010011") - def FSUB_H = BitPat("b0000110??????????????????1010011") - def FSUB_Q = BitPat("b0000111??????????????????1010011") - def FSUB_S = BitPat("b0000100??????????????????1010011") - def FSW = BitPat("b?????????????????010?????0100111") - def HFENCE_GVMA = BitPat("b0110001??????????000000001110011") - def HFENCE_VVMA = BitPat("b0010001??????????000000001110011") - def HINVAL_GVMA = BitPat("b0110011??????????000000001110011") - def HINVAL_VVMA = BitPat("b0010011??????????000000001110011") - def HLV_B = BitPat("b011000000000?????100?????1110011") - def HLV_BU = BitPat("b011000000001?????100?????1110011") - def HLV_D = BitPat("b011011000000?????100?????1110011") - def HLV_H = BitPat("b011001000000?????100?????1110011") - def HLV_HU = BitPat("b011001000001?????100?????1110011") - def HLV_W = BitPat("b011010000000?????100?????1110011") - def HLV_WU = BitPat("b011010000001?????100?????1110011") - def HLVX_HU = BitPat("b011001000011?????100?????1110011") - def HLVX_WU = BitPat("b011010000011?????100?????1110011") - def HSV_B = BitPat("b0110001??????????100000001110011") - def HSV_D = BitPat("b0110111??????????100000001110011") - def HSV_H = BitPat("b0110011??????????100000001110011") - def HSV_W = BitPat("b0110101??????????100000001110011") - def JAL = BitPat("b?????????????????????????1101111") - def JALR = BitPat("b?????????????????000?????1100111") - def LB = BitPat("b?????????????????000?????0000011") - def LBU = BitPat("b?????????????????100?????0000011") - def LD = BitPat("b?????????????????011?????0000011") - def LH = BitPat("b?????????????????001?????0000011") - def LHU = BitPat("b?????????????????101?????0000011") - def LR_D = BitPat("b00010??00000?????011?????0101111") - def LR_W = BitPat("b00010??00000?????010?????0101111") - def LUI = BitPat("b?????????????????????????0110111") - def LW = BitPat("b?????????????????010?????0000011") - def LWU = BitPat("b?????????????????110?????0000011") - def MAX = BitPat("b0000101??????????110?????0110011") - def MAXU = BitPat("b0000101??????????111?????0110011") - def MIN = BitPat("b0000101??????????100?????0110011") - def MINU = BitPat("b0000101??????????101?????0110011") - def MRET = BitPat("b00110000001000000000000001110011") - def MUL = BitPat("b0000001??????????000?????0110011") - def MULH = BitPat("b0000001??????????001?????0110011") - def MULHSU = BitPat("b0000001??????????010?????0110011") - def MULHU = BitPat("b0000001??????????011?????0110011") - def MULW = BitPat("b0000001??????????000?????0111011") - def OR = BitPat("b0000000??????????110?????0110011") - def ORC_B = BitPat("b001010000111?????101?????0010011") - def ORI = BitPat("b?????????????????110?????0010011") - def ORN = BitPat("b0100000??????????110?????0110011") - def PACK = BitPat("b0000100??????????100?????0110011") - def PACKH = BitPat("b0000100??????????111?????0110011") - def PACKW = BitPat("b0000100??????????100?????0111011") - def REM = BitPat("b0000001??????????110?????0110011") - def REMU = BitPat("b0000001??????????111?????0110011") - def REMUW = BitPat("b0000001??????????111?????0111011") - def REMW = BitPat("b0000001??????????110?????0111011") - def REV8 = BitPat("b011010111000?????101?????0010011") - def ROL = BitPat("b0110000??????????001?????0110011") - def ROLW = BitPat("b0110000??????????001?????0111011") - def ROR = BitPat("b0110000??????????101?????0110011") - def RORI = BitPat("b011000???????????101?????0010011") - def RORIW = BitPat("b0110000??????????101?????0011011") - def RORW = BitPat("b0110000??????????101?????0111011") - def SB = BitPat("b?????????????????000?????0100011") - def SC_D = BitPat("b00011????????????011?????0101111") - def SC_W = BitPat("b00011????????????010?????0101111") - def SD = BitPat("b?????????????????011?????0100011") - def SEXT_B = BitPat("b011000000100?????001?????0010011") - def SEXT_H = BitPat("b011000000101?????001?????0010011") - def SFENCE_INVAL_IR = BitPat("b00011000000100000000000001110011") - def SFENCE_VMA = BitPat("b0001001??????????000000001110011") - def SFENCE_W_INVAL = BitPat("b00011000000000000000000001110011") - def SH = BitPat("b?????????????????001?????0100011") - def SH1ADD = BitPat("b0010000??????????010?????0110011") - def SH1ADD_UW = BitPat("b0010000??????????010?????0111011") - def SH2ADD = BitPat("b0010000??????????100?????0110011") - def SH2ADD_UW = BitPat("b0010000??????????100?????0111011") - def SH3ADD = BitPat("b0010000??????????110?????0110011") - def SH3ADD_UW = BitPat("b0010000??????????110?????0111011") - def SHA256SIG0 = BitPat("b000100000010?????001?????0010011") - def SHA256SIG1 = BitPat("b000100000011?????001?????0010011") - def SHA256SUM0 = BitPat("b000100000000?????001?????0010011") - def SHA256SUM1 = BitPat("b000100000001?????001?????0010011") - def SHA512SIG0 = BitPat("b000100000110?????001?????0010011") - def SHA512SIG1 = BitPat("b000100000111?????001?????0010011") - def SHA512SUM0 = BitPat("b000100000100?????001?????0010011") - def SHA512SUM1 = BitPat("b000100000101?????001?????0010011") - def SINVAL_VMA = BitPat("b0001011??????????000000001110011") - def SLL = BitPat("b0000000??????????001?????0110011") - def SLLI = BitPat("b000000???????????001?????0010011") - def SLLI_UW = BitPat("b000010???????????001?????0011011") - def SLLIW = BitPat("b0000000??????????001?????0011011") - def SLLW = BitPat("b0000000??????????001?????0111011") - def SLT = BitPat("b0000000??????????010?????0110011") - def SLTI = BitPat("b?????????????????010?????0010011") - def SLTIU = BitPat("b?????????????????011?????0010011") - def SLTU = BitPat("b0000000??????????011?????0110011") - def SM3P0 = BitPat("b000100001000?????001?????0010011") - def SM3P1 = BitPat("b000100001001?????001?????0010011") - def SM4ED = BitPat("b??11000??????????000?????0110011") - def SM4KS = BitPat("b??11010??????????000?????0110011") - def SRA = BitPat("b0100000??????????101?????0110011") - def SRAI = BitPat("b010000???????????101?????0010011") - def SRAIW = BitPat("b0100000??????????101?????0011011") - def SRAW = BitPat("b0100000??????????101?????0111011") - def SRET = BitPat("b00010000001000000000000001110011") - def SRL = BitPat("b0000000??????????101?????0110011") - def SRLI = BitPat("b000000???????????101?????0010011") - def SRLIW = BitPat("b0000000??????????101?????0011011") - def SRLW = BitPat("b0000000??????????101?????0111011") - def SUB = BitPat("b0100000??????????000?????0110011") - def SUBW = BitPat("b0100000??????????000?????0111011") - def SW = BitPat("b?????????????????010?????0100011") - def VAADD_VV = BitPat("b001001???????????010?????1010111") - def VAADD_VX = BitPat("b001001???????????110?????1010111") - def VAADDU_VV = BitPat("b001000???????????010?????1010111") - def VAADDU_VX = BitPat("b001000???????????110?????1010111") - def VADC_VIM = BitPat("b0100000??????????011?????1010111") - def VADC_VVM = BitPat("b0100000??????????000?????1010111") - def VADC_VXM = BitPat("b0100000??????????100?????1010111") - def VADD_VI = BitPat("b000000???????????011?????1010111") - def VADD_VV = BitPat("b000000???????????000?????1010111") - def VADD_VX = BitPat("b000000???????????100?????1010111") - def VAMOADDEI16_V = BitPat("b00000????????????101?????0101111") - def VAMOADDEI32_V = BitPat("b00000????????????110?????0101111") - def VAMOADDEI64_V = BitPat("b00000????????????111?????0101111") - def VAMOADDEI8_V = BitPat("b00000????????????000?????0101111") - def VAMOANDEI16_V = BitPat("b01100????????????101?????0101111") - def VAMOANDEI32_V = BitPat("b01100????????????110?????0101111") - def VAMOANDEI64_V = BitPat("b01100????????????111?????0101111") - def VAMOANDEI8_V = BitPat("b01100????????????000?????0101111") - def VAMOMAXEI16_V = BitPat("b10100????????????101?????0101111") - def VAMOMAXEI32_V = BitPat("b10100????????????110?????0101111") - def VAMOMAXEI64_V = BitPat("b10100????????????111?????0101111") - def VAMOMAXEI8_V = BitPat("b10100????????????000?????0101111") - def VAMOMAXUEI16_V = BitPat("b11100????????????101?????0101111") - def VAMOMAXUEI32_V = BitPat("b11100????????????110?????0101111") - def VAMOMAXUEI64_V = BitPat("b11100????????????111?????0101111") - def VAMOMAXUEI8_V = BitPat("b11100????????????000?????0101111") - def VAMOMINEI16_V = BitPat("b10000????????????101?????0101111") - def VAMOMINEI32_V = BitPat("b10000????????????110?????0101111") - def VAMOMINEI64_V = BitPat("b10000????????????111?????0101111") - def VAMOMINEI8_V = BitPat("b10000????????????000?????0101111") - def VAMOMINUEI16_V = BitPat("b11000????????????101?????0101111") - def VAMOMINUEI32_V = BitPat("b11000????????????110?????0101111") - def VAMOMINUEI64_V = BitPat("b11000????????????111?????0101111") - def VAMOMINUEI8_V = BitPat("b11000????????????000?????0101111") - def VAMOOREI16_V = BitPat("b01000????????????101?????0101111") - def VAMOOREI32_V = BitPat("b01000????????????110?????0101111") - def VAMOOREI64_V = BitPat("b01000????????????111?????0101111") - def VAMOOREI8_V = BitPat("b01000????????????000?????0101111") - def VAMOSWAPEI16_V = BitPat("b00001????????????101?????0101111") - def VAMOSWAPEI32_V = BitPat("b00001????????????110?????0101111") - def VAMOSWAPEI64_V = BitPat("b00001????????????111?????0101111") - def VAMOSWAPEI8_V = BitPat("b00001????????????000?????0101111") - def VAMOXOREI16_V = BitPat("b00100????????????101?????0101111") - def VAMOXOREI32_V = BitPat("b00100????????????110?????0101111") - def VAMOXOREI64_V = BitPat("b00100????????????111?????0101111") - def VAMOXOREI8_V = BitPat("b00100????????????000?????0101111") - def VAND_VI = BitPat("b001001???????????011?????1010111") - def VAND_VV = BitPat("b001001???????????000?????1010111") - def VAND_VX = BitPat("b001001???????????100?????1010111") - def VASUB_VV = BitPat("b001011???????????010?????1010111") - def VASUB_VX = BitPat("b001011???????????110?????1010111") - def VASUBU_VV = BitPat("b001010???????????010?????1010111") - def VASUBU_VX = BitPat("b001010???????????110?????1010111") - def VCOMPRESS_VM = BitPat("b0101111??????????010?????1010111") - def VCPOP_M = BitPat("b010000??????10000010?????1010111") - def VDIV_VV = BitPat("b100001???????????010?????1010111") - def VDIV_VX = BitPat("b100001???????????110?????1010111") - def VDIVU_VV = BitPat("b100000???????????010?????1010111") - def VDIVU_VX = BitPat("b100000???????????110?????1010111") - def VFADD_VF = BitPat("b000000???????????101?????1010111") - def VFADD_VV = BitPat("b000000???????????001?????1010111") - def VFCLASS_V = BitPat("b010011??????10000001?????1010111") - def VFCVT_F_X_V = BitPat("b010010??????00011001?????1010111") - def VFCVT_F_XU_V = BitPat("b010010??????00010001?????1010111") - def VFCVT_RTZ_X_F_V = BitPat("b010010??????00111001?????1010111") - def VFCVT_RTZ_XU_F_V = BitPat("b010010??????00110001?????1010111") - def VFCVT_X_F_V = BitPat("b010010??????00001001?????1010111") - def VFCVT_XU_F_V = BitPat("b010010??????00000001?????1010111") - def VFDIV_VF = BitPat("b100000???????????101?????1010111") - def VFDIV_VV = BitPat("b100000???????????001?????1010111") - def VFIRST_M = BitPat("b010000??????10001010?????1010111") - def VFMACC_VF = BitPat("b101100???????????101?????1010111") - def VFMACC_VV = BitPat("b101100???????????001?????1010111") - def VFMADD_VF = BitPat("b101000???????????101?????1010111") - def VFMADD_VV = BitPat("b101000???????????001?????1010111") - def VFMAX_VF = BitPat("b000110???????????101?????1010111") - def VFMAX_VV = BitPat("b000110???????????001?????1010111") - def VFMERGE_VFM = BitPat("b0101110??????????101?????1010111") - def VFMIN_VF = BitPat("b000100???????????101?????1010111") - def VFMIN_VV = BitPat("b000100???????????001?????1010111") - def VFMSAC_VF = BitPat("b101110???????????101?????1010111") - def VFMSAC_VV = BitPat("b101110???????????001?????1010111") - def VFMSUB_VF = BitPat("b101010???????????101?????1010111") - def VFMSUB_VV = BitPat("b101010???????????001?????1010111") - def VFMUL_VF = BitPat("b100100???????????101?????1010111") - def VFMUL_VV = BitPat("b100100???????????001?????1010111") - def VFMV_F_S = BitPat("b0100001?????00000001?????1010111") - def VFMV_S_F = BitPat("b010000100000?????101?????1010111") - def VFMV_V_F = BitPat("b010111100000?????101?????1010111") - def VFNCVT_F_F_W = BitPat("b010010??????10100001?????1010111") - def VFNCVT_F_X_W = BitPat("b010010??????10011001?????1010111") - def VFNCVT_F_XU_W = BitPat("b010010??????10010001?????1010111") - def VFNCVT_ROD_F_F_W = BitPat("b010010??????10101001?????1010111") - def VFNCVT_RTZ_X_F_W = BitPat("b010010??????10111001?????1010111") - def VFNCVT_RTZ_XU_F_W = BitPat("b010010??????10110001?????1010111") - def VFNCVT_X_F_W = BitPat("b010010??????10001001?????1010111") - def VFNCVT_XU_F_W = BitPat("b010010??????10000001?????1010111") - def VFNMACC_VF = BitPat("b101101???????????101?????1010111") - def VFNMACC_VV = BitPat("b101101???????????001?????1010111") - def VFNMADD_VF = BitPat("b101001???????????101?????1010111") - def VFNMADD_VV = BitPat("b101001???????????001?????1010111") - def VFNMSAC_VF = BitPat("b101111???????????101?????1010111") - def VFNMSAC_VV = BitPat("b101111???????????001?????1010111") - def VFNMSUB_VF = BitPat("b101011???????????101?????1010111") - def VFNMSUB_VV = BitPat("b101011???????????001?????1010111") - def VFRDIV_VF = BitPat("b100001???????????101?????1010111") - def VFREC7_V = BitPat("b010011??????00101001?????1010111") - def VFREDMAX_VS = BitPat("b000111???????????001?????1010111") - def VFREDMIN_VS = BitPat("b000101???????????001?????1010111") - def VFREDOSUM_VS = BitPat("b000011???????????001?????1010111") - def VFREDUSUM_VS = BitPat("b000001???????????001?????1010111") - def VFRSQRT7_V = BitPat("b010011??????00100001?????1010111") - def VFRSUB_VF = BitPat("b100111???????????101?????1010111") - def VFSGNJ_VF = BitPat("b001000???????????101?????1010111") - def VFSGNJ_VV = BitPat("b001000???????????001?????1010111") - def VFSGNJN_VF = BitPat("b001001???????????101?????1010111") - def VFSGNJN_VV = BitPat("b001001???????????001?????1010111") - def VFSGNJX_VF = BitPat("b001010???????????101?????1010111") - def VFSGNJX_VV = BitPat("b001010???????????001?????1010111") - def VFSLIDE1DOWN_VF = BitPat("b001111???????????101?????1010111") - def VFSLIDE1UP_VF = BitPat("b001110???????????101?????1010111") - def VFSQRT_V = BitPat("b010011??????00000001?????1010111") - def VFSUB_VF = BitPat("b000010???????????101?????1010111") - def VFSUB_VV = BitPat("b000010???????????001?????1010111") - def VFWADD_VF = BitPat("b110000???????????101?????1010111") - def VFWADD_VV = BitPat("b110000???????????001?????1010111") - def VFWADD_WF = BitPat("b110100???????????101?????1010111") - def VFWADD_WV = BitPat("b110100???????????001?????1010111") - def VFWCVT_F_F_V = BitPat("b010010??????01100001?????1010111") - def VFWCVT_F_X_V = BitPat("b010010??????01011001?????1010111") - def VFWCVT_F_XU_V = BitPat("b010010??????01010001?????1010111") - def VFWCVT_RTZ_X_F_V = BitPat("b010010??????01111001?????1010111") - def VFWCVT_RTZ_XU_F_V = BitPat("b010010??????01110001?????1010111") - def VFWCVT_X_F_V = BitPat("b010010??????01001001?????1010111") - def VFWCVT_XU_F_V = BitPat("b010010??????01000001?????1010111") - def VFWMACC_VF = BitPat("b111100???????????101?????1010111") - def VFWMACC_VV = BitPat("b111100???????????001?????1010111") - def VFWMSAC_VF = BitPat("b111110???????????101?????1010111") - def VFWMSAC_VV = BitPat("b111110???????????001?????1010111") - def VFWMUL_VF = BitPat("b111000???????????101?????1010111") - def VFWMUL_VV = BitPat("b111000???????????001?????1010111") - def VFWNMACC_VF = BitPat("b111101???????????101?????1010111") - def VFWNMACC_VV = BitPat("b111101???????????001?????1010111") - def VFWNMSAC_VF = BitPat("b111111???????????101?????1010111") - def VFWNMSAC_VV = BitPat("b111111???????????001?????1010111") - def VFWREDOSUM_VS = BitPat("b110011???????????001?????1010111") - def VFWREDUSUM_VS = BitPat("b110001???????????001?????1010111") - def VFWSUB_VF = BitPat("b110010???????????101?????1010111") - def VFWSUB_VV = BitPat("b110010???????????001?????1010111") - def VFWSUB_WF = BitPat("b110110???????????101?????1010111") - def VFWSUB_WV = BitPat("b110110???????????001?????1010111") - def VID_V = BitPat("b010100?0000010001010?????1010111") - def VIOTA_M = BitPat("b010100??????10000010?????1010111") - def VL1RE16_V = BitPat("b000000101000?????101?????0000111") - def VL1RE32_V = BitPat("b000000101000?????110?????0000111") - def VL1RE64_V = BitPat("b000000101000?????111?????0000111") - def VL1RE8_V = BitPat("b000000101000?????000?????0000111") - def VL2RE16_V = BitPat("b001000101000?????101?????0000111") - def VL2RE32_V = BitPat("b001000101000?????110?????0000111") - def VL2RE64_V = BitPat("b001000101000?????111?????0000111") - def VL2RE8_V = BitPat("b001000101000?????000?????0000111") - def VL4RE16_V = BitPat("b011000101000?????101?????0000111") - def VL4RE32_V = BitPat("b011000101000?????110?????0000111") - def VL4RE64_V = BitPat("b011000101000?????111?????0000111") - def VL4RE8_V = BitPat("b011000101000?????000?????0000111") - def VL8RE16_V = BitPat("b111000101000?????101?????0000111") - def VL8RE32_V = BitPat("b111000101000?????110?????0000111") - def VL8RE64_V = BitPat("b111000101000?????111?????0000111") - def VL8RE8_V = BitPat("b111000101000?????000?????0000111") - def VLE1024_V = BitPat("b???100?00000?????111?????0000111") - def VLE1024FF_V = BitPat("b???100?10000?????111?????0000111") - def VLE128_V = BitPat("b???100?00000?????000?????0000111") - def VLE128FF_V = BitPat("b???100?10000?????000?????0000111") - def VLE16_V = BitPat("b???000?00000?????101?????0000111") - def VLE16FF_V = BitPat("b???000?10000?????101?????0000111") - def VLE256_V = BitPat("b???100?00000?????101?????0000111") - def VLE256FF_V = BitPat("b???100?10000?????101?????0000111") - def VLE32_V = BitPat("b???000?00000?????110?????0000111") - def VLE32FF_V = BitPat("b???000?10000?????110?????0000111") - def VLE512_V = BitPat("b???100?00000?????110?????0000111") - def VLE512FF_V = BitPat("b???100?10000?????110?????0000111") - def VLE64_V = BitPat("b???000?00000?????111?????0000111") - def VLE64FF_V = BitPat("b???000?10000?????111?????0000111") - def VLE8_V = BitPat("b???000?00000?????000?????0000111") - def VLE8FF_V = BitPat("b???000?10000?????000?????0000111") - def VLM_V = BitPat("b000000101011?????000?????0000111") - def VLOXEI1024_V = BitPat("b???111???????????111?????0000111") - def VLOXEI128_V = BitPat("b???111???????????000?????0000111") - def VLOXEI16_V = BitPat("b???011???????????101?????0000111") - def VLOXEI256_V = BitPat("b???111???????????101?????0000111") - def VLOXEI32_V = BitPat("b???011???????????110?????0000111") - def VLOXEI512_V = BitPat("b???111???????????110?????0000111") - def VLOXEI64_V = BitPat("b???011???????????111?????0000111") - def VLOXEI8_V = BitPat("b???011???????????000?????0000111") - def VLSE1024_V = BitPat("b???110???????????111?????0000111") - def VLSE128_V = BitPat("b???110???????????000?????0000111") - def VLSE16_V = BitPat("b???010???????????101?????0000111") - def VLSE256_V = BitPat("b???110???????????101?????0000111") - def VLSE32_V = BitPat("b???010???????????110?????0000111") - def VLSE512_V = BitPat("b???110???????????110?????0000111") - def VLSE64_V = BitPat("b???010???????????111?????0000111") - def VLSE8_V = BitPat("b???010???????????000?????0000111") - def VLUXEI1024_V = BitPat("b???101???????????111?????0000111") - def VLUXEI128_V = BitPat("b???101???????????000?????0000111") - def VLUXEI16_V = BitPat("b???001???????????101?????0000111") - def VLUXEI256_V = BitPat("b???101???????????101?????0000111") - def VLUXEI32_V = BitPat("b???001???????????110?????0000111") - def VLUXEI512_V = BitPat("b???101???????????110?????0000111") - def VLUXEI64_V = BitPat("b???001???????????111?????0000111") - def VLUXEI8_V = BitPat("b???001???????????000?????0000111") - def VMACC_VV = BitPat("b101101???????????010?????1010111") - def VMACC_VX = BitPat("b101101???????????110?????1010111") - def VMADC_VI = BitPat("b0100011??????????011?????1010111") - def VMADC_VIM = BitPat("b0100010??????????011?????1010111") - def VMADC_VV = BitPat("b0100011??????????000?????1010111") - def VMADC_VVM = BitPat("b0100010??????????000?????1010111") - def VMADC_VX = BitPat("b0100011??????????100?????1010111") - def VMADC_VXM = BitPat("b0100010??????????100?????1010111") - def VMADD_VV = BitPat("b101001???????????010?????1010111") - def VMADD_VX = BitPat("b101001???????????110?????1010111") - def VMAND_MM = BitPat("b011001???????????010?????1010111") - def VMANDN_MM = BitPat("b011000???????????010?????1010111") - def VMAX_VV = BitPat("b000111???????????000?????1010111") - def VMAX_VX = BitPat("b000111???????????100?????1010111") - def VMAXU_VV = BitPat("b000110???????????000?????1010111") - def VMAXU_VX = BitPat("b000110???????????100?????1010111") - def VMERGE_VIM = BitPat("b0101110??????????011?????1010111") - def VMERGE_VVM = BitPat("b0101110??????????000?????1010111") - def VMERGE_VXM = BitPat("b0101110??????????100?????1010111") - def VMFEQ_VF = BitPat("b011000???????????101?????1010111") - def VMFEQ_VV = BitPat("b011000???????????001?????1010111") - def VMFGE_VF = BitPat("b011111???????????101?????1010111") - def VMFGT_VF = BitPat("b011101???????????101?????1010111") - def VMFLE_VF = BitPat("b011001???????????101?????1010111") - def VMFLE_VV = BitPat("b011001???????????001?????1010111") - def VMFLT_VF = BitPat("b011011???????????101?????1010111") - def VMFLT_VV = BitPat("b011011???????????001?????1010111") - def VMFNE_VF = BitPat("b011100???????????101?????1010111") - def VMFNE_VV = BitPat("b011100???????????001?????1010111") - def VMIN_VV = BitPat("b000101???????????000?????1010111") - def VMIN_VX = BitPat("b000101???????????100?????1010111") - def VMINU_VV = BitPat("b000100???????????000?????1010111") - def VMINU_VX = BitPat("b000100???????????100?????1010111") - def VMNAND_MM = BitPat("b011101???????????010?????1010111") - def VMNOR_MM = BitPat("b011110???????????010?????1010111") - def VMOR_MM = BitPat("b011010???????????010?????1010111") - def VMORN_MM = BitPat("b011100???????????010?????1010111") - def VMSBC_VV = BitPat("b0100111??????????000?????1010111") - def VMSBC_VVM = BitPat("b0100110??????????000?????1010111") - def VMSBC_VX = BitPat("b0100111??????????100?????1010111") - def VMSBC_VXM = BitPat("b0100110??????????100?????1010111") - def VMSBF_M = BitPat("b010100??????00001010?????1010111") - def VMSEQ_VI = BitPat("b011000???????????011?????1010111") - def VMSEQ_VV = BitPat("b011000???????????000?????1010111") - def VMSEQ_VX = BitPat("b011000???????????100?????1010111") - def VMSGT_VI = BitPat("b011111???????????011?????1010111") - def VMSGT_VX = BitPat("b011111???????????100?????1010111") - def VMSGTU_VI = BitPat("b011110???????????011?????1010111") - def VMSGTU_VX = BitPat("b011110???????????100?????1010111") - def VMSIF_M = BitPat("b010100??????00011010?????1010111") - def VMSLE_VI = BitPat("b011101???????????011?????1010111") - def VMSLE_VV = BitPat("b011101???????????000?????1010111") - def VMSLE_VX = BitPat("b011101???????????100?????1010111") - def VMSLEU_VI = BitPat("b011100???????????011?????1010111") - def VMSLEU_VV = BitPat("b011100???????????000?????1010111") - def VMSLEU_VX = BitPat("b011100???????????100?????1010111") - def VMSLT_VV = BitPat("b011011???????????000?????1010111") - def VMSLT_VX = BitPat("b011011???????????100?????1010111") - def VMSLTU_VV = BitPat("b011010???????????000?????1010111") - def VMSLTU_VX = BitPat("b011010???????????100?????1010111") - def VMSNE_VI = BitPat("b011001???????????011?????1010111") - def VMSNE_VV = BitPat("b011001???????????000?????1010111") - def VMSNE_VX = BitPat("b011001???????????100?????1010111") - def VMSOF_M = BitPat("b010100??????00010010?????1010111") - def VMUL_VV = BitPat("b100101???????????010?????1010111") - def VMUL_VX = BitPat("b100101???????????110?????1010111") - def VMULH_VV = BitPat("b100111???????????010?????1010111") - def VMULH_VX = BitPat("b100111???????????110?????1010111") - def VMULHSU_VV = BitPat("b100110???????????010?????1010111") - def VMULHSU_VX = BitPat("b100110???????????110?????1010111") - def VMULHU_VV = BitPat("b100100???????????010?????1010111") - def VMULHU_VX = BitPat("b100100???????????110?????1010111") - def VMV1R_V = BitPat("b1001111?????00000011?????1010111") - def VMV2R_V = BitPat("b1001111?????00001011?????1010111") - def VMV4R_V = BitPat("b1001111?????00011011?????1010111") - def VMV8R_V = BitPat("b1001111?????00111011?????1010111") - def VMV_S_X = BitPat("b010000100000?????110?????1010111") - def VMV_V_I = BitPat("b010111100000?????011?????1010111") - def VMV_V_V = BitPat("b010111100000?????000?????1010111") - def VMV_V_X = BitPat("b010111100000?????100?????1010111") - def VMV_X_S = BitPat("b0100001?????00000010?????1010111") - def VMXNOR_MM = BitPat("b011111???????????010?????1010111") - def VMXOR_MM = BitPat("b011011???????????010?????1010111") - def VNCLIP_WI = BitPat("b101111???????????011?????1010111") - def VNCLIP_WV = BitPat("b101111???????????000?????1010111") - def VNCLIP_WX = BitPat("b101111???????????100?????1010111") - def VNCLIPU_WI = BitPat("b101110???????????011?????1010111") - def VNCLIPU_WV = BitPat("b101110???????????000?????1010111") - def VNCLIPU_WX = BitPat("b101110???????????100?????1010111") - def VNMSAC_VV = BitPat("b101111???????????010?????1010111") - def VNMSAC_VX = BitPat("b101111???????????110?????1010111") - def VNMSUB_VV = BitPat("b101011???????????010?????1010111") - def VNMSUB_VX = BitPat("b101011???????????110?????1010111") - def VNSRA_WI = BitPat("b101101???????????011?????1010111") - def VNSRA_WV = BitPat("b101101???????????000?????1010111") - def VNSRA_WX = BitPat("b101101???????????100?????1010111") - def VNSRL_WI = BitPat("b101100???????????011?????1010111") - def VNSRL_WV = BitPat("b101100???????????000?????1010111") - def VNSRL_WX = BitPat("b101100???????????100?????1010111") - def VOR_VI = BitPat("b001010???????????011?????1010111") - def VOR_VV = BitPat("b001010???????????000?????1010111") - def VOR_VX = BitPat("b001010???????????100?????1010111") - def VREDAND_VS = BitPat("b000001???????????010?????1010111") - def VREDMAX_VS = BitPat("b000111???????????010?????1010111") - def VREDMAXU_VS = BitPat("b000110???????????010?????1010111") - def VREDMIN_VS = BitPat("b000101???????????010?????1010111") - def VREDMINU_VS = BitPat("b000100???????????010?????1010111") - def VREDOR_VS = BitPat("b000010???????????010?????1010111") - def VREDSUM_VS = BitPat("b000000???????????010?????1010111") - def VREDXOR_VS = BitPat("b000011???????????010?????1010111") - def VREM_VV = BitPat("b100011???????????010?????1010111") - def VREM_VX = BitPat("b100011???????????110?????1010111") - def VREMU_VV = BitPat("b100010???????????010?????1010111") - def VREMU_VX = BitPat("b100010???????????110?????1010111") - def VRGATHER_VI = BitPat("b001100???????????011?????1010111") - def VRGATHER_VV = BitPat("b001100???????????000?????1010111") - def VRGATHER_VX = BitPat("b001100???????????100?????1010111") - def VRGATHEREI16_VV = BitPat("b001110???????????000?????1010111") - def VRSUB_VI = BitPat("b000011???????????011?????1010111") - def VRSUB_VX = BitPat("b000011???????????100?????1010111") - def VS1R_V = BitPat("b000000101000?????000?????0100111") - def VS2R_V = BitPat("b001000101000?????000?????0100111") - def VS4R_V = BitPat("b011000101000?????000?????0100111") - def VS8R_V = BitPat("b111000101000?????000?????0100111") - def VSADD_VI = BitPat("b100001???????????011?????1010111") - def VSADD_VV = BitPat("b100001???????????000?????1010111") - def VSADD_VX = BitPat("b100001???????????100?????1010111") - def VSADDU_VI = BitPat("b100000???????????011?????1010111") - def VSADDU_VV = BitPat("b100000???????????000?????1010111") - def VSADDU_VX = BitPat("b100000???????????100?????1010111") - def VSBC_VVM = BitPat("b0100100??????????000?????1010111") - def VSBC_VXM = BitPat("b0100100??????????100?????1010111") - def VSE1024_V = BitPat("b???100?00000?????111?????0100111") - def VSE128_V = BitPat("b???100?00000?????000?????0100111") - def VSE16_V = BitPat("b???000?00000?????101?????0100111") - def VSE256_V = BitPat("b???100?00000?????101?????0100111") - def VSE32_V = BitPat("b???000?00000?????110?????0100111") - def VSE512_V = BitPat("b???100?00000?????110?????0100111") - def VSE64_V = BitPat("b???000?00000?????111?????0100111") - def VSE8_V = BitPat("b???000?00000?????000?????0100111") - def VSETIVLI = BitPat("b11???????????????111?????1010111") - def VSETVL = BitPat("b1000000??????????111?????1010111") - def VSETVLI = BitPat("b0????????????????111?????1010111") - def VSEXT_VF2 = BitPat("b010010??????00111010?????1010111") - def VSEXT_VF4 = BitPat("b010010??????00101010?????1010111") - def VSEXT_VF8 = BitPat("b010010??????00011010?????1010111") - def VSLIDE1DOWN_VX = BitPat("b001111???????????110?????1010111") - def VSLIDE1UP_VX = BitPat("b001110???????????110?????1010111") - def VSLIDEDOWN_VI = BitPat("b001111???????????011?????1010111") - def VSLIDEDOWN_VX = BitPat("b001111???????????100?????1010111") - def VSLIDEUP_VI = BitPat("b001110???????????011?????1010111") - def VSLIDEUP_VX = BitPat("b001110???????????100?????1010111") - def VSLL_VI = BitPat("b100101???????????011?????1010111") - def VSLL_VV = BitPat("b100101???????????000?????1010111") - def VSLL_VX = BitPat("b100101???????????100?????1010111") - def VSM_V = BitPat("b000000101011?????000?????0100111") - def VSMUL_VV = BitPat("b100111???????????000?????1010111") - def VSMUL_VX = BitPat("b100111???????????100?????1010111") - def VSOXEI1024_V = BitPat("b???111???????????111?????0100111") - def VSOXEI128_V = BitPat("b???111???????????000?????0100111") - def VSOXEI16_V = BitPat("b???011???????????101?????0100111") - def VSOXEI256_V = BitPat("b???111???????????101?????0100111") - def VSOXEI32_V = BitPat("b???011???????????110?????0100111") - def VSOXEI512_V = BitPat("b???111???????????110?????0100111") - def VSOXEI64_V = BitPat("b???011???????????111?????0100111") - def VSOXEI8_V = BitPat("b???011???????????000?????0100111") - def VSRA_VI = BitPat("b101001???????????011?????1010111") - def VSRA_VV = BitPat("b101001???????????000?????1010111") - def VSRA_VX = BitPat("b101001???????????100?????1010111") - def VSRL_VI = BitPat("b101000???????????011?????1010111") - def VSRL_VV = BitPat("b101000???????????000?????1010111") - def VSRL_VX = BitPat("b101000???????????100?????1010111") - def VSSE1024_V = BitPat("b???110???????????111?????0100111") - def VSSE128_V = BitPat("b???110???????????000?????0100111") - def VSSE16_V = BitPat("b???010???????????101?????0100111") - def VSSE256_V = BitPat("b???110???????????101?????0100111") - def VSSE32_V = BitPat("b???010???????????110?????0100111") - def VSSE512_V = BitPat("b???110???????????110?????0100111") - def VSSE64_V = BitPat("b???010???????????111?????0100111") - def VSSE8_V = BitPat("b???010???????????000?????0100111") - def VSSRA_VI = BitPat("b101011???????????011?????1010111") - def VSSRA_VV = BitPat("b101011???????????000?????1010111") - def VSSRA_VX = BitPat("b101011???????????100?????1010111") - def VSSRL_VI = BitPat("b101010???????????011?????1010111") - def VSSRL_VV = BitPat("b101010???????????000?????1010111") - def VSSRL_VX = BitPat("b101010???????????100?????1010111") - def VSSUB_VV = BitPat("b100011???????????000?????1010111") - def VSSUB_VX = BitPat("b100011???????????100?????1010111") - def VSSUBU_VV = BitPat("b100010???????????000?????1010111") - def VSSUBU_VX = BitPat("b100010???????????100?????1010111") - def VSUB_VV = BitPat("b000010???????????000?????1010111") - def VSUB_VX = BitPat("b000010???????????100?????1010111") - def VSUXEI1024_V = BitPat("b???101???????????111?????0100111") - def VSUXEI128_V = BitPat("b???101???????????000?????0100111") - def VSUXEI16_V = BitPat("b???001???????????101?????0100111") - def VSUXEI256_V = BitPat("b???101???????????101?????0100111") - def VSUXEI32_V = BitPat("b???001???????????110?????0100111") - def VSUXEI512_V = BitPat("b???101???????????110?????0100111") - def VSUXEI64_V = BitPat("b???001???????????111?????0100111") - def VSUXEI8_V = BitPat("b???001???????????000?????0100111") - def VWADD_VV = BitPat("b110001???????????010?????1010111") - def VWADD_VX = BitPat("b110001???????????110?????1010111") - def VWADD_WV = BitPat("b110101???????????010?????1010111") - def VWADD_WX = BitPat("b110101???????????110?????1010111") - def VWADDU_VV = BitPat("b110000???????????010?????1010111") - def VWADDU_VX = BitPat("b110000???????????110?????1010111") - def VWADDU_WV = BitPat("b110100???????????010?????1010111") - def VWADDU_WX = BitPat("b110100???????????110?????1010111") - def VWMACC_VV = BitPat("b111101???????????010?????1010111") - def VWMACC_VX = BitPat("b111101???????????110?????1010111") - def VWMACCSU_VV = BitPat("b111111???????????010?????1010111") - def VWMACCSU_VX = BitPat("b111111???????????110?????1010111") - def VWMACCU_VV = BitPat("b111100???????????010?????1010111") - def VWMACCU_VX = BitPat("b111100???????????110?????1010111") - def VWMACCUS_VX = BitPat("b111110???????????110?????1010111") - def VWMUL_VV = BitPat("b111011???????????010?????1010111") - def VWMUL_VX = BitPat("b111011???????????110?????1010111") - def VWMULSU_VV = BitPat("b111010???????????010?????1010111") - def VWMULSU_VX = BitPat("b111010???????????110?????1010111") - def VWMULU_VV = BitPat("b111000???????????010?????1010111") - def VWMULU_VX = BitPat("b111000???????????110?????1010111") - def VWREDSUM_VS = BitPat("b110001???????????000?????1010111") - def VWREDSUMU_VS = BitPat("b110000???????????000?????1010111") - def VWSUB_VV = BitPat("b110011???????????010?????1010111") - def VWSUB_VX = BitPat("b110011???????????110?????1010111") - def VWSUB_WV = BitPat("b110111???????????010?????1010111") - def VWSUB_WX = BitPat("b110111???????????110?????1010111") - def VWSUBU_VV = BitPat("b110010???????????010?????1010111") - def VWSUBU_VX = BitPat("b110010???????????110?????1010111") - def VWSUBU_WV = BitPat("b110110???????????010?????1010111") - def VWSUBU_WX = BitPat("b110110???????????110?????1010111") - def VXOR_VI = BitPat("b001011???????????011?????1010111") - def VXOR_VV = BitPat("b001011???????????000?????1010111") - def VXOR_VX = BitPat("b001011???????????100?????1010111") - def VZEXT_VF2 = BitPat("b010010??????00110010?????1010111") - def VZEXT_VF4 = BitPat("b010010??????00100010?????1010111") - def VZEXT_VF8 = BitPat("b010010??????00010010?????1010111") - def WFI = BitPat("b00010000010100000000000001110011") - def XNOR = BitPat("b0100000??????????100?????0110011") - def XOR = BitPat("b0000000??????????100?????0110011") - def XORI = BitPat("b?????????????????100?????0010011") - def XPERM4 = BitPat("b0010100??????????010?????0110011") - def XPERM8 = BitPat("b0010100??????????100?????0110011") - def ZEXT_H = BitPat("b000010000000?????100?????0111011") - -} object Causes { - val misaligned_fetch = 0x0 - val fetch_access = 0x1 - val illegal_instruction = 0x2 - val breakpoint = 0x3 - val misaligned_load = 0x4 - val load_access = 0x5 - val misaligned_store = 0x6 - val store_access = 0x7 - val user_ecall = 0x8 - val supervisor_ecall = 0x9 + val misaligned_fetch = 0x0 + val fetch_access = 0x1 + val illegal_instruction = 0x2 + val breakpoint = 0x3 + val misaligned_load = 0x4 + val load_access = 0x5 + val misaligned_store = 0x6 + val store_access = 0x7 + val user_ecall = 0x8 + val supervisor_ecall = 0x9 val virtual_supervisor_ecall = 0xa - val machine_ecall = 0xb - val fetch_page_fault = 0xc - val load_page_fault = 0xd - val store_page_fault = 0xf - val fetch_guest_page_fault = 0x14 - val load_guest_page_fault = 0x15 - val virtual_instruction = 0x16 - val store_guest_page_fault = 0x17 + val machine_ecall = 0xb + val fetch_page_fault = 0xc + val load_page_fault = 0xd + val store_page_fault = 0xf + val fetch_guest_page_fault = 0x14 + val load_guest_page_fault = 0x15 + val virtual_instruction = 0x16 + val store_guest_page_fault = 0x17 val all = { val res = collection.mutable.ArrayBuffer[Int]() res += misaligned_fetch @@ -858,413 +48,413 @@ object Causes { } } object CSRs { - val fflags = 0x1 - val frm = 0x2 - val fcsr = 0x3 - val vstart = 0x8 - val vxsat = 0x9 - val vxrm = 0xa - val vcsr = 0xf - val seed = 0x15 - val jvt = 0x17 - val cycle = 0xc00 - val time = 0xc01 - val instret = 0xc02 - val hpmcounter3 = 0xc03 - val hpmcounter4 = 0xc04 - val hpmcounter5 = 0xc05 - val hpmcounter6 = 0xc06 - val hpmcounter7 = 0xc07 - val hpmcounter8 = 0xc08 - val hpmcounter9 = 0xc09 - val hpmcounter10 = 0xc0a - val hpmcounter11 = 0xc0b - val hpmcounter12 = 0xc0c - val hpmcounter13 = 0xc0d - val hpmcounter14 = 0xc0e - val hpmcounter15 = 0xc0f - val hpmcounter16 = 0xc10 - val hpmcounter17 = 0xc11 - val hpmcounter18 = 0xc12 - val hpmcounter19 = 0xc13 - val hpmcounter20 = 0xc14 - val hpmcounter21 = 0xc15 - val hpmcounter22 = 0xc16 - val hpmcounter23 = 0xc17 - val hpmcounter24 = 0xc18 - val hpmcounter25 = 0xc19 - val hpmcounter26 = 0xc1a - val hpmcounter27 = 0xc1b - val hpmcounter28 = 0xc1c - val hpmcounter29 = 0xc1d - val hpmcounter30 = 0xc1e - val hpmcounter31 = 0xc1f - val vl = 0xc20 - val vtype = 0xc21 - val vlenb = 0xc22 - val sstatus = 0x100 - val sedeleg = 0x102 - val sideleg = 0x103 - val sie = 0x104 - val stvec = 0x105 - val scounteren = 0x106 - val senvcfg = 0x10a - val sstateen0 = 0x10c - val sstateen1 = 0x10d - val sstateen2 = 0x10e - val sstateen3 = 0x10f - val sscratch = 0x140 - val sepc = 0x141 - val scause = 0x142 - val stval = 0x143 - val sip = 0x144 - val stimecmp = 0x14d - val siselect = 0x150 - val sireg = 0x151 - val stopei = 0x15c - val satp = 0x180 - val scontext = 0x5a8 - val vsstatus = 0x200 - val vsie = 0x204 - val vstvec = 0x205 - val vsscratch = 0x240 - val vsepc = 0x241 - val vscause = 0x242 - val vstval = 0x243 - val vsip = 0x244 - val vstimecmp = 0x24d - val vsiselect = 0x250 - val vsireg = 0x251 - val vstopei = 0x25c - val vsatp = 0x280 - val hstatus = 0x600 - val hedeleg = 0x602 - val hideleg = 0x603 - val hie = 0x604 - val htimedelta = 0x605 - val hcounteren = 0x606 - val hgeie = 0x607 - val hvien = 0x608 - val hvictl = 0x609 - val henvcfg = 0x60a - val hstateen0 = 0x60c - val hstateen1 = 0x60d - val hstateen2 = 0x60e - val hstateen3 = 0x60f - val htval = 0x643 - val hip = 0x644 - val hvip = 0x645 - val hviprio1 = 0x646 - val hviprio2 = 0x647 - val htinst = 0x64a - val hgatp = 0x680 - val hcontext = 0x6a8 - val hgeip = 0xe12 - val vstopi = 0xeb0 - val scountovf = 0xda0 - val stopi = 0xdb0 - val utvt = 0x7 - val unxti = 0x45 - val uintstatus = 0x46 - val uscratchcsw = 0x48 - val uscratchcswl = 0x49 - val stvt = 0x107 - val snxti = 0x145 - val sintstatus = 0x146 - val sscratchcsw = 0x148 - val sscratchcswl = 0x149 - val mtvt = 0x307 - val mnxti = 0x345 - val mintstatus = 0x346 - val mscratchcsw = 0x348 - val mscratchcswl = 0x349 - val mstatus = 0x300 - val misa = 0x301 - val medeleg = 0x302 - val mideleg = 0x303 - val mie = 0x304 - val mtvec = 0x305 - val mcounteren = 0x306 - val mvien = 0x308 - val mvip = 0x309 - val menvcfg = 0x30a - val mstateen0 = 0x30c - val mstateen1 = 0x30d - val mstateen2 = 0x30e - val mstateen3 = 0x30f - val mcountinhibit = 0x320 - val mscratch = 0x340 - val mepc = 0x341 - val mcause = 0x342 - val mtval = 0x343 - val mip = 0x344 - val mtinst = 0x34a - val mtval2 = 0x34b - val miselect = 0x350 - val mireg = 0x351 - val mtopei = 0x35c - val pmpcfg0 = 0x3a0 - val pmpcfg1 = 0x3a1 - val pmpcfg2 = 0x3a2 - val pmpcfg3 = 0x3a3 - val pmpcfg4 = 0x3a4 - val pmpcfg5 = 0x3a5 - val pmpcfg6 = 0x3a6 - val pmpcfg7 = 0x3a7 - val pmpcfg8 = 0x3a8 - val pmpcfg9 = 0x3a9 - val pmpcfg10 = 0x3aa - val pmpcfg11 = 0x3ab - val pmpcfg12 = 0x3ac - val pmpcfg13 = 0x3ad - val pmpcfg14 = 0x3ae - val pmpcfg15 = 0x3af - val pmpaddr0 = 0x3b0 - val pmpaddr1 = 0x3b1 - val pmpaddr2 = 0x3b2 - val pmpaddr3 = 0x3b3 - val pmpaddr4 = 0x3b4 - val pmpaddr5 = 0x3b5 - val pmpaddr6 = 0x3b6 - val pmpaddr7 = 0x3b7 - val pmpaddr8 = 0x3b8 - val pmpaddr9 = 0x3b9 - val pmpaddr10 = 0x3ba - val pmpaddr11 = 0x3bb - val pmpaddr12 = 0x3bc - val pmpaddr13 = 0x3bd - val pmpaddr14 = 0x3be - val pmpaddr15 = 0x3bf - val pmpaddr16 = 0x3c0 - val pmpaddr17 = 0x3c1 - val pmpaddr18 = 0x3c2 - val pmpaddr19 = 0x3c3 - val pmpaddr20 = 0x3c4 - val pmpaddr21 = 0x3c5 - val pmpaddr22 = 0x3c6 - val pmpaddr23 = 0x3c7 - val pmpaddr24 = 0x3c8 - val pmpaddr25 = 0x3c9 - val pmpaddr26 = 0x3ca - val pmpaddr27 = 0x3cb - val pmpaddr28 = 0x3cc - val pmpaddr29 = 0x3cd - val pmpaddr30 = 0x3ce - val pmpaddr31 = 0x3cf - val pmpaddr32 = 0x3d0 - val pmpaddr33 = 0x3d1 - val pmpaddr34 = 0x3d2 - val pmpaddr35 = 0x3d3 - val pmpaddr36 = 0x3d4 - val pmpaddr37 = 0x3d5 - val pmpaddr38 = 0x3d6 - val pmpaddr39 = 0x3d7 - val pmpaddr40 = 0x3d8 - val pmpaddr41 = 0x3d9 - val pmpaddr42 = 0x3da - val pmpaddr43 = 0x3db - val pmpaddr44 = 0x3dc - val pmpaddr45 = 0x3dd - val pmpaddr46 = 0x3de - val pmpaddr47 = 0x3df - val pmpaddr48 = 0x3e0 - val pmpaddr49 = 0x3e1 - val pmpaddr50 = 0x3e2 - val pmpaddr51 = 0x3e3 - val pmpaddr52 = 0x3e4 - val pmpaddr53 = 0x3e5 - val pmpaddr54 = 0x3e6 - val pmpaddr55 = 0x3e7 - val pmpaddr56 = 0x3e8 - val pmpaddr57 = 0x3e9 - val pmpaddr58 = 0x3ea - val pmpaddr59 = 0x3eb - val pmpaddr60 = 0x3ec - val pmpaddr61 = 0x3ed - val pmpaddr62 = 0x3ee - val pmpaddr63 = 0x3ef - val mseccfg = 0x747 - val tselect = 0x7a0 - val tdata1 = 0x7a1 - val tdata2 = 0x7a2 - val tdata3 = 0x7a3 - val tinfo = 0x7a4 - val tcontrol = 0x7a5 - val mcontext = 0x7a8 - val mscontext = 0x7aa - val dcsr = 0x7b0 - val dpc = 0x7b1 - val dscratch0 = 0x7b2 - val dscratch1 = 0x7b3 - val mcycle = 0xb00 - val minstret = 0xb02 - val mhpmcounter3 = 0xb03 - val mhpmcounter4 = 0xb04 - val mhpmcounter5 = 0xb05 - val mhpmcounter6 = 0xb06 - val mhpmcounter7 = 0xb07 - val mhpmcounter8 = 0xb08 - val mhpmcounter9 = 0xb09 - val mhpmcounter10 = 0xb0a - val mhpmcounter11 = 0xb0b - val mhpmcounter12 = 0xb0c - val mhpmcounter13 = 0xb0d - val mhpmcounter14 = 0xb0e - val mhpmcounter15 = 0xb0f - val mhpmcounter16 = 0xb10 - val mhpmcounter17 = 0xb11 - val mhpmcounter18 = 0xb12 - val mhpmcounter19 = 0xb13 - val mhpmcounter20 = 0xb14 - val mhpmcounter21 = 0xb15 - val mhpmcounter22 = 0xb16 - val mhpmcounter23 = 0xb17 - val mhpmcounter24 = 0xb18 - val mhpmcounter25 = 0xb19 - val mhpmcounter26 = 0xb1a - val mhpmcounter27 = 0xb1b - val mhpmcounter28 = 0xb1c - val mhpmcounter29 = 0xb1d - val mhpmcounter30 = 0xb1e - val mhpmcounter31 = 0xb1f - val mhpmevent3 = 0x323 - val mhpmevent4 = 0x324 - val mhpmevent5 = 0x325 - val mhpmevent6 = 0x326 - val mhpmevent7 = 0x327 - val mhpmevent8 = 0x328 - val mhpmevent9 = 0x329 - val mhpmevent10 = 0x32a - val mhpmevent11 = 0x32b - val mhpmevent12 = 0x32c - val mhpmevent13 = 0x32d - val mhpmevent14 = 0x32e - val mhpmevent15 = 0x32f - val mhpmevent16 = 0x330 - val mhpmevent17 = 0x331 - val mhpmevent18 = 0x332 - val mhpmevent19 = 0x333 - val mhpmevent20 = 0x334 - val mhpmevent21 = 0x335 - val mhpmevent22 = 0x336 - val mhpmevent23 = 0x337 - val mhpmevent24 = 0x338 - val mhpmevent25 = 0x339 - val mhpmevent26 = 0x33a - val mhpmevent27 = 0x33b - val mhpmevent28 = 0x33c - val mhpmevent29 = 0x33d - val mhpmevent30 = 0x33e - val mhpmevent31 = 0x33f - val mvendorid = 0xf11 - val marchid = 0xf12 - val mimpid = 0xf13 - val mhartid = 0xf14 - val mconfigptr = 0xf15 - val mtopi = 0xfb0 - val sieh = 0x114 - val siph = 0x154 - val stimecmph = 0x15d - val vsieh = 0x214 - val vsiph = 0x254 - val vstimecmph = 0x25d - val htimedeltah = 0x615 - val hidelegh = 0x613 - val hvienh = 0x618 - val henvcfgh = 0x61a - val hviph = 0x655 - val hviprio1h = 0x656 - val hviprio2h = 0x657 - val hstateen0h = 0x61c - val hstateen1h = 0x61d - val hstateen2h = 0x61e - val hstateen3h = 0x61f - val cycleh = 0xc80 - val timeh = 0xc81 - val instreth = 0xc82 - val hpmcounter3h = 0xc83 - val hpmcounter4h = 0xc84 - val hpmcounter5h = 0xc85 - val hpmcounter6h = 0xc86 - val hpmcounter7h = 0xc87 - val hpmcounter8h = 0xc88 - val hpmcounter9h = 0xc89 - val hpmcounter10h = 0xc8a - val hpmcounter11h = 0xc8b - val hpmcounter12h = 0xc8c - val hpmcounter13h = 0xc8d - val hpmcounter14h = 0xc8e - val hpmcounter15h = 0xc8f - val hpmcounter16h = 0xc90 - val hpmcounter17h = 0xc91 - val hpmcounter18h = 0xc92 - val hpmcounter19h = 0xc93 - val hpmcounter20h = 0xc94 - val hpmcounter21h = 0xc95 - val hpmcounter22h = 0xc96 - val hpmcounter23h = 0xc97 - val hpmcounter24h = 0xc98 - val hpmcounter25h = 0xc99 - val hpmcounter26h = 0xc9a - val hpmcounter27h = 0xc9b - val hpmcounter28h = 0xc9c - val hpmcounter29h = 0xc9d - val hpmcounter30h = 0xc9e - val hpmcounter31h = 0xc9f - val mstatush = 0x310 - val midelegh = 0x313 - val mieh = 0x314 - val mvienh = 0x318 - val mviph = 0x319 - val menvcfgh = 0x31a - val mstateen0h = 0x31c - val mstateen1h = 0x31d - val mstateen2h = 0x31e - val mstateen3h = 0x31f - val miph = 0x354 - val mhpmevent3h = 0x723 - val mhpmevent4h = 0x724 - val mhpmevent5h = 0x725 - val mhpmevent6h = 0x726 - val mhpmevent7h = 0x727 - val mhpmevent8h = 0x728 - val mhpmevent9h = 0x729 - val mhpmevent10h = 0x72a - val mhpmevent11h = 0x72b - val mhpmevent12h = 0x72c - val mhpmevent13h = 0x72d - val mhpmevent14h = 0x72e - val mhpmevent15h = 0x72f - val mhpmevent16h = 0x730 - val mhpmevent17h = 0x731 - val mhpmevent18h = 0x732 - val mhpmevent19h = 0x733 - val mhpmevent20h = 0x734 - val mhpmevent21h = 0x735 - val mhpmevent22h = 0x736 - val mhpmevent23h = 0x737 - val mhpmevent24h = 0x738 - val mhpmevent25h = 0x739 - val mhpmevent26h = 0x73a - val mhpmevent27h = 0x73b - val mhpmevent28h = 0x73c - val mhpmevent29h = 0x73d - val mhpmevent30h = 0x73e - val mhpmevent31h = 0x73f - val mnscratch = 0x740 - val mnepc = 0x741 - val mncause = 0x742 - val mnstatus = 0x744 - val mseccfgh = 0x757 - val mcycleh = 0xb80 - val minstreth = 0xb82 - val mhpmcounter3h = 0xb83 - val mhpmcounter4h = 0xb84 - val mhpmcounter5h = 0xb85 - val mhpmcounter6h = 0xb86 - val mhpmcounter7h = 0xb87 - val mhpmcounter8h = 0xb88 - val mhpmcounter9h = 0xb89 + val fflags = 0x1 + val frm = 0x2 + val fcsr = 0x3 + val vstart = 0x8 + val vxsat = 0x9 + val vxrm = 0xa + val vcsr = 0xf + val seed = 0x15 + val jvt = 0x17 + val cycle = 0xc00 + val time = 0xc01 + val instret = 0xc02 + val hpmcounter3 = 0xc03 + val hpmcounter4 = 0xc04 + val hpmcounter5 = 0xc05 + val hpmcounter6 = 0xc06 + val hpmcounter7 = 0xc07 + val hpmcounter8 = 0xc08 + val hpmcounter9 = 0xc09 + val hpmcounter10 = 0xc0a + val hpmcounter11 = 0xc0b + val hpmcounter12 = 0xc0c + val hpmcounter13 = 0xc0d + val hpmcounter14 = 0xc0e + val hpmcounter15 = 0xc0f + val hpmcounter16 = 0xc10 + val hpmcounter17 = 0xc11 + val hpmcounter18 = 0xc12 + val hpmcounter19 = 0xc13 + val hpmcounter20 = 0xc14 + val hpmcounter21 = 0xc15 + val hpmcounter22 = 0xc16 + val hpmcounter23 = 0xc17 + val hpmcounter24 = 0xc18 + val hpmcounter25 = 0xc19 + val hpmcounter26 = 0xc1a + val hpmcounter27 = 0xc1b + val hpmcounter28 = 0xc1c + val hpmcounter29 = 0xc1d + val hpmcounter30 = 0xc1e + val hpmcounter31 = 0xc1f + val vl = 0xc20 + val vtype = 0xc21 + val vlenb = 0xc22 + val sstatus = 0x100 + val sedeleg = 0x102 + val sideleg = 0x103 + val sie = 0x104 + val stvec = 0x105 + val scounteren = 0x106 + val senvcfg = 0x10a + val sstateen0 = 0x10c + val sstateen1 = 0x10d + val sstateen2 = 0x10e + val sstateen3 = 0x10f + val sscratch = 0x140 + val sepc = 0x141 + val scause = 0x142 + val stval = 0x143 + val sip = 0x144 + val stimecmp = 0x14d + val siselect = 0x150 + val sireg = 0x151 + val stopei = 0x15c + val satp = 0x180 + val scontext = 0x5a8 + val vsstatus = 0x200 + val vsie = 0x204 + val vstvec = 0x205 + val vsscratch = 0x240 + val vsepc = 0x241 + val vscause = 0x242 + val vstval = 0x243 + val vsip = 0x244 + val vstimecmp = 0x24d + val vsiselect = 0x250 + val vsireg = 0x251 + val vstopei = 0x25c + val vsatp = 0x280 + val hstatus = 0x600 + val hedeleg = 0x602 + val hideleg = 0x603 + val hie = 0x604 + val htimedelta = 0x605 + val hcounteren = 0x606 + val hgeie = 0x607 + val hvien = 0x608 + val hvictl = 0x609 + val henvcfg = 0x60a + val hstateen0 = 0x60c + val hstateen1 = 0x60d + val hstateen2 = 0x60e + val hstateen3 = 0x60f + val htval = 0x643 + val hip = 0x644 + val hvip = 0x645 + val hviprio1 = 0x646 + val hviprio2 = 0x647 + val htinst = 0x64a + val hgatp = 0x680 + val hcontext = 0x6a8 + val hgeip = 0xe12 + val vstopi = 0xeb0 + val scountovf = 0xda0 + val stopi = 0xdb0 + val utvt = 0x7 + val unxti = 0x45 + val uintstatus = 0x46 + val uscratchcsw = 0x48 + val uscratchcswl = 0x49 + val stvt = 0x107 + val snxti = 0x145 + val sintstatus = 0x146 + val sscratchcsw = 0x148 + val sscratchcswl = 0x149 + val mtvt = 0x307 + val mnxti = 0x345 + val mintstatus = 0x346 + val mscratchcsw = 0x348 + val mscratchcswl = 0x349 + val mstatus = 0x300 + val misa = 0x301 + val medeleg = 0x302 + val mideleg = 0x303 + val mie = 0x304 + val mtvec = 0x305 + val mcounteren = 0x306 + val mvien = 0x308 + val mvip = 0x309 + val menvcfg = 0x30a + val mstateen0 = 0x30c + val mstateen1 = 0x30d + val mstateen2 = 0x30e + val mstateen3 = 0x30f + val mcountinhibit = 0x320 + val mscratch = 0x340 + val mepc = 0x341 + val mcause = 0x342 + val mtval = 0x343 + val mip = 0x344 + val mtinst = 0x34a + val mtval2 = 0x34b + val miselect = 0x350 + val mireg = 0x351 + val mtopei = 0x35c + val pmpcfg0 = 0x3a0 + val pmpcfg1 = 0x3a1 + val pmpcfg2 = 0x3a2 + val pmpcfg3 = 0x3a3 + val pmpcfg4 = 0x3a4 + val pmpcfg5 = 0x3a5 + val pmpcfg6 = 0x3a6 + val pmpcfg7 = 0x3a7 + val pmpcfg8 = 0x3a8 + val pmpcfg9 = 0x3a9 + val pmpcfg10 = 0x3aa + val pmpcfg11 = 0x3ab + val pmpcfg12 = 0x3ac + val pmpcfg13 = 0x3ad + val pmpcfg14 = 0x3ae + val pmpcfg15 = 0x3af + val pmpaddr0 = 0x3b0 + val pmpaddr1 = 0x3b1 + val pmpaddr2 = 0x3b2 + val pmpaddr3 = 0x3b3 + val pmpaddr4 = 0x3b4 + val pmpaddr5 = 0x3b5 + val pmpaddr6 = 0x3b6 + val pmpaddr7 = 0x3b7 + val pmpaddr8 = 0x3b8 + val pmpaddr9 = 0x3b9 + val pmpaddr10 = 0x3ba + val pmpaddr11 = 0x3bb + val pmpaddr12 = 0x3bc + val pmpaddr13 = 0x3bd + val pmpaddr14 = 0x3be + val pmpaddr15 = 0x3bf + val pmpaddr16 = 0x3c0 + val pmpaddr17 = 0x3c1 + val pmpaddr18 = 0x3c2 + val pmpaddr19 = 0x3c3 + val pmpaddr20 = 0x3c4 + val pmpaddr21 = 0x3c5 + val pmpaddr22 = 0x3c6 + val pmpaddr23 = 0x3c7 + val pmpaddr24 = 0x3c8 + val pmpaddr25 = 0x3c9 + val pmpaddr26 = 0x3ca + val pmpaddr27 = 0x3cb + val pmpaddr28 = 0x3cc + val pmpaddr29 = 0x3cd + val pmpaddr30 = 0x3ce + val pmpaddr31 = 0x3cf + val pmpaddr32 = 0x3d0 + val pmpaddr33 = 0x3d1 + val pmpaddr34 = 0x3d2 + val pmpaddr35 = 0x3d3 + val pmpaddr36 = 0x3d4 + val pmpaddr37 = 0x3d5 + val pmpaddr38 = 0x3d6 + val pmpaddr39 = 0x3d7 + val pmpaddr40 = 0x3d8 + val pmpaddr41 = 0x3d9 + val pmpaddr42 = 0x3da + val pmpaddr43 = 0x3db + val pmpaddr44 = 0x3dc + val pmpaddr45 = 0x3dd + val pmpaddr46 = 0x3de + val pmpaddr47 = 0x3df + val pmpaddr48 = 0x3e0 + val pmpaddr49 = 0x3e1 + val pmpaddr50 = 0x3e2 + val pmpaddr51 = 0x3e3 + val pmpaddr52 = 0x3e4 + val pmpaddr53 = 0x3e5 + val pmpaddr54 = 0x3e6 + val pmpaddr55 = 0x3e7 + val pmpaddr56 = 0x3e8 + val pmpaddr57 = 0x3e9 + val pmpaddr58 = 0x3ea + val pmpaddr59 = 0x3eb + val pmpaddr60 = 0x3ec + val pmpaddr61 = 0x3ed + val pmpaddr62 = 0x3ee + val pmpaddr63 = 0x3ef + val mseccfg = 0x747 + val tselect = 0x7a0 + val tdata1 = 0x7a1 + val tdata2 = 0x7a2 + val tdata3 = 0x7a3 + val tinfo = 0x7a4 + val tcontrol = 0x7a5 + val mcontext = 0x7a8 + val mscontext = 0x7aa + val dcsr = 0x7b0 + val dpc = 0x7b1 + val dscratch0 = 0x7b2 + val dscratch1 = 0x7b3 + val mcycle = 0xb00 + val minstret = 0xb02 + val mhpmcounter3 = 0xb03 + val mhpmcounter4 = 0xb04 + val mhpmcounter5 = 0xb05 + val mhpmcounter6 = 0xb06 + val mhpmcounter7 = 0xb07 + val mhpmcounter8 = 0xb08 + val mhpmcounter9 = 0xb09 + val mhpmcounter10 = 0xb0a + val mhpmcounter11 = 0xb0b + val mhpmcounter12 = 0xb0c + val mhpmcounter13 = 0xb0d + val mhpmcounter14 = 0xb0e + val mhpmcounter15 = 0xb0f + val mhpmcounter16 = 0xb10 + val mhpmcounter17 = 0xb11 + val mhpmcounter18 = 0xb12 + val mhpmcounter19 = 0xb13 + val mhpmcounter20 = 0xb14 + val mhpmcounter21 = 0xb15 + val mhpmcounter22 = 0xb16 + val mhpmcounter23 = 0xb17 + val mhpmcounter24 = 0xb18 + val mhpmcounter25 = 0xb19 + val mhpmcounter26 = 0xb1a + val mhpmcounter27 = 0xb1b + val mhpmcounter28 = 0xb1c + val mhpmcounter29 = 0xb1d + val mhpmcounter30 = 0xb1e + val mhpmcounter31 = 0xb1f + val mhpmevent3 = 0x323 + val mhpmevent4 = 0x324 + val mhpmevent5 = 0x325 + val mhpmevent6 = 0x326 + val mhpmevent7 = 0x327 + val mhpmevent8 = 0x328 + val mhpmevent9 = 0x329 + val mhpmevent10 = 0x32a + val mhpmevent11 = 0x32b + val mhpmevent12 = 0x32c + val mhpmevent13 = 0x32d + val mhpmevent14 = 0x32e + val mhpmevent15 = 0x32f + val mhpmevent16 = 0x330 + val mhpmevent17 = 0x331 + val mhpmevent18 = 0x332 + val mhpmevent19 = 0x333 + val mhpmevent20 = 0x334 + val mhpmevent21 = 0x335 + val mhpmevent22 = 0x336 + val mhpmevent23 = 0x337 + val mhpmevent24 = 0x338 + val mhpmevent25 = 0x339 + val mhpmevent26 = 0x33a + val mhpmevent27 = 0x33b + val mhpmevent28 = 0x33c + val mhpmevent29 = 0x33d + val mhpmevent30 = 0x33e + val mhpmevent31 = 0x33f + val mvendorid = 0xf11 + val marchid = 0xf12 + val mimpid = 0xf13 + val mhartid = 0xf14 + val mconfigptr = 0xf15 + val mtopi = 0xfb0 + val sieh = 0x114 + val siph = 0x154 + val stimecmph = 0x15d + val vsieh = 0x214 + val vsiph = 0x254 + val vstimecmph = 0x25d + val htimedeltah = 0x615 + val hidelegh = 0x613 + val hvienh = 0x618 + val henvcfgh = 0x61a + val hviph = 0x655 + val hviprio1h = 0x656 + val hviprio2h = 0x657 + val hstateen0h = 0x61c + val hstateen1h = 0x61d + val hstateen2h = 0x61e + val hstateen3h = 0x61f + val cycleh = 0xc80 + val timeh = 0xc81 + val instreth = 0xc82 + val hpmcounter3h = 0xc83 + val hpmcounter4h = 0xc84 + val hpmcounter5h = 0xc85 + val hpmcounter6h = 0xc86 + val hpmcounter7h = 0xc87 + val hpmcounter8h = 0xc88 + val hpmcounter9h = 0xc89 + val hpmcounter10h = 0xc8a + val hpmcounter11h = 0xc8b + val hpmcounter12h = 0xc8c + val hpmcounter13h = 0xc8d + val hpmcounter14h = 0xc8e + val hpmcounter15h = 0xc8f + val hpmcounter16h = 0xc90 + val hpmcounter17h = 0xc91 + val hpmcounter18h = 0xc92 + val hpmcounter19h = 0xc93 + val hpmcounter20h = 0xc94 + val hpmcounter21h = 0xc95 + val hpmcounter22h = 0xc96 + val hpmcounter23h = 0xc97 + val hpmcounter24h = 0xc98 + val hpmcounter25h = 0xc99 + val hpmcounter26h = 0xc9a + val hpmcounter27h = 0xc9b + val hpmcounter28h = 0xc9c + val hpmcounter29h = 0xc9d + val hpmcounter30h = 0xc9e + val hpmcounter31h = 0xc9f + val mstatush = 0x310 + val midelegh = 0x313 + val mieh = 0x314 + val mvienh = 0x318 + val mviph = 0x319 + val menvcfgh = 0x31a + val mstateen0h = 0x31c + val mstateen1h = 0x31d + val mstateen2h = 0x31e + val mstateen3h = 0x31f + val miph = 0x354 + val mhpmevent3h = 0x723 + val mhpmevent4h = 0x724 + val mhpmevent5h = 0x725 + val mhpmevent6h = 0x726 + val mhpmevent7h = 0x727 + val mhpmevent8h = 0x728 + val mhpmevent9h = 0x729 + val mhpmevent10h = 0x72a + val mhpmevent11h = 0x72b + val mhpmevent12h = 0x72c + val mhpmevent13h = 0x72d + val mhpmevent14h = 0x72e + val mhpmevent15h = 0x72f + val mhpmevent16h = 0x730 + val mhpmevent17h = 0x731 + val mhpmevent18h = 0x732 + val mhpmevent19h = 0x733 + val mhpmevent20h = 0x734 + val mhpmevent21h = 0x735 + val mhpmevent22h = 0x736 + val mhpmevent23h = 0x737 + val mhpmevent24h = 0x738 + val mhpmevent25h = 0x739 + val mhpmevent26h = 0x73a + val mhpmevent27h = 0x73b + val mhpmevent28h = 0x73c + val mhpmevent29h = 0x73d + val mhpmevent30h = 0x73e + val mhpmevent31h = 0x73f + val mnscratch = 0x740 + val mnepc = 0x741 + val mncause = 0x742 + val mnstatus = 0x744 + val mseccfgh = 0x757 + val mcycleh = 0xb80 + val minstreth = 0xb82 + val mhpmcounter3h = 0xb83 + val mhpmcounter4h = 0xb84 + val mhpmcounter5h = 0xb85 + val mhpmcounter6h = 0xb86 + val mhpmcounter7h = 0xb87 + val mhpmcounter8h = 0xb88 + val mhpmcounter9h = 0xb89 val mhpmcounter10h = 0xb8a val mhpmcounter11h = 0xb8b val mhpmcounter12h = 0xb8c @@ -1596,7 +786,7 @@ object CSRs { res.toArray } val all32 = { - val res = collection.mutable.ArrayBuffer(all:_*) + val res = collection.mutable.ArrayBuffer(all: _*) res += sieh res += siph res += stimecmph diff --git a/chisel/playground/src/defines/isa/RVI.scala b/chisel/playground/src/defines/isa/RVI.scala new file mode 100644 index 0000000..4e37e8f --- /dev/null +++ b/chisel/playground/src/defines/isa/RVI.scala @@ -0,0 +1,165 @@ +package cpu.defines + +import chisel3._ +import chisel3.util._ + +trait HasInstrType { + def InstrN = "b0000".U + def InstrI = "b0100".U + def InstrR = "b0101".U + def InstrS = "b0010".U + def InstrB = "b0001".U + def InstrU = "b0110".U + def InstrJ = "b0111".U + def InstrA = "b1110".U + def InstrSA = "b1111".U // Atom Inst: SC + + def isrfWen(instrType: UInt): Bool = instrType(2) +} + +object RV32I_ALUInstr extends HasInstrType with CoreParameter { + def ADDI = BitPat("b????????????_?????_000_?????_0010011") + def SLLI = if (XLEN == 32) BitPat("b0000000?????_?????_001_?????_0010011") + else BitPat("b000000??????_?????_001_?????_0010011") + def SLTI = BitPat("b????????????_?????_010_?????_0010011") + def SLTIU = BitPat("b????????????_?????_011_?????_0010011") + def XORI = BitPat("b????????????_?????_100_?????_0010011") + def SRLI = if (XLEN == 32) BitPat("b0000000?????_?????_101_?????_0010011") + else BitPat("b000000??????_?????_101_?????_0010011") + def ORI = BitPat("b????????????_?????_110_?????_0010011") + def ANDI = BitPat("b????????????_?????_111_?????_0010011") + def SRAI = if (XLEN == 32) BitPat("b0100000?????_?????_101_?????_0010011") + else BitPat("b010000??????_?????_101_?????_0010011") + + def ADD = BitPat("b0000000_?????_?????_000_?????_0110011") + def SLL = BitPat("b0000000_?????_?????_001_?????_0110011") + def SLT = BitPat("b0000000_?????_?????_010_?????_0110011") + def SLTU = BitPat("b0000000_?????_?????_011_?????_0110011") + def XOR = BitPat("b0000000_?????_?????_100_?????_0110011") + def SRL = BitPat("b0000000_?????_?????_101_?????_0110011") + def OR = BitPat("b0000000_?????_?????_110_?????_0110011") + def AND = BitPat("b0000000_?????_?????_111_?????_0110011") + def SUB = BitPat("b0100000_?????_?????_000_?????_0110011") + def SRA = BitPat("b0100000_?????_?????_101_?????_0110011") + + def AUIPC = BitPat("b????????????????????_?????_0010111") + def LUI = BitPat("b????????????????????_?????_0110111") + + val table = Array( + ADDI -> List(InstrI, FuType.alu, ALUOpType.add), + SLLI -> List(InstrI, FuType.alu, ALUOpType.sll), + SLTI -> List(InstrI, FuType.alu, ALUOpType.slt), + SLTIU -> List(InstrI, FuType.alu, ALUOpType.sltu), + XORI -> List(InstrI, FuType.alu, ALUOpType.xor), + SRLI -> List(InstrI, FuType.alu, ALUOpType.srl), + ORI -> List(InstrI, FuType.alu, ALUOpType.or), + ANDI -> List(InstrI, FuType.alu, ALUOpType.and), + SRAI -> List(InstrI, FuType.alu, ALUOpType.sra), + ADD -> List(InstrR, FuType.alu, ALUOpType.add), + SLL -> List(InstrR, FuType.alu, ALUOpType.sll), + SLT -> List(InstrR, FuType.alu, ALUOpType.slt), + SLTU -> List(InstrR, FuType.alu, ALUOpType.sltu), + XOR -> List(InstrR, FuType.alu, ALUOpType.xor), + SRL -> List(InstrR, FuType.alu, ALUOpType.srl), + OR -> List(InstrR, FuType.alu, ALUOpType.or), + AND -> List(InstrR, FuType.alu, ALUOpType.and), + SUB -> List(InstrR, FuType.alu, ALUOpType.sub), + SRA -> List(InstrR, FuType.alu, ALUOpType.sra), + AUIPC -> List(InstrU, FuType.alu, ALUOpType.add), + LUI -> List(InstrU, FuType.alu, ALUOpType.add) + ) +} + +object RV32I_BRUInstr extends HasInstrType { + def JAL = BitPat("b????????????????????_?????_1101111") + def JALR = BitPat("b????????????_?????_000_?????_1100111") + + def BNE = BitPat("b???????_?????_?????_001_?????_1100011") + def BEQ = BitPat("b???????_?????_?????_000_?????_1100011") + def BLT = BitPat("b???????_?????_?????_100_?????_1100011") + def BGE = BitPat("b???????_?????_?????_101_?????_1100011") + def BLTU = BitPat("b???????_?????_?????_110_?????_1100011") + def BGEU = BitPat("b???????_?????_?????_111_?????_1100011") + + val table = Array( + JAL -> List(InstrJ, FuType.bru, ALUOpType.jal), + JALR -> List(InstrI, FuType.bru, ALUOpType.jalr), + BEQ -> List(InstrB, FuType.bru, ALUOpType.beq), + BNE -> List(InstrB, FuType.bru, ALUOpType.bne), + BLT -> List(InstrB, FuType.bru, ALUOpType.blt), + BGE -> List(InstrB, FuType.bru, ALUOpType.bge), + BLTU -> List(InstrB, FuType.bru, ALUOpType.bltu), + BGEU -> List(InstrB, FuType.bru, ALUOpType.bgeu) + ) + + val bruFuncTobtbTypeTable = List( + ALUOpType.beq -> BTBtype.B, + ALUOpType.bne -> BTBtype.B, + ALUOpType.blt -> BTBtype.B, + ALUOpType.bge -> BTBtype.B, + ALUOpType.bltu -> BTBtype.B, + ALUOpType.bgeu -> BTBtype.B, + ALUOpType.call -> BTBtype.J, + ALUOpType.ret -> BTBtype.R, + ALUOpType.jal -> BTBtype.J, + ALUOpType.jalr -> BTBtype.I + ) +} + +object RV32I_LSUInstr extends HasInstrType { + def LB = BitPat("b????????????_?????_000_?????_0000011") + def LH = BitPat("b????????????_?????_001_?????_0000011") + def LW = BitPat("b????????????_?????_010_?????_0000011") + def LBU = BitPat("b????????????_?????_100_?????_0000011") + def LHU = BitPat("b????????????_?????_101_?????_0000011") + def SB = BitPat("b???????_?????_?????_000_?????_0100011") + def SH = BitPat("b???????_?????_?????_001_?????_0100011") + def SW = BitPat("b???????_?????_?????_010_?????_0100011") + + val table = Array( + LB -> List(InstrI, FuType.lsu, LSUOpType.lb), + LH -> List(InstrI, FuType.lsu, LSUOpType.lh), + LW -> List(InstrI, FuType.lsu, LSUOpType.lw), + LBU -> List(InstrI, FuType.lsu, LSUOpType.lbu), + LHU -> List(InstrI, FuType.lsu, LSUOpType.lhu), + SB -> List(InstrS, FuType.lsu, LSUOpType.sb), + SH -> List(InstrS, FuType.lsu, LSUOpType.sh), + SW -> List(InstrS, FuType.lsu, LSUOpType.sw) + ) +} + +object RV64IInstr extends HasInstrType { + def ADDIW = BitPat("b???????_?????_?????_000_?????_0011011") + def SLLIW = BitPat("b0000000_?????_?????_001_?????_0011011") + def SRLIW = BitPat("b0000000_?????_?????_101_?????_0011011") + def SRAIW = BitPat("b0100000_?????_?????_101_?????_0011011") + def SLLW = BitPat("b0000000_?????_?????_001_?????_0111011") + def SRLW = BitPat("b0000000_?????_?????_101_?????_0111011") + def SRAW = BitPat("b0100000_?????_?????_101_?????_0111011") + def ADDW = BitPat("b0000000_?????_?????_000_?????_0111011") + def SUBW = BitPat("b0100000_?????_?????_000_?????_0111011") + + def LWU = BitPat("b???????_?????_?????_110_?????_0000011") + def LD = BitPat("b???????_?????_?????_011_?????_0000011") + def SD = BitPat("b???????_?????_?????_011_?????_0100011") + + val table = Array( + ADDIW -> List(InstrI, FuType.alu, ALUOpType.addw), + SLLIW -> List(InstrI, FuType.alu, ALUOpType.sllw), + SRLIW -> List(InstrI, FuType.alu, ALUOpType.srlw), + SRAIW -> List(InstrI, FuType.alu, ALUOpType.sraw), + SLLW -> List(InstrR, FuType.alu, ALUOpType.sllw), + SRLW -> List(InstrR, FuType.alu, ALUOpType.srlw), + SRAW -> List(InstrR, FuType.alu, ALUOpType.sraw), + ADDW -> List(InstrR, FuType.alu, ALUOpType.addw), + SUBW -> List(InstrR, FuType.alu, ALUOpType.subw), + LWU -> List(InstrI, FuType.lsu, LSUOpType.lwu), + LD -> List(InstrI, FuType.lsu, LSUOpType.ld), + SD -> List(InstrS, FuType.lsu, LSUOpType.sd) + ) +} + +object RVIInstr extends CoreParameter { + val table = RV32I_ALUInstr.table ++ RV32I_BRUInstr.table ++ RV32I_LSUInstr.table ++ + (if (XLEN == 64) RV64IInstr.table else Array.empty) +} diff --git a/chisel/playground/src/defines/isa/RVM.scala b/chisel/playground/src/defines/isa/RVM.scala new file mode 100644 index 0000000..1679a8c --- /dev/null +++ b/chisel/playground/src/defines/isa/RVM.scala @@ -0,0 +1,57 @@ +package cpu.defines + +import chisel3._ +import chisel3.util._ + +object RV32MInstr extends HasInstrType with CoreParameter { + def MUL = BitPat("b0000001_?????_?????_000_?????_0110011") + def MULH = BitPat("b0000001_?????_?????_001_?????_0110011") + def MULHSU = BitPat("b0000001_?????_?????_010_?????_0110011") + def MULHU = BitPat("b0000001_?????_?????_011_?????_0110011") + def DIV = BitPat("b0000001_?????_?????_100_?????_0110011") + def DIVU = BitPat("b0000001_?????_?????_101_?????_0110011") + def REM = BitPat("b0000001_?????_?????_110_?????_0110011") + def REMU = BitPat("b0000001_?????_?????_111_?????_0110011") + def MULW = BitPat("b0000001_?????_?????_000_?????_0111011") + def DIVW = BitPat("b0000001_?????_?????_100_?????_0111011") + def DIVUW = BitPat("b0000001_?????_?????_101_?????_0111011") + def REMW = BitPat("b0000001_?????_?????_110_?????_0111011") + def REMUW = BitPat("b0000001_?????_?????_111_?????_0111011") + + val mulTable = Array( + MUL -> List(InstrR, FuType.mdu, MDUOpType.mul), + MULH -> List(InstrR, FuType.mdu, MDUOpType.mulh), + MULHSU -> List(InstrR, FuType.mdu, MDUOpType.mulhsu), + MULHU -> List(InstrR, FuType.mdu, MDUOpType.mulhu) + ) + val divTable = Array( + DIV -> List(InstrR, FuType.mdu, MDUOpType.div), + DIVU -> List(InstrR, FuType.mdu, MDUOpType.divu), + REM -> List(InstrR, FuType.mdu, MDUOpType.rem), + REMU -> List(InstrR, FuType.mdu, MDUOpType.remu) + ) + val table = mulTable ++ (if (config.hasMDU) divTable else Array.empty) +} + +object RV64MInstr extends HasInstrType with CoreParameter { + def MULW = BitPat("b0000001_?????_?????_000_?????_0111011") + def DIVW = BitPat("b0000001_?????_?????_100_?????_0111011") + def DIVUW = BitPat("b0000001_?????_?????_101_?????_0111011") + def REMW = BitPat("b0000001_?????_?????_110_?????_0111011") + def REMUW = BitPat("b0000001_?????_?????_111_?????_0111011") + + val mulTable = Array( + MULW -> List(InstrR, FuType.mdu, MDUOpType.mulw) + ) + val divTable = Array( + DIVW -> List(InstrR, FuType.mdu, MDUOpType.divw), + DIVUW -> List(InstrR, FuType.mdu, MDUOpType.divuw), + REMW -> List(InstrR, FuType.mdu, MDUOpType.remw), + REMUW -> List(InstrR, FuType.mdu, MDUOpType.remuw) + ) + val table = mulTable ++ (if (config.hasMDU) divTable else Array.empty) +} + +object RVMInstr extends CoreParameter { + val table = RV32MInstr.table ++ (if (XLEN == 64) RV64MInstr.table else Array.empty) +} diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala index ef3a962..353c525 100644 --- a/chisel/playground/src/pipeline/decoder/Decoder.scala +++ b/chisel/playground/src/pipeline/decoder/Decoder.scala @@ -16,137 +16,190 @@ class Decoder extends Module { }) val inst = io.in.inst - val signals: List[UInt] = ListLookup( - //@formatter:off - inst, - List(INST_INVALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - Array( /* inst_valid | reg1_ren | reg2_ren | fusel | op | reg_wen | reg_waddr | imm_type | dual_issue */ - // NOP - NOP -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - // 位操作 - OR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - AND -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - XOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - NOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_NOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - // 移位 - SLLV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - SRLV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - SRAV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - SLL -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE), - SRL -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE), - SRA -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE), - // 立即数 - ORI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE), - ANDI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE), - XORI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE), - LUI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T2, IMM_HZE, DUAL_ISSUE), + val table: Array[(BitPat, List[BitPat])] = Array( + BNE-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SNE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BEQ-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SEQ, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BLT-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BLTU-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BGE-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGE, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + BGEU-> List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGEU, N,M_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - // Move - MOVN -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVN, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - MOVZ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVZ, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + JAL-> List(Y,N,N,N,Y,N,N,N,N,N,N,A2_SIZE,A1_PC, IMM_UJ,DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + JALR-> List(Y,N,N,N,N,Y,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + AUIPC-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - // HI，LO的Move指令 - MFHI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFHI, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - MFLO -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFLO, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - MTHI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MTHILO, EXE_MTHI, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - MTLO -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MTHILO, EXE_MTLO, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + LB-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + LH-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + LW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + LBU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + LHU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, Y,M_XRD, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SB-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + SH-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), + SW-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD, Y,M_XWR, N,N,N,N,N,N,N,CSR.N,N,N,N,N), - // C0的Move指令 - MFC0 -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_MFC0, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - MTC0 -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_MTC0, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + LUI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + ADDI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLTI -> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLTIU-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + ANDI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + ORI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + XORI-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + ADD-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SUB-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SUB, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLT-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLT, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLTU-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLTU, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + AND-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_AND, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + OR-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_OR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + XOR-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_XOR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SLL-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SL, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRL-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SR, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), + SRA-> List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SRA, N,M_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N), - // 比较指令 - SLT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLT, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - SLTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - // 立即数 - SLTI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLT, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE), - SLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE), + FENCE-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.N,N,Y,N,N), - // Trap - TEQ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TEQ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - TEQI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TEQ, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), - TGE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TGE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - TGEI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGE, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), - TGEIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), - TGEU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - TLT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TLT, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - TLTI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLT, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), - TLTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - TLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), - TNE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TNE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - TNEI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TNE, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), + ECALL-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + EBREAK-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + MRET-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + WFI-> List(Y,N,N,N,N,N,N,X,N,N,N,A2_X, A1_X, IMM_X, DW_X, aluFn.FN_X, N,M_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N), + CSRRW-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N), + CSRRS-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N), + CSRRC-> List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N), + CSRRWI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N), + CSRRSI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N), + CSRRCI-> List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD, N,M_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N)) - // 算术指令 - ADD -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_ADD, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - ADDU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_ADDU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - SUB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SUB, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - SUBU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SUBU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - MUL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MUL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - MULT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MULT, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - MULTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MULTU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - MADD -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MADD, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - MADDU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MADDU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - MSUB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MSUB, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - MSUBU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MSUBU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - DIV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_DIV, EXE_DIV, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - DIVU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_DIV, EXE_DIVU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - CLO -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLO, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - CLZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLZ, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - // 立即数 - ADDI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADD, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE), - ADDIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADDU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE), - // 跳转指令 - J -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_J, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - JAL -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_JAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE), - JR -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_JR, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - JALR -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_JALR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - BEQ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_BR, EXE_BEQ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - BNE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_BR, EXE_BNE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - BGTZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGTZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - BLEZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLEZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - BGEZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGEZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - BGEZAL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGEZAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE), - BLTZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLTZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - BLTZAL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLTZAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE), - // TLB - TLBP -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBP, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), - TLBR -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBR, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), - TLBWI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWI, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), - TLBWR -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWR, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + // val signals: List[UInt] = ListLookup( + // //@formatter:off + // inst, + // List(INST_INVALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // Array( /* inst_valid | reg1_ren | reg2_ren | fusel | op | reg_wen | reg_waddr | imm_type | dual_issue */ + // // NOP + // NOP -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // // 位操作 + // OR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // AND -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // XOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // NOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_NOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // // 移位 + // SLLV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // SRLV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // SRAV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // SLL -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE), + // SRL -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE), + // SRA -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE), + // // 立即数 + // ORI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE), + // ANDI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE), + // XORI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE), + // LUI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR, WRITE_ENABLE, WRA_T2, IMM_HZE, DUAL_ISSUE), - // 例外指令 - SYSCALL -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_SYSCALL, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), - BREAK -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_BREAK, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), - ERET -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_ERET, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), - WAIT -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + // // Move + // MOVN -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVN, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // MOVZ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVZ, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), - // 访存指令 - LB -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LB, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - LBU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LBU, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - LH -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LH, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - LHU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LHU, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - LW -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LW, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - SB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SB, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - SH -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SH, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - SW -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SW, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - LWL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_LWL, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - LWR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_LWR, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - SWL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SWL, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - SWR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SWR, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // // HI，LO的Move指令 + // MFHI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFHI, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // MFLO -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFLO, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // MTHI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MTHILO, EXE_MTHI, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // MTLO -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MTHILO, EXE_MTLO, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + + // // C0的Move指令 + // MFC0 -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_MFC0, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // MTC0 -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_MTC0, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + + // // 比较指令 + // SLT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLT, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // SLTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // // 立即数 + // SLTI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLT, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE), + // SLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE), + + // // Trap + // TEQ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TEQ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // TEQI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TEQ, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), + // TGE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TGE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // TGEI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGE, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), + // TGEIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), + // TGEU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // TLT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TLT, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // TLTI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLT, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), + // TLTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // TLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), + // TNE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_EX, EXE_TNE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // TNEI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TNE, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE), + + // // 算术指令 + // ADD -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_ADD, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // ADDU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_ADDU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // SUB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SUB, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // SUBU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SUBU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // MUL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MUL, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // MULT -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MULT, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // MULTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MULTU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // MADD -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MADD, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // MADDU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MADDU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // MSUB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MSUB, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // MSUBU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MUL, EXE_MSUBU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // DIV -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_DIV, EXE_DIV, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // DIVU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_DIV, EXE_DIVU, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // CLO -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLO, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // CLZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLZ, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // // 立即数 + // ADDI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADD, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE), + // ADDIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADDU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE), + // // 跳转指令 + // J -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_J, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // JAL -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_JAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE), + // JR -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_JR, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // JALR -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_JALR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE), + // BEQ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_BR, EXE_BEQ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // BNE -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_BR, EXE_BNE, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // BGTZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGTZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // BLEZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLEZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // BGEZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGEZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // BGEZAL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BGEZAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE), + // BLTZ -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLTZ, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // BLTZAL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_BR, EXE_BLTZAL, WRITE_ENABLE, WRA_T3, IMM_N, DUAL_ISSUE), + + // // TLB + // TLBP -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBP, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + // TLBR -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBR, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + // TLBWI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWI, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + // TLBWR -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWR, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + + // // 例外指令 + // SYSCALL -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_SYSCALL, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + // BREAK -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_BREAK, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + // ERET -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_ERET, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + // WAIT -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + + // // 访存指令 + // LB -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LB, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // LBU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LBU, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // LH -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LH, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // LHU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LHU, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // LW -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LW, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // SB -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SB, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // SH -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SH, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // SW -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SW, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // LWL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_LWL, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // LWR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_LWR, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // SWL -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SWL, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // SWR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SWR, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - LL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LL, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - SC -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SC, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // LL -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_MEM, EXE_LL, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), + // SC -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_MEM, EXE_SC, WRITE_ENABLE, WRA_T2, IMM_N, DUAL_ISSUE), - SYNC -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - PREF -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_ENABLE, WRA_X, IMM_N, DUAL_ISSUE), - PREFX -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // SYNC -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), + // PREF -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_ENABLE, WRA_X, IMM_N, DUAL_ISSUE), + // PREFX -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE), - // Cache - CACHE -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CACHE, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), - ), - // @formatter:on - ) + // // Cache + // CACHE -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CACHE, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE), + // ), + // // @formatter:on + // ) val inst_valid :: reg1_ren :: reg2_ren :: fusel :: op :: reg_wen :: reg_waddr_type :: imm_type :: dual_issue :: Nil = signals