Clo91eaf
|
a765eed394
|
fix(top_sram_wrapper) fix bit bug
|
2024-05-11 14:15:32 +08:00 |
Liphen
|
5bd7124535
|
feat(debug): 增加sram差分测试接口
|
2024-05-11 11:40:26 +08:00 |
|
Liphen
|
4a9e3dc05f
|
修改debug信号的wen为commit
|
2024-05-09 19:16:02 +08:00 |
|
Liphen
|
2c7af2ce4b
|
增加sram的顶层接口
|
2024-03-22 11:13:19 +08:00 |
|
Liphen
|
301199c756
|
feat: 添加icache成功生成Verilog
|
2023-12-21 15:24:57 +08:00 |
|
Liphen
|
152bc91507
|
fix(dcache): 修复取数据问题
|
2023-11-27 14:14:19 +08:00 |
|
Liphen
|
6fbb02fffc
|
生成verilog
|
2023-11-23 16:08:39 +08:00 |
|
Liphen
|
8913ae5da0
|
修改了部分前端设计，去除cache、tlb
|
2023-11-12 15:50:49 +08:00 |
|
Liphen
|
3c7beb03c6
|
增加pua-mips代码
|
2023-11-07 17:58:40 +08:00 |