Merge branch 'main' of github.com:Ciliphen/DC-CA-SA-Lab
This commit is contained in:
commit
fa9c7afce3
|
@ -64,4 +64,5 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
|
||||||
io.regfile(1).wdata
|
io.regfile(1).wdata
|
||||||
)
|
)
|
||||||
}
|
}
|
||||||
|
io.debug.wb_rf_wen := io.ctrl.allow_to_go
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue