From 24baf95dd73af5be9ea9f2c3c5c1b0e189688180 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Thu, 23 Nov 2023 16:17:15 +0800
Subject: [PATCH] =?UTF-8?q?=E5=8F=AF=E4=BB=A5=E5=AE=9E=E7=8E=B0=E5=B7=AE?=
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---
 chisel/Makefile                                              | 2 +-
 chisel/difftest                                              | 2 +-
 chisel/playground/src/pipeline/writeback/WriteBackUnit.scala | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/chisel/Makefile b/chisel/Makefile
index 792560a..c90f6a3 100644
--- a/chisel/Makefile
+++ b/chisel/Makefile
@@ -10,7 +10,7 @@ verilog:
 	mill -i __.test.runMain Elaborate -td $(BUILD_DIR)
 
 func:
-	# cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
+	cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
 	cd $(DIFF_WORK_DIR) && make func
 
 test:
diff --git a/chisel/difftest b/chisel/difftest
index 1f6c6a6..219f3b9 160000
--- a/chisel/difftest
+++ b/chisel/difftest
@@ -1 +1 @@
-Subproject commit 1f6c6a632c18a0fd1daf6b1c09a8fa56717b7679
+Subproject commit 219f3b97c692c2b0c16aca7769487e3ab4fbe0a5
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 243fdfd..26aa562 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -64,4 +64,5 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
       io.regfile(1).wdata
     )
   }
+  io.debug.wb_rf_wen := io.ctrl.allow_to_go
 }