可以实现差分测试

chisel/Makefile

@@ -10,7 +10,7 @@ verilog:
 	mill -i __.test.runMain Elaborate -td $(BUILD_DIR)
 
 func:
-	# cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
+	cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
 	cd $(DIFF_WORK_DIR) && make func
 
 test:

chisel/difftest

@@ -1 +1 @@
-Subproject commit 1f6c6a632c18a0fd1daf6b1c09a8fa56717b7679
+Subproject commit 219f3b97c692c2b0c16aca7769487e3ab4fbe0a5

chisel/playground/src/pipeline/writeback/WriteBackUnit.scala

@@ -64,4 +64,5 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
       io.regfile(1).wdata
     )
   }
+  io.debug.wb_rf_wen := io.ctrl.allow_to_go
 }