diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 243fdfd..26aa562 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -64,4 +64,5 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
       io.regfile(1).wdata
     )
   }
+  io.debug.wb_rf_wen := io.ctrl.allow_to_go
 }