yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

feat: 成功生成sram的verilog

This commit is contained in:
Liphen 2024-03-22 22:57:04 +08:00
parent 0a20a7cda9
commit 81b3915c46
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
chisel/playground/src/pipeline/execute/fu/Lsu.scala
View File

@ -120,6 +120,7 @@ class Lsu extends Module {
io.dataSram.addr := req_addr io.dataSram.addr := req_addr
io.dataSram.wdata := req_wdata io.dataSram.wdata := req_wdata
val result = Mux(partial_load, rdata_partial_result, rdata_result) val result = Wire(UInt(XLEN.W))
result := Mux(partial_load, rdata_partial_result, rdata_result)
BoringUtils.addSource(result, "lsu_rdata") BoringUtils.addSource(result, "lsu_rdata")
} }