!572 kernel部件化编译构建（liteos_m仓库修改）

Merge pull request !572 from Hongjin Li/lihongjin/br_dev

.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md

@@ -1,6 +1,6 @@
 ### 相关的Issue
 
-  
+
 ### 原因（目的、解决的问题等）
 
 
@@ -8,5 +8,14 @@
 
 
 ### 测试用例（新增、改动、可能影响的功能）
-    
-    
+
+
+### 是否需要同步至release（如：3.0LTS ... ）分支？
+
+必须选择一项（在MarkDown模式下用[x]替换[ ]即可勾选对应选项）:
+- [ ] 是，需要同步的分支：
+- [ ] 否
+
+理由：
+
+

BUILD.gn

@@ -33,25 +33,9 @@ LITEOS_MENUCONFIG_H = rebase_path("$root_out_dir/config.h")
 
 declare_args() {
   liteos_name = "OHOS_Image"
-  liteos_config_file = "${ohos_build_type}.config"
   liteos_kernel_only = false
 }
 
-liteos_config_file =
-    rebase_path(liteos_config_file, "", "$product_path/kernel_configs")
-print("liteos_config_file:", liteos_config_file)
-
-exec_script("//build/lite/run_shell_cmd.py",
-            [ "env" + " CONFIG_=LOSCFG_" + " KCONFIG_CONFIG_HEADER='y=true'" +
-                  " KCONFIG_CONFIG=$liteos_config_file" +
-                  " BOARD_COMPANY=$device_company" +
-                  " DEVICE_PATH=$device_path" + " srctree=" + rebase_path(".") +
-                  " genconfig" + " --header-path $LITEOS_MENUCONFIG_H" +
-                  " --file-list kconfig_files.txt" +
-                  " --env-list kconfig_env.txt" + " --config-out config.gni" ],
-            "",
-            [ liteos_config_file ])
-
 import("liteos.gni")
 
 liteos_arch_cflags = []
@@ -159,6 +143,7 @@ config("kconfig_config") {
     "$LITEOS_MENUCONFIG_H",
   ]
   asmflags = cflags
+  cflags_cc = cflags
 }
 
 config("warn_config") {

Kconfig

@@ -50,7 +50,7 @@ config COMPILER_CLANG_LLVM
 config LLVM_TARGET
     string "Clang LLVM target"
     depends on COMPILER_CLANG_LLVM
-    default "arm-liteos" if ARCH_ARM_AARCH32
+    default "arm-liteos-ohos" if ARCH_ARM_AARCH32
 
 endchoice
 
@@ -286,6 +286,8 @@ config KERNEL_CPPSUPPORT
     help
       If you wish to build LiteOS with support for C++.
 
+rsource "components/signal/Kconfig"
+
 config BASE_CORE_CPUP
     bool
     default n

Makefile

@@ -98,7 +98,7 @@ endef
 export HELP
 
 all:
-	$(HIDE)hb build -f --gn-args "liteos_kernel_only=true liteos_name=$(LITEOS_TARGET)"
+	$(HIDE)hb build -f --gn-args "liteos_kernel_only=true liteos_name=\"$(LITEOS_TARGET)\""
 
 help:
 	$(HIDE)echo "$$HELP"

README.md

@@ -4,6 +4,7 @@
 -   [Directory Structure](#section161941989596)
 -   [Constraints](#section119744591305)
 -   [Usage](#section3732185231214)
+-   [Contribution](#section1371123476307)
 -   [Repositories Involved](#section1371113476307)
 
 ## Introduction<a name="section11660541593"></a>
@@ -21,24 +22,46 @@ The directory structure is as follows. For more details, see [arch_spec.md](arch
 
 ```
 /kernel/liteos_m
+├── arch                 # Code of the kernel instruction architecture layer
+│   ├── arm              # Code of the ARM32 architecture
+│   │   ├── arm9         # Code of the ARM9 architecture
+│   │   ├── cortex-m3    # Code of the cortex-m3 architecture
+│   │   ├── cortex-m33   # Code of the cortex-m33 architecture
+│   │   ├── cortex-m4    # Code of the cortex-m4 architecture
+│   │   ├── cortex-m7    # Code of the cortex-m7 architecture
+│   │   └── include      # Arm architecture public header file directory
+│   ├── csky             # Code of the csky architecture
+│   │   └── v2           # Code of the csky v2 architecture
+│   ├── include          # APIs exposed externally
+│   ├── risc-v           # Code of the risc-v architecture
+│   │   ├── nuclei       # Code of the nuclei system technology risc-v architecture
+│   │   └── riscv32      # Code of the risc-v architecture
+│   └── xtensa           # Code of the xtensa architecture
+│       └── lx6          # Code of the lx6 xtensa architecture
 ├── components           # Optional components
 │   ├── backtrace        # Backtrace support
 │   ├── cppsupport       # C++ support
-│   └── cpup             # CPU percent (CPUP)
+│   ├── cpup             # CPU percent (CPUP)
 │   ├── dynlink          # Dynamic loading and linking
 │   ├── exchook          # Exception hooks
 │   ├── fs               # File systems
-│   └── net              # Networking functions
+│   ├── lmk              # Low memory killer functions
+│   ├── lms              # Lite memory sanitizer functions
+│   ├── net              # Networking functions
+│   ├── power            # Power management
+│   ├── shell            # Shell function
+│   ├── fs               # File systems
+│   └── trace            # Trace tool
+├── drivers              # driver Kconfig
 ├── kal                  # Kernel abstraction layer
 │   ├── cmsis            # CMSIS API support
 │   └── posix            # POSIX API support
 ├── kernel               # Minimum kernel function set
-│   ├── arch             # Code of the kernel instruction architecture layer
-│   │   ├── arm          # Code of the Arm32 architecture
-│   │   └── include      # APIs exposed externally
 │   ├── include          # APIs exposed externally
 │   └── src              # Source code of the minimum kernel function set
 ├── targets              # Board-level projects
+├── testsuites           # Kernel testsuites
+├── tools                # Kernel tools
 ├── utils                # Common directory
 ```
 
@@ -46,62 +69,27 @@ The directory structure is as follows. For more details, see [arch_spec.md](arch
 
 OpenHarmony LiteOS-M supports only C and C++.
 
-It applies only to Cortex-M3, Cortex-M4, Cortex-M7, and RISC-V chip architectures.
+Applicable architecture: See the directory structure for the arch layer.
 
 As for dynamic loading module, the shared library to be loaded needs signature verification or source restriction to ensure security.
 
 ## Usage<a name="section3732185231214"></a>
 
-The OpenHarmony LiteOS-M kernel build system is a modular build system based on Generate Ninja (GN) and Ninja. It supports module-based configuration, tailoring, and assembling, and helps you build custom products. This document describes how to build a LiteOS-M project based on GN and Ninja. For details about the methods such as GCC+Makefile, IAR, and Keil MDK, visit the community websites.
+The OpenHarmony LiteOS-M kernel build system is a modular build system based on Generate Ninja (GN) and Ninja. It supports module-based configuration, tailoring, and assembling, and helps you build custom products. This document describes how to build a LiteOS-M project based on GN and Ninja. For details about the methods such as GCC+gn, IAR, and Keil MDK, visit the community websites.
 
 ### Setting Up the Environment
 
-Before setting up the environment for a development board, you must set up the basic system environment for OpenHarmony first. The basic system environment includes the OpenHarmony build environment and development environment. For details, see [Setting Up Ubuntu Development Environment](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/quick-start/quickstart-lite-env-setup-linux.md). You need to install Python3.7+, GN, Ninja, and hb. For the LiteOS-M kernel, you also need to install the Make build tool and [GNU Arm Embedded Toolchain](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads).
+Before setting up the environment for a development board, you must set up the basic system environment for OpenHarmony first. The basic system environment includes the OpenHarmony build environment and development environment. For details, see [Setting Up Development Environment](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/quick-start/quickstart-lite-env-setup.md).
 
 ### Obtaining the OpenHarmony Source Code
 
-Obtain the latest OpenHarmony source code through Git clone on a Linux server. For details about how to obtain the source code, see [Source Code Acquisition](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/get-code/sourcecode-acquire.md). This document assumes that the clone directory is `~/openHarmony` after the complete OpenHarmony repository code is obtained.
+For details about how to obtain the source code, see [Source Code Acquisition](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/get-code/sourcecode-acquire.md). This document assumes that the clone directory is `~/openHarmony` after the complete OpenHarmony repository code is obtained.
 
-### Obtaining the Source Code of the Sample Project
+### Example projects that are already supported
 
-The following uses the development board Nucleo-F767Zi as an example to describe how to build and run the `OpenHarmony LiteOS-M` kernel project. In the local directory, run the following command to clone the sample code:
+Qemu simulator: `arm_mps2_an386、esp32、riscv32_virt、SmartL_E802`, For details about how to compile and run, see [qemu guide](https://gitee.com/openharmony/device_qemu)
 
-```
-git clone https://gitee.com/harylee/nucleo_f767zi.git
-```
-
-The code is cloned to **~/nucleo_f767zi**. Run the following commands to copy the **device** and **vendor** directories in the code directory to the corresponding directories of the **openHarmony** project:
-
-```
-mkdir ~/openHarmony/device/st
-
-cp -r ~/nucleo_f767zi/device/st/nucleo_f767zi ~/openHarmony/device/st/nucleo_f767zi
-
-chmod +x ~/openHarmony/device/st/nucleo_f767zi/build.sh
-
-cp -r ~/nucleo_f767zi/vendor/st ~/openHarmony/vendor/st
-```
-
-For details about the directory of the sample code, see [Board-Level Directory Specifications](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-chip-board-overview.md). If you need to port the development board, see [Board-Level OS Porting](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-chip-board.md).
-
-### Building and Running
-
-Before the build, configure the **bin** directory of the cross compilation toolchain in the **PATH** environment variable or set **board&#95;toolchain&#95;path** in the **device/st/nucleo&#95;f767zi/liteos&#95;m/config.gni** file to the **bin** directory of the cross compilation toolchain.
-In the **OpenHarmony** root directory, run the **hb set** command to set the product path, select **nucleo_f767zi**, and run the **hb build** command to start the build. 
-
-Example:
-
-```
-user@dev:~/OpenHarmony$ hb set
-
-[OHOS INFO] Input code path: # Press Enter and select nucleo_f767zi.
-
-OHOS Which product do you need? nucleo_f767zi@st
-
-user@dev:~/OpenHarmony$ hb build
-```
-
-The image is generated in the **~/openHarmony/out/nucleo&#95;f767zi/** directory. You can download the image file to the board by using the STM32 ST-LINK Utility software and run the image.
+Bestechnic: `bes2600`, For details about how to compile and run, see [Bestechnic developer guide](https://gitee.com/openharmony/device_soc_bestechnic)
 
 ### Community Porting Project Links
 
@@ -125,6 +113,20 @@ The LiteOS-M kernel porting projects for specific development boards are provide
 
         This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the Nucleo-F767ZI development board. The code supports build in Ninja, GCC, and IAR modes.
 
+## Contribution<a name="section1371123476307"></a>
+
+[How to involve](https://gitee.com/openharmony/docs/blob/HEAD/en/contribute/contribution.md)
+
+[Commit message spec](https://gitee.com/openharmony/kernel_liteos_m/wikis/Commit%20message%E8%A7%84%E8%8C%83)
+
+[Liteos-M kernel coding style guide](https://gitee.com/openharmony/kernel_liteos_m/wikis/OpenHarmony%E8%BD%BB%E5%86%85%E6%A0%B8%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83)
+
+How to contribute a chip based on Liteos-M kernel:
+
+[ Board-Level Directory Specifications](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-chip-board-overview.md)
+
+[Mini System SoC Porting Guide](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-minichip.md)
+
 ## Repositories Involved<a name="section1371113476307"></a>
 
 [Kernel Subsystem](https://gitee.com/openharmony/docs/blob/HEAD/en/readme/kernel-subsystem.md)

README_zh.md

@@ -4,6 +4,7 @@
 -   [目录](#section161941989596)
 -   [约束](#section119744591305)
 -   [使用说明](#section3732185231214)
+-   [贡献](#section1371123476307)
 -   [相关仓](#section1371113476307)
 
 ## 简介<a name="section11660541593"></a>
@@ -19,24 +20,45 @@ OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系
 
 ```
 /kernel/liteos_m
+├── arch                 # 内核指令架构层目录
+│   ├── arm              # arm 架构代码
+│   │   ├── arm9         # arm9 架构代码
+│   │   ├── cortex-m3    # cortex-m3架构代码
+│   │   ├── cortex-m33   # cortex-m33架构代码
+│   │   ├── cortex-m4    # cortex-m4架构代码
+│   │   ├── cortex-m7    # cortex-m7架构代码
+│   │   └── include      # arm架构公共头文件目录
+│   ├── csky             # csky架构代码
+│   │   └── v2           # csky v2架构代码
+│   ├── include          # 架构层对外接口存放目录
+│   ├── risc-v           # risc-v 架构
+│   │   ├── nuclei       # 芯来科技risc-v架构代码
+│   │   └── riscv32      # risc-v官方通用架构代码
+│   └── xtensa           # xtensa 架构代码
+│       └── lx6          # xtensa lx6架构代码
 ├── components           # 可选组件
-│   ├── backtrace        # 回溯栈支持
+│   ├── backtrace        # 栈回溯功能
 │   ├── cppsupport       # C++支持
 │   ├── cpup             # CPUP功能
 │   ├── dynlink          # 动态加载与链接
 │   ├── exchook          # 异常钩子
 │   ├── fs               # 文件系统
-│   └── net              # Network功能
+│   ├── lmk              # Low memory killer 机制
+│   ├── lms              # Lite memory sanitizer 机制
+│   ├── net              # Network功能
+│   ├── power            # 低功耗管理
+│   ├── shell            # shell功能
+│   └── trace            # trace 工具
+├── drivers              # 驱动框架Kconfig
 ├── kal                  # 内核抽象层
 │   ├── cmsis            # cmsis标准接口支持
 │   └── posix            # posix标准接口支持
 ├── kernel               # 内核最小功能集支持
-│   ├── arch             # 内核指令架构层代码
-│   │   ├── arm          # arm32架构的代码
-│   │   └── include      # 对外接口存放目录
 │   ├── include          # 对外接口存放目录
 │   └── src              # 内核最小功能集源码
 ├── targets              # 板级工程目录
+├── testsuites           # 内核测试用例
+├── tools                # 内核工具
 ├── utils                # 通用公共目录
 ```
 
@@ -44,60 +66,28 @@ OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系
 
 开发语言：C/C++；
 
-适用架构：当前只适用于cortex-m3、cortex-m4、cortex-m7、risc-v芯片架构。
+适用架构：详见目录结构arch层。
 
 动态加载模块：待加载的共享库需要验签或者限制来源，确保安全性。
 
 ## 使用说明<a name="section3732185231214"></a>
 
-OpenHarmony LiteOS-M内核的编译构建系统是一个基于gn和ninja的组件化构建系统，支持按组件配置、裁剪和拼装，按需构建出定制化的产品。本文主要介绍如何基于gn和ninja编译LiteOS-M工程，GCC+Makefile、IAR、Keil MDK等编译方式可以参考社区爱好者贡献的站点。
+OpenHarmony
+LiteOS-M内核的编译构建系统是一个基于gn和ninja的组件化构建系统，支持按组件配置、裁剪和拼装，按需构建出定制化的产品。本文主要介绍如何基于gn和ninja编译LiteOS-M工程，GCC+gn、IAR、Keil MDK等编译方式可以参考社区爱好者贡献的站点。
 
 ### 搭建系统基础环境
 
-在搭建各个开发板环境前，需要完成OpenHarmony系统基础环境搭建。系统基础环境主要是指OpenHarmony的编译环境和开发环境，详细介绍请参考官方站点[Ubuntu编译环境准备](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/quick-start/quickstart-lite-env-setup-linux.md)。开发者需要根据环境搭建文档，完成下述软件的安装：Python3.7+、gn、ninja、hb。对于LiteOS-M内核，还需要安装Make构建工具和[ARM GCC编译工具链](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads)。
+在搭建各个开发板环境前，需要完成OpenHarmony系统基础环境搭建。系统基础环境主要是指OpenHarmony的编译环境和开发环境，详细介绍请参考官方站点[开发环境准备](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/quick-start/quickstart-lite-env-setup.md)。开发者需要根据环境搭建文档完成环境搭建。
 
 ### 获取OpenHarmony源码
 
-开发者需要在Linux服务器上通过Git克隆获取OpenHarmony最新源码，详细的源码获取方式，请见[源码获取](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/get-code/sourcecode-acquire.md)。获取OpenHarmony完整仓代码后，假设克隆目录为`~/openHarmony`。
+详细的源码获取方式，请见[源码获取](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/get-code/sourcecode-acquire.md)。获取OpenHarmony完整仓代码后，假设克隆目录为`~/openHarmony`。
 
-### 获取示例工程源码
+### 已支持的示例工程
 
-以开发板Nucleo-F767Zi为例，演示如何编译运行`OpenHarmony LiteOS-M`内核工程。在本地目录，执行下述命令克隆示例代码。
+Qemu模拟器: `arm_mps2_an386、esp32、riscv32_virt、SmartL_E802`, 编译运行详见: [Qemu指导](https://gitee.com/openharmony/device_qemu)
 
-```
-git clone https://gitee.com/harylee/nucleo_f767zi.git
-```
-
-假设克隆到的代码目录为`~/nucleo_f767zi`。 执行如下命令把代码目录的`device`、`vendor`目录复制到`openHarmony`工程的相应目录。
-
-```
-mkdir ~/openHarmony/device/st
-
-cp -r ~/nucleo_f767zi/device/st/nucleo_f767zi ~/openHarmony/device/st/nucleo_f767zi
-
-chmod +x ~/openHarmony/device/st/nucleo_f767zi/build.sh
-
-cp -r ~/nucleo_f767zi/vendor/st ~/openHarmony/vendor/st
-```
-
-关于示例代码目录的说明，可以参考资料站点[板级目录规范](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/porting/porting-chip-board-overview.md)。如果需要自行移植开发板，请参考[板级系统移植](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/porting/porting-chip-board.md)。
-
-### 编译运行
-
-编译运行前，交叉编译工具链`bin`目录配置到`PATH`环境变量中或者配置`device/st/nucleo_f767zi/liteos_m/config.gni`文件中`board_toolchain_path`配置项为交叉编译工具链`bin`目录。
-在`OpenHarmony`根目录，执行`hb set`设置产品路径，选择`nucleo_f767zi`产品，然后执行`hb build`开启编译。如下：
-
-```
-user@dev:~/OpenHarmony$ hb set
-
-[OHOS INFO] Input code path: # 直接按回车，然后选择nucleo_f767zi产品即可
-
-OHOS Which product do you need? nucleo_f767zi@st
-
-user@dev:~/OpenHarmony$ hb build
-```
-
-最终的镜像生成在`~/openHarmony/out/nucleo_f767zi/`目录中，通过`STM32 ST-LINK Utility`软件将镜像文件下载至单板查看运行效果。
+恒玄科技: `bes2600`, 编译运行详见: [恒玄开发指导](https://gitee.com/openharmony/device_soc_bestechnic)
 
 ### 社区移植工程链接
 
@@ -121,6 +111,22 @@ LiteOS-M内核移植的具体开发板的工程由社区开发者提供，可以
 
         该仓包含OpenHarmony LiteOS-M内核移植支持`Nucleo-F767ZI`开发板的工程代码，支持Ninja、GCC、IAR等方式进行编译。
 
+## 贡献<a name="section1371123476307"></a>
+
+[如何贡献](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/contribute/%E5%8F%82%E4%B8%8E%E8%B4%A1%E7%8C%AE.md)
+
+[Commit message规范](https://gitee.com/openharmony/kernel_liteos_m/wikis/Commit%20message%E8%A7%84%E8%8C%83)
+
+[Liteos-M 内核编码规范](https://gitee.com/openharmony/kernel_liteos_m/wikis/OpenHarmony%E8%BD%BB%E5%86%85%E6%A0%B8%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83)
+
+如何基于Liteos-M内核贡献一款芯片:
+
+[板级目录规范](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/porting/porting-chip-board-overview.md)
+
+[轻量系统芯片移植指导](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/porting-minichip.md)
+
+[轻量系统芯片移植案例](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/porting-minichip-cases.md)
+
 ## 相关仓<a name="section1371113476307"></a>
 
 [内核子系统](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/readme/%E5%86%85%E6%A0%B8%E5%AD%90%E7%B3%BB%E7%BB%9F.md)

arch/arm/arm9/gcc/BUILD.gn

@@ -39,6 +39,7 @@ kernel_module(module_name) {
     "los_timer.c",
     "reset_vector.S",
   ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
 }
 
 config("public") {

arch/arm/arm9/gcc/los_arch_atomic.h

@@ -40,74 +40,187 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic exchange for 32-bit variable.
- *
- * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
- * @attention
- * <ul>The pointer v must not be NULL.</ul>
- *
- * @param  v       [IN] The variable pointer.
- * @param  val       [IN] The exchange value.
- *
- * @retval #INT32       The previous value of the atomic variable
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
 {
-    return -1;
+    return *v;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
 {
-    return -1;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic exchange for 32-bit variable with compare.
- *
- * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
- * @attention
- * <ul>The pointer v must not be NULL.</ul>
- *
- * @param  v       [IN] The variable pointer.
- * @param  val     [IN] The new value.
- * @param  oldVal      [IN] The old value.
- *
- * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
- * @retval FALSE The previous value of the atomic variable is equal to oldVal.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
 {
-    return FALSE;
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicXchg32bits(Atomic *v, INT32 val)
+{
+    INT32 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(Atomic *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
 }
 
 #ifdef __cplusplus

arch/arm/arm9/gcc/los_arch_interrupt.h

@@ -97,7 +97,8 @@ extern UINT32 g_intCount;
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a arm9 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -147,7 +148,8 @@ extern UINT32 g_intCount;
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a arm9 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -157,7 +159,8 @@ extern UINT32 g_intCount;
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -171,7 +174,7 @@ extern UINT32 g_intCount;
  */
 #define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_hwi
  * Set interrupt vector table.
@@ -204,25 +207,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_arch_interrupt
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_arch_interrupt
  * @brief: Default vector handling function.
@@ -322,15 +306,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/arm9/gcc/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/arm9/gcc/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,20 +73,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    LosTaskCB *taskCB = OS_TCB_FROM_TID(taskID);
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        PRINT_ERR("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
     context->r0 = taskID;
     context->r1 = 0x01010101L;
@@ -109,7 +91,7 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->r11 = 0x11111111L;
     context->r12 = 0x12121212L;
     context->sp = (UINTPTR)topStack + stackSize;
-    context->lr = (UINTPTR)HalSysExit;
+    context->lr = (UINTPTR)ArchSysExit;
 
     if ((UINTPTR)taskCB->taskEntry & 0x01) {
         context->pc = (UINTPTR)OsTaskEntryThumb;
@@ -122,7 +104,7 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();
@@ -131,7 +113,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
     return LOS_OK; /* never return */
 }
 
-LITE_OS_SEC_TEXT_INIT VOID HalTaskSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchTaskSchedule(VOID)
 {
     __asm__ __volatile__("swi 0");
 }

arch/arm/arm9/gcc/los_interrupt.c

@@ -48,9 +48,6 @@
 #define OS_INT_ENABLE_ADDR          (OS_INT_REG_BASE)
 #define OS_INT_STATUS_ADDR          (OS_INT_REG_BASE + 12)
 
-#define OS_INT_ENABLE(num)          (*((volatile UINT32 *)OS_INT_ENABLE_ADDR) |= (1U << (num)))
-#define OS_INT_DISABLE(num)         (*((volatile UINT32 *)OS_INT_ENABLE_ADDR ) &= ~(1U << (num)))
-
 #define OS_INSTR_SET_MASK           0x01000020U
 #define OS_ARM_INSTR_LEN            4
 #define OS_THUMB_INSTR_LEN          2
@@ -64,7 +61,7 @@ ExcInfo g_excInfo = {0};
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -112,21 +109,50 @@ VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
 
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     UINT32 status;
 
     READ_UINT32(status, OS_INT_STATUS_ADDR);
+
     return (31 - CLZ(status));
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    *((volatile UINT32 *)OS_INT_ENABLE_ADDR) |= (1U << (hwiNum));
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    *((volatile UINT32 *)OS_INT_ENABLE_ADDR) &= ~(1U << (hwiNum));
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .getCurIrqNum   = HwiNumGet,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -140,8 +166,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -175,13 +201,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
     OsSchedUpdateSleepTime();
 #endif
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -201,7 +227,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -211,11 +237,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -232,25 +258,25 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    OS_INT_ENABLE(hwiNum);
+    HwiUnmask(hwiNum);
     LOS_IntRestore(intSave);
 
     return LOS_OK;
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -258,7 +284,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
         return OS_ERRNO_HWI_NUM_INVALID;
     }
 
-    OS_INT_DISABLE(hwiNum);
+    HwiMask(hwiNum);
 
     intSave = LOS_IntLock();
     g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
@@ -316,6 +342,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->spsr);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -332,6 +359,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -381,7 +409,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcMemPoolCheckInfo();
 #endif
@@ -414,7 +444,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************
@@ -431,7 +461,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
     UINT32 val;
 
     for (val = OS_SYS_VECTOR_CNT; val < OS_VECTOR_CNT; val++) {
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
         g_hwiForm[val].pfnHook = HalHwiDefaultHandler;
         g_hwiForm[val].uwParam = 0;
 #else
@@ -447,7 +477,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
     return;
 }
 
-UINT32 HalIntLock(VOID)
+UINT32 ArchIntLock(VOID)
 {
     UINT32 ret;
     UINT32 temp;
@@ -461,12 +491,12 @@ UINT32 HalIntLock(VOID)
     return ret;
 }
 
-VOID HalIntRestore(UINT32 intSave)
+VOID ArchIntRestore(UINT32 intSave)
 {
     __asm__ __volatile__("MSR CPSR_c, %0" : : "r"(intSave));
 }
 
-UINT32 HalIntUnLock(VOID)
+UINT32 ArchIntUnLock(VOID)
 {
     UINT32 intSave;
 

arch/arm/arm9/gcc/los_timer.c

@@ -29,8 +29,8 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "los_timer.h"
 #include "los_config.h"
-#include "los_sched.h"
 #include "los_arch_context.h"
 #include "los_arch_interrupt.h"
 #include "los_reg.h"
@@ -51,18 +51,31 @@
 #define OS_TIMER_READ_CTL_ADDR      (OS_TIMER_REG_BASE + 16)
 #define OS_TIMER_READ_VAL_ADDR      (OS_TIMER_REG_BASE + 20)
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = OS_TIMER_IRQ_NUM,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 intSave = LOS_IntLock();
     UINT32 value;
 
+    ArchTickTimer *tick = &g_archTickTimer;
+    tick->freq = OS_SYS_CLOCK;
+
     READ_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
     value &= ~(OS_TIMER_32K_CLK_BIT);
     WRITE_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
@@ -77,13 +90,13 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     value |= OS_TIMER_ENABLE; // Enable timer.
     WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
 
-    (VOID)HalHwiCreate(OS_TIMER_IRQ_NUM, 0, 0, (HWI_PROC_FUNC)handler, 0);
+    (VOID)ArchHwiCreate(OS_TIMER_IRQ_NUM, 0, 0, (HWI_PROC_FUNC)handler, 0);
     LOS_IntRestore(intSave);
 
     return LOS_OK;
 }
 
-STATIC VOID HalClockIrqClear(VOID)
+STATIC VOID SysTickClockIrqClear(VOID)
 {
     UINT32 mask = OS_TIMER_INT_MASK << OS_TIMER_INT_POS;
     UINT32 status;
@@ -94,15 +107,15 @@ STATIC VOID HalClockIrqClear(VOID)
     } while (status & mask);
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
-    HalTickLock();
+    SysTickLock();
     WRITE_UINT32(nextResponseTime, OS_TIMER_PERIOD_REG_ADDR);
-    HalClockIrqClear();
-    HalTickUnlock();
+    SysTickClockIrqClear();
+    SysTickUnlock();
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 val;
 
@@ -118,7 +131,7 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)val;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     UINT32 value;
 
@@ -129,7 +142,7 @@ WEAK VOID HalTickLock(VOID)
     WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     UINT32 value;
 
@@ -140,7 +153,12 @@ WEAK VOID HalTickUnlock(VOID)
     WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     dsb();
     wfi();

arch/arm/cortex-m3/keil/los_arch_atomic.h

@@ -40,110 +40,105 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic exchange for 32-bit variable.
- *
- * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
- * @attention
- * <ul>The pointer v must not be NULL.</ul>
- *
- * @param  v       [IN] The variable pointer.
- * @param  val     [IN] The exchange value.
- *
- * @retval #INT32       The previous value of the atomic variable
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
 {
-    INT32 prevVal = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "strex   %1, %4, [%3]"
-                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
-                             : "r"(v), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return prevVal;
+    (VOID)ArchAtomicAdd(v, 1);
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
 {
-    INT32 val = 0;
-    UINT32 status = 0;
+    (VOID)ArchAtomicSub(v, 1);
+}
 
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
 
     return val;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic exchange for 32-bit variable with compare.
- *
- * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
- * @attention
- * <ul>The pointer v must not be NULL.</ul>
- *
- * @param  v       [IN] The variable pointer.
- * @param  val     [IN] The new value.
- * @param  oldVal  [IN] The old value.
- *
- * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
- * @retval FALSE The previous value of the atomic variable is equal to oldVal.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
 {
-    INT32 prevVal = 0;
-    UINT32 status = 0;
+    INT64 val;
+    UINT32 intSave;
 
-    do {
-        __asm__ __volatile__("1: ldrex %0, %2\n"
-                             "    mov %1, #0\n"
-                             "    cmp %0, %3\n"
-                             "    bne 2f\n"
-                             "    strex %1, %4, %2\n"
-                             "2:"
-                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
-                             : "r"(oldVal), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
 
     return prevVal != oldVal;
 }

arch/arm/cortex-m3/keil/los_arch_interrupt.h

@@ -109,7 +109,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M3 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -159,7 +160,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M3 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -169,7 +171,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -309,7 +312,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -342,25 +345,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_arch_interrupt
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_arch_interrupt
  * @brief: Default vector handling function.
@@ -528,7 +512,6 @@ VOID HalExcUsageFault(VOID);
 VOID HalExcSvcCall(VOID);
 VOID HalHwiInit(VOID);
 
-
 /**
  * @ingroup los_exc
  * Cortex-M exception types: An error occurred while the bus status register was being pushed.
@@ -665,15 +648,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m3/keil/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m3/keil/los_atomic.S

@@ -0,0 +1,98 @@
+;
+; Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this list of
+;    conditions and the following disclaimer.
+;
+; 2. Redistributions in binary form must reproduce the above copyright notice, this list
+;    of conditions and the following disclaimer in the documentation and/or other materials
+;    provided with the distribution.
+;
+; 3. Neither the name of the copyright holder nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without specific prior written
+;    permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+        EXPORT  ArchAtomicRead
+        EXPORT  ArchAtomicSet
+        EXPORT  ArchAtomicAdd
+        EXPORT  ArchAtomicSub
+        EXPORT  ArchAtomicXchg32bits
+        EXPORT  ArchAtomicCmpXchg32bits
+
+    PRESERVE8
+    AREA  |.text|, CODE, READONLY
+    THUMB
+
+
+        EXPORT  ArchAtomicRead
+        EXPORT  ArchAtomicSet
+        EXPORT  ArchAtomicAdd
+        EXPORT  ArchAtomicSub
+        EXPORT  ArchAtomicXchg32bits
+        EXPORT  ArchAtomicCmpXchg32bits
+
+    PRESERVE8
+    AREA  |.text|, CODE, READONLY
+    THUMB
+
+ArchAtomicRead
+    ldrex r1, [r0]
+    mov r0, r1
+    bx lr
+
+ArchAtomicSet
+    ldrex r2, [r0]
+    strex r3, r1, [r0]
+    teq r3, #0
+    bne ArchAtomicSet
+    bx lr
+
+ArchAtomicAdd
+    ldrex r2, [r0]
+    add r2, r2, r1
+    strex r3, r2, [r0]
+    teq r3, #0
+    bne ArchAtomicAdd
+    mov r0, r2
+    bx lr
+
+ArchAtomicSub
+    ldrex r2, [r0]
+    sub r2, r2, r1
+    strex r3, r2, [r0]
+    teq r3, #0
+    bne ArchAtomicSub
+    mov r0, r2
+    bx lr
+
+ArchAtomicXchg32bits
+    ldrex r2, [r0]
+    strex r3, r1, [r0]
+    teq r3, #0
+    bne ArchAtomicXchg32bits
+    mov r0, r2
+
+ArchAtomicCmpXchg32bits
+    ldrex r3, [r0]
+    cmp r3, r2
+    bne end
+    strex r4, r1, [r0]
+    teq r4, #0
+    bne ArchAtomicCmpXchg32bits
+end

arch/arm/cortex-m3/keil/los_context.c

@@ -37,35 +37,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -73,7 +66,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -81,19 +74,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -147,14 +130,14 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m3/keil/los_dispatch.S

@@ -31,11 +31,11 @@
 
         PRESERVE8
 
-        EXPORT  HalIntLock
-        EXPORT  HalIntUnLock
-        EXPORT  HalIntRestore
+        EXPORT  ArchIntLock
+        EXPORT  ArchIntUnLock
+        EXPORT  ArchIntRestore
         EXPORT  HalStartToRun
-        EXPORT  HalTaskSchedule
+        EXPORT  ArchTaskSchedule
         EXPORT  HalPendSV
         IMPORT  OsSchedTaskSwitch
         IMPORT  g_losTask
@@ -77,21 +77,21 @@ HalStartToRun
     BX      R6
 
 
-HalIntLock
+ArchIntLock
     MRS     R0, PRIMASK
     CPSID   I
     BX      LR
 
-HalIntUnLock
+ArchIntUnLock
     MRS     R0, PRIMASK
     CPSIE   I
     BX      LR
 
-HalIntRestore
+ArchIntRestore
     MSR     PRIMASK, R0
     BX      LR
 
-HalTaskSchedule
+ArchTaskSchedule
     LDR     R0, =OS_NVIC_INT_CTRL
     LDR     R1, =OS_NVIC_PENDSVSET
     STR     R1, [R0]

arch/arm/cortex-m3/keil/los_interrupt.c

@@ -47,7 +47,7 @@ UINT32 g_intCount = 0;
 #ifdef __ICCARM__
 #pragma location = ".data.vector"
 #elif defined(__CC_ARM) || defined(__GNUC__)
-#pragma data_alignment=0x100
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
 LITE_OS_SEC_VEC
 #endif
 /* *
@@ -56,7 +56,7 @@ LITE_OS_SEC_VEC
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -108,18 +108,86 @@ WEAK VOID SysTick_Handler(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -133,8 +201,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -168,13 +236,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
     g_intCount++;
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -194,7 +262,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -204,11 +272,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -229,13 +297,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
 
     LOS_IntRestore(intSave);
 
@@ -243,13 +311,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -257,7 +325,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
         return OS_ERRNO_HWI_NUM_INVALID;
     }
 
-    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+    HwiMask((IRQn_Type)hwiNum);
 
     intSave = LOS_IntLock();
 
@@ -378,6 +446,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -394,6 +463,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -443,7 +513,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcNvicDump();
     OsExcMemPoolCheckInfo();
@@ -483,7 +555,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************

arch/arm/cortex-m3/keil/los_timer.c

@@ -34,38 +34,40 @@
 #include "ARMCM3.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -74,7 +76,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -83,7 +85,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle = 0;
     UINT32 intSave = LOS_IntLock();
@@ -96,17 +98,22 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m33/gcc/NTZ/BUILD.gn

@@ -38,6 +38,7 @@ kernel_module(module_name) {
     "los_interrupt.c",
     "los_timer.c",
   ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
 }
 
 config("public") {

arch/arm/cortex-m33/gcc/NTZ/los_arch_atomic.h

@@ -40,12 +40,92 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    __asm__ __volatile__("ldrex %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%1]\n"
+                             "strex %0, %2, [%1]\n"
+                             : "=&r"(status)
+                             : "r"(v), "r"(setVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "add %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "sub %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
@@ -57,14 +137,14 @@ extern "C" {
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "strex   %1, %4, [%3]"
+        __asm__ __volatile__("ldrex %0, [%3]\n"
+                             "strex %1, %4, [%3]"
                              : "=&r"(prevVal), "=&r"(status), "+m"(*v)
                              : "r"(v), "r"(val)
                              : "cc");
@@ -73,42 +153,6 @@ STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -128,18 +172,18 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("1: ldrex %0, %2\n"
-                             "    mov %1, #0\n"
-                             "    cmp %0, %3\n"
-                             "    bne 2f\n"
-                             "    strex %1, %4, %2\n"
-                             "2:"
+        __asm__ __volatile__("ldrex %0, %2\n"
+                             "mov %1, #0\n"
+                             "cmp %0, %3\n"
+                             "bne 1f\n"
+                             "strex %1, %4, %2\n"
+                             "1:"
                              : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
                              : "r"(oldVal), "r"(val)
                              : "cc");
@@ -148,6 +192,101 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
     return prevVal != oldVal;
 }
 
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m33/gcc/NTZ/los_arch_interrupt.h

@@ -109,7 +109,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -159,7 +160,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -169,7 +171,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -309,7 +312,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -342,25 +345,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_arch_interrupt
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_arch_interrupt
  * @brief: Default vector handling function.
@@ -528,7 +512,6 @@ VOID HalExcUsageFault(VOID);
 VOID HalSVCHandler(VOID);
 VOID HalHwiInit(VOID);
 
-
 /**
  * @ingroup los_exc
  * Cortex-M exception types: An error occurred while the bus status register was being pushed.
@@ -665,15 +648,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m33/gcc/NTZ/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m33/gcc/NTZ/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,19 +73,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -146,14 +129,29 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+#if (LOSCFG_KERNEL_SIGNAL == 1)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    UNUSED(stackTop);
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+#endif
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m33/gcc/NTZ/los_dispatch.S

@@ -47,6 +47,15 @@
     .section .text
     .thumb
 
+.macro SIGNAL_CONTEXT_RESTORE
+    push    {r12, lr}
+    blx     OsSignalTaskContextRestore
+    pop     {r12, lr}
+    cmp     r0, #0
+    mov     r1, r0
+    bne     SignalContextRestore
+.endm
+
     .type HalStartToRun, %function
     .global HalStartToRun
 HalStartToRun:
@@ -90,13 +99,11 @@ __DisabledFPU:
     MOV     lr, r5
     cpsie   I
     BX      r6
-
     .fnend
 
-
-    .type HalIntLock, %function
-    .global HalIntLock
-HalIntLock:
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
     .fnstart
     .cantunwind
 
@@ -105,9 +112,9 @@ HalIntLock:
     BX LR
     .fnend
 
-    .type HalIntUnLock, %function
-    .global HalIntUnLock
-HalIntUnLock:
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
     .fnstart
     .cantunwind
 
@@ -116,9 +123,9 @@ HalIntUnLock:
     BX LR
     .fnend
 
-    .type HalIntRestore, %function
-    .global HalIntRestore
-HalIntRestore:
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
     .fnstart
     .cantunwind
 
@@ -126,9 +133,9 @@ HalIntRestore:
     BX LR
     .fnend
 
-    .type HalTaskSchedule, %function
-    .global HalTaskSchedule
-HalTaskSchedule:
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
     .fnstart
     .cantunwind
 
@@ -140,9 +147,6 @@ HalTaskSchedule:
     bx      lr
    .fnend
 
-
-
-
     .type HalPendSV, %function
     .global HalPendSV
 HalPendSV:
@@ -153,6 +157,8 @@ HalPendSV:
     cpsid   I
 
 HalTaskSwitch:
+    SIGNAL_CONTEXT_RESTORE
+
     push    {r12, lr}
     blx     OsSchedTaskSwitch
     pop     {r12, lr}
@@ -182,9 +188,11 @@ __DisabledFPU1:
 
     ldr     r0, [r5, #4]
     str     r0, [r5]
-
     ldr     r1,   [r0]
 
+SignalContextRestore:
+    ldr.w   r3, =OS_FPU_CPACR
+    ldr     r3, [r3]
     and     r3, r3, #OS_FPU_CPACR_ENABLE
     cmp     r3, #OS_FPU_CPACR_ENABLE
     bne     __DisabledFPU2
@@ -193,9 +201,7 @@ __DisabledFPU1:
 __DisabledFPU2:
     ldmfd   r1!, {r4-r12}
     msr     psp,  r1
-
     msr     PRIMASK, r12
-
-
     bx      lr
+
     .fnend

arch/arm/cortex-m33/gcc/NTZ/los_interrupt.c

@@ -40,6 +40,7 @@
 #include "los_memory.h"
 #include "los_membox.h"
 
+#define DEF_HANDLER_START_INDEX 2
 /*lint -save -e40 -e522 -e533*/
 UINT32 g_intCount = 0;
 
@@ -49,9 +50,9 @@ UINT32 g_intCount = 0;
  * @ingroup los_hwi
  * Hardware interrupt form mapping handling function array.
  */
-STATIC HWI_PROC_FUNC __attribute__((aligned(0x100))) g_hwiForm[OS_VECTOR_CNT] = {0};
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -98,18 +99,86 @@ VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
 #endif
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -123,8 +192,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -158,13 +227,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
     g_intCount++;
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -184,7 +253,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -194,11 +263,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -219,13 +288,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
 
     LOS_IntRestore(intSave);
 
@@ -233,13 +302,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -247,7 +316,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
         return OS_ERRNO_HWI_NUM_INVALID;
     }
 
-    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+    HwiMask((IRQn_Type)hwiNum);
 
     intSave = LOS_IntLock();
 
@@ -368,6 +437,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -384,6 +454,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -433,7 +504,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcNvicDump();
     OsExcMemPoolCheckInfo();
@@ -473,7 +546,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************
@@ -489,7 +562,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
     UINT32 index;
     g_hwiForm[0] = 0;             /* [0] Top of Stack */
     g_hwiForm[1] = 0; /* [1] reset */
-    for (index = 2; index < OS_VECTOR_CNT; index++) {
+    for (index = DEF_HANDLER_START_INDEX; index < OS_VECTOR_CNT; index++) {
         g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
     }
     /* Exception handler register */

arch/arm/cortex-m33/gcc/NTZ/los_timer.c

@@ -33,38 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,7 +84,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle = 0;
     UINT32 intSave = LOS_IntLock();
@@ -95,17 +97,22 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m33/gcc/TZ/BUILD.gn

@@ -39,6 +39,7 @@ kernel_module(module_name) {
     "non_secure/los_timer.c",
     "non_secure/los_trustzone.c",
   ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
 
   include_dirs = [
     "non_secure",

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_atomic.h

@@ -40,12 +40,92 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    __asm__ __volatile__("ldrex %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%1]\n"
+                             "strex %0, %2, [%1]\n"
+                             : "=&r"(status)
+                             : "r"(v), "r"(setVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "add %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "sub %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
@@ -57,14 +137,14 @@ extern "C" {
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "strex   %1, %4, [%3]"
+        __asm__ __volatile__("ldrex %0, [%3]\n"
+                             "strex %1, %4, [%3]"
                              : "=&r"(prevVal), "=&r"(status), "+m"(*v)
                              : "r"(v), "r"(val)
                              : "cc");
@@ -73,42 +153,6 @@ STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -128,18 +172,18 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("1: ldrex %0, %2\n"
-                             "    mov %1, #0\n"
-                             "    cmp %0, %3\n"
-                             "    bne 2f\n"
-                             "    strex %1, %4, %2\n"
-                             "2:"
+        __asm__ __volatile__("ldrex %0, %2\n"
+                             "mov %1, #0\n"
+                             "cmp %0, %3\n"
+                             "bne 1f\n"
+                             "strex %1, %4, %2\n"
+                             "1:"
                              : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
                              : "r"(oldVal), "r"(val)
                              : "cc");
@@ -148,6 +192,101 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
     return prevVal != oldVal;
 }
 
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_interrupt.h

@@ -109,7 +109,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -159,7 +160,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -169,7 +171,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -309,7 +312,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -342,25 +345,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_arch_interrupt
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_arch_interrupt
  * @brief: Default vector handling function.
@@ -528,7 +512,6 @@ VOID HalExcUsageFault(VOID);
 VOID HalSVCHandler(VOID);
 VOID HalHwiInit(VOID);
 
-
 /**
  * @ingroup los_exc
  * Cortex-M exception types: An error occurred while the bus status register was being pushed.
@@ -665,15 +648,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m33/gcc/TZ/non_secure/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,19 +73,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -150,14 +133,28 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->stackLimit = (UINT32)stackTop;
+    context->excReturn = 0xFFFFFFBC;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m33/gcc/TZ/non_secure/los_dispatch.S

@@ -45,6 +45,15 @@
     .section .text
     .thumb
 
+.macro SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+.endm
+
     .type HalStartFirstTask, %function
     .global HalStartFirstTask
 HalStartFirstTask:
@@ -76,9 +85,9 @@ __DisabledFPU1:
     CPSIE   I
     BX      R3
 
-    .type HalIntLock, %function
-    .global HalIntLock
-HalIntLock:
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
     .fnstart
     .cantunwind
 
@@ -87,9 +96,9 @@ HalIntLock:
     BX LR
     .fnend
 
-    .type HalIntUnLock, %function
-    .global HalIntUnLock
-HalIntUnLock:
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
     .fnstart
     .cantunwind
 
@@ -98,9 +107,9 @@ HalIntUnLock:
     BX LR
     .fnend
 
-    .type HalIntRestore, %function
-    .global HalIntRestore
-HalIntRestore:
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
     .fnstart
     .cantunwind
 
@@ -108,9 +117,9 @@ HalIntRestore:
     BX LR
     .fnend
 
-    .type HalTaskSchedule, %function
-    .global HalTaskSchedule
-HalTaskSchedule:
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
     .fnstart
     .cantunwind
 
@@ -132,6 +141,8 @@ HalPendSV:
     cpsid   I
 
 HalTaskSwitch:
+    SIGNAL_CONTEXT_RESTORE
+
     push    {r12, lr}
     blx     OsSchedTaskSwitch
     pop     {r12, lr}
@@ -175,8 +186,9 @@ __DisabledFPU2:
 
     LDR     R0, [R5, #4]
     STR     R0, [R5]
-
     LDR     R1, [R0]
+
+SignalContextRestore:
     LDMIA   R1!, {R0, R2-R3}                  /* Restore secureContext, PSPLIM and LR from the current task stack. */
     MSR     PSPLIM, R2
     MOV     LR, R3
@@ -205,7 +217,7 @@ __DisabledFPU3:
     .fnend
 
     .type HalSVCStartSchedule, %function
-    .global HalSVCStartSchedule    
+    .global HalSVCStartSchedule
 HalSVCStartSchedule:
     .fnstart
     .cantunwind
@@ -219,7 +231,7 @@ HalSVCStartSchedule:
     .fnend
 
     .type HalSVCSecureContextAlloc, %function
-    .global HalSVCSecureContextAlloc  
+    .global HalSVCSecureContextAlloc
 HalSVCSecureContextAlloc:
     .fnstart
     .cantunwind
@@ -228,7 +240,7 @@ HalSVCSecureContextAlloc:
     .fnend
 
     .type HalSVCSecureContextFree, %function
-    .global HalSVCSecureContextFree  
+    .global HalSVCSecureContextFree
 HalSVCSecureContextFree:
     .fnstart
     .cantunwind
@@ -237,7 +249,7 @@ HalSVCSecureContextFree:
     .fnend
 
     .type HalSVCHandler, %function
-    .global HalSVCHandler  
+    .global HalSVCHandler
 HalSVCHandler:
     .fnstart
     .cantunwind

arch/arm/cortex-m33/gcc/TZ/non_secure/los_interrupt.c

@@ -40,6 +40,7 @@
 #include "los_memory.h"
 #include "los_membox.h"
 
+#define DEF_HANDLER_START_INDEX 2
 /*lint -save -e40 -e522 -e533*/
 UINT32 g_intCount = 0;
 
@@ -49,9 +50,9 @@ UINT32 g_intCount = 0;
  * @ingroup los_hwi
  * Hardware interrupt form mapping handling function array.
  */
-STATIC HWI_PROC_FUNC __attribute__((aligned(0x100))) g_hwiForm[OS_VECTOR_CNT] = {0};
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -98,18 +99,86 @@ VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
 #endif
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -123,8 +192,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -158,13 +227,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
     g_intCount++;
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -184,7 +253,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -194,11 +263,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -219,13 +288,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
 
     LOS_IntRestore(intSave);
 
@@ -233,13 +302,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -368,6 +437,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -384,6 +454,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -433,7 +504,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcNvicDump();
     OsExcMemPoolCheckInfo();
@@ -473,7 +546,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************
@@ -487,9 +560,9 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
 {
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;
-    g_hwiForm[0] = 0;             /* [0] Top of Stack */
+    g_hwiForm[0] = 0; /* [0] Top of Stack */
     g_hwiForm[1] = 0; /* [1] reset */
-    for (index = 2; index < OS_VECTOR_CNT; index++) {
+    for (index = DEF_HANDLER_START_INDEX; index < OS_VECTOR_CNT; index++) {
         g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
     }
     /* Exception handler register */

arch/arm/cortex-m33/gcc/TZ/non_secure/los_timer.c

@@ -33,38 +33,39 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
-#include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(g_cyclesPerTick);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +74,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,7 +83,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle = 0；
     UINT32 intSave = LOS_IntLock();
@@ -95,17 +96,22 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m33/iar/NTZ/los_arch_atomic.h

@@ -29,8 +29,8 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef LOS_ATOMIC_H
-#define LOS_ATOMIC_H
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
 
 #include "los_compiler.h"
 
@@ -40,77 +40,121 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    asm volatile("ldrex %0, [%1]\n"
+                 : "=&r"(val)
+                 : "r"(v)
+                 : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %0, [%1]\n"
+                     "strex %0, %2, [%1]\n"
+                     : "=&r"(status)
+                     : "r"(v), "r"(setVal)
+                     : "cc");
+    } while (status != 0);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "add %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(addVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "sub %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(subVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
- * @ingroup  los_atomic
+ * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
  * @param  v       [IN] The variable pointer.
- * @param  val       [IN] The exchange value.
+ * @param  val     [IN] The exchange value.
  *
  * @retval #INT32       The previous value of the atomic variable
  * @par Dependency:
- * <ul><li>los_atomic.h: the header file that contains the API declaration.</li></ul>
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "strex   %1, %4, [%3]"
-                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
-                             : "r"(v), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+        asm volatile("ldrex %0, [%2]\n"
+                     "strex %1, %3, [%2]"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(val)
+                     : "cc");
+    } while (status != 0);
 
     return prevVal;
 }
 
 /**
- * @ingroup  los_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
-/**
- * @ingroup  los_atomic
+ * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
  *
  * @par Description:
@@ -120,30 +164,125 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  *
  * @param  v       [IN] The variable pointer.
  * @param  val     [IN] The new value.
- * @param  oldVal      [IN] The old value.
+ * @param  oldVal  [IN] The old value.
  *
  * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
  * @retval FALSE The previous value of the atomic variable is equal to oldVal.
  * @par Dependency:
- * <ul><li>los_atomic.h: the header file that contains the API declaration.</li></ul>
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("1: ldrex %0, %2\n"
-                             "    mov %1, #0\n"
-                             "    cmp %0, %3\n"
-                             "    bne 2f\n"
-                             "    strex %1, %4, %2\n"
-                             "2:"
-                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
-                             : "r"(oldVal), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+        asm volatile("ldrex %0, [%2]\n"
+                     "mov %1, #0\n"
+                     "cmp %0, %3\n"
+                     "bne 1f\n"
+                     "strex %1, %4, [%2]\n"
+                     "1:"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(oldVal), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
 
     return prevVal != oldVal;
 }
@@ -154,5 +293,4 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-#endif /* LOS_ATOMIC_H */
-
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/arm/cortex-m33/iar/NTZ/los_arch_interrupt.h

@@ -109,7 +109,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -159,7 +160,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -169,7 +171,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -309,7 +312,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_hwi
  * Set interrupt vector table.
@@ -342,25 +345,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_hwi
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_hwi
  * @brief: Default vector handling function.
@@ -529,7 +513,6 @@ VOID HalExcUsageFault(VOID);
 VOID HalSVCHandler(VOID);
 VOID HalHwiInit(VOID);
 
-
 /**
  * @ingroup los_exc
  * Cortex-M exception types: An error occurred while the bus status register was being pushed.
@@ -666,15 +649,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m33/iar/NTZ/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m33/iar/NTZ/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,19 +73,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -146,14 +129,27 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    UNUSED(stackTop);
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m33/iar/NTZ/los_dispatch.S

@@ -31,13 +31,14 @@
 
     PRESERVE8
 
-    EXPORT  HalIntLock
-    EXPORT  HalIntUnLock
-    EXPORT  HalIntRestore
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
     EXPORT  HalStartToRun
-    EXPORT  HalTaskSchedule
+    EXPORT  ArchTaskSchedule
     EXPORT  HalPendSV
     IMPORT  OsSchedTaskSwitch
+    IMPORT  OsSignalTaskContextRestore
     IMPORT  g_losTask
 
 OS_FPU_CPACR                EQU     0xE000ED88
@@ -52,6 +53,15 @@ OS_TASK_STATUS_RUNNING      EQU     0x0010
     THUMB
     REQUIRE8
 
+    MACRO SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+    ENDM
+
 HalStartToRun
     LDR     R4, =OS_NVIC_SYSPRI2
     LDR     R5, =OS_NVIC_PENDSV_PRI
@@ -90,21 +100,21 @@ __DisabledFPU
     BX      R6
 
 
-HalIntLock
+ArchIntLock
     MRS     R0, PRIMASK
     CPSID   I
     BX      LR
 
-HalIntUnLock
+ArchIntUnLock
     MRS     R0, PRIMASK
     CPSIE   I
     BX      LR
 
-HalIntRestore
+ArchIntRestore
     MSR     PRIMASK, R0
     BX      LR
 
-HalTaskSchedule
+ArchTaskSchedule
     LDR     R0, =OS_NVIC_INT_CTRL
     LDR     R1, =OS_NVIC_PENDSVSET
     STR     R1, [R0]
@@ -145,8 +155,11 @@ __DisabledFPU1
 
     LDR     R0, [R5, #4]
     STR     R0, [R5]
-
     LDR     R1, [R0]
+
+SignalContextRestore
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
     AND     R3, R3, #OS_FPU_CPACR_ENABLE
     CMP     R3, #OS_FPU_CPACR_ENABLE
     BNE     __DisabledFPU2

arch/arm/cortex-m33/iar/NTZ/los_interrupt.c

@@ -46,14 +46,14 @@ UINT32 g_intCount = 0;
 
 /*lint -restore*/
 #pragma location = ".data.vector"
-#pragma data_alignment=0x100
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
 /* *
  * @ingroup los_hwi
  * hardware interrupt form mapping handling function array.
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -105,18 +105,86 @@ WEAK VOID SysTick_Handler(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -130,8 +198,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -167,13 +235,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -193,7 +261,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -203,11 +271,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINTPTR intSave;
 
@@ -228,13 +296,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
 
     LOS_IntRestore(intSave);
 
@@ -242,13 +310,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -376,6 +444,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -392,6 +461,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -441,7 +511,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcNvicDump();
     OsExcMemPoolCheckInfo();
@@ -481,7 +553,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************

arch/arm/cortex-m33/iar/NTZ/los_timer.c

@@ -33,38 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,7 +84,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle = 0;
     UINTPTR intSave = LOS_IntLock();
@@ -95,17 +97,22 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_atomic.h

@@ -29,8 +29,8 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef LOS_ATOMIC_H
-#define LOS_ATOMIC_H
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
 
 #include "los_compiler.h"
 
@@ -40,77 +40,121 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    asm volatile("ldrex %0, [%1]\n"
+                 : "=&r"(val)
+                 : "r"(v)
+                 : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %0, [%1]\n"
+                     "strex %0, %2, [%1]\n"
+                     : "=&r"(status)
+                     : "r"(v), "r"(setVal)
+                     : "cc");
+    } while (status != 0);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "add %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(addVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "sub %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(subVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
- * @ingroup  los_atomic
+ * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
  * @param  v       [IN] The variable pointer.
- * @param  val       [IN] The exchange value.
+ * @param  val     [IN] The exchange value.
  *
  * @retval #INT32       The previous value of the atomic variable
  * @par Dependency:
- * <ul><li>los_atomic.h: the header file that contains the API declaration.</li></ul>
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "strex   %1, %4, [%3]"
-                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
-                             : "r"(v), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+        asm volatile("ldrex %0, [%2]\n"
+                     "strex %1, %3, [%2]"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(val)
+                     : "cc");
+    } while (status != 0);
 
     return prevVal;
 }
 
 /**
- * @ingroup  los_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
-/**
- * @ingroup  los_atomic
+ * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
  *
  * @par Description:
@@ -120,30 +164,125 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  *
  * @param  v       [IN] The variable pointer.
  * @param  val     [IN] The new value.
- * @param  oldVal      [IN] The old value.
+ * @param  oldVal  [IN] The old value.
  *
  * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
  * @retval FALSE The previous value of the atomic variable is equal to oldVal.
  * @par Dependency:
- * <ul><li>los_atomic.h: the header file that contains the API declaration.</li></ul>
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("1: ldrex %0, %2\n"
-                             "    mov %1, #0\n"
-                             "    cmp %0, %3\n"
-                             "    bne 2f\n"
-                             "    strex %1, %4, %2\n"
-                             "2:"
-                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
-                             : "r"(oldVal), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+        asm volatile("ldrex %0, [%2]\n"
+                     "mov %1, #0\n"
+                     "cmp %0, %3\n"
+                     "bne 1f\n"
+                     "strex %1, %4, [%2]\n"
+                     "1:"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(oldVal), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
 
     return prevVal != oldVal;
 }
@@ -154,5 +293,4 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-#endif /* LOS_ATOMIC_H */
-
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_interrupt.h

@@ -109,7 +109,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -159,7 +160,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -169,7 +171,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -309,7 +312,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_hwi
  * Set interrupt vector table.
@@ -342,25 +345,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_hwi
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_hwi
  * @brief: Default vector handling function.
@@ -529,7 +513,6 @@ VOID HalExcUsageFault(VOID);
 VOID HalSVCHandler(VOID);
 VOID HalHwiInit(VOID);
 
-
 /**
  * @ingroup los_exc
  * Cortex-M exception types: An error occurred while the bus status register was being pushed.
@@ -666,15 +649,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m33/iar/TZ/non_secure/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,19 +73,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -150,14 +133,28 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->stackLimit = (UINT32)stackTop;
+    context->excReturn = 0xFFFFFFBC;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m33/iar/TZ/non_secure/los_dispatch.S

@@ -31,17 +31,17 @@
 
     PRESERVE8
 
-    EXPORT  HalIntLock
-    EXPORT  HalIntUnLock
-    EXPORT  HalIntRestore
-    EXPORT  HalTaskSchedule
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
+    EXPORT  ArchTaskSchedule
     EXPORT  HalPendSV
     EXPORT  HalSVCHandler
     EXPORT  HalStartFirstTask
     EXPORT  HalSVCStartSchedule
     EXPORT  HalSVCSecureContextAlloc
     EXPORT  HalSVCSecureContextFree
-
+    IMPORT  OsSignalTaskContextRestore
     IMPORT  OsSchedTaskSwitch
     IMPORT  g_losTask
 
@@ -62,6 +62,15 @@ OS_TASK_STATUS_RUNNING      EQU     0x0010
     THUMB
     REQUIRE8
 
+    MACRO SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+    ENDM
+
 HalStartFirstTask
     MOV     R0, #2
     MSR     CONTROL, R0
@@ -91,21 +100,21 @@ __DisabledFPU1
     CPSIE   I
     BX      R3
 
-HalIntLock
+ArchIntLock
     MRS     R0, PRIMASK
     CPSID   I
     BX      LR
 
-HalIntUnLock
+ArchIntUnLock
     MRS     R0, PRIMASK
     CPSIE   I
     BX      LR
 
-HalIntRestore
+ArchIntRestore
     MSR     PRIMASK, R0
     BX      LR
 
-HalTaskSchedule
+ArchTaskSchedule
     LDR     R0, =OS_NVIC_INT_CTRL
     LDR     R1, =OS_NVIC_PENDSVSET
     STR     R1, [R0]
@@ -118,6 +127,8 @@ HalPendSV
     CPSID   I
 
 HalTaskSwitch
+    SIGNAL_CONTEXT_RESTORE
+
     PUSH    {R12, LR}
     BLX     OsSchedTaskSwitch
     POP     {R12, LR}
@@ -161,8 +172,9 @@ __DisabledFPU2
 
     LDR     R0, [R5, #4]
     STR     R0, [R5]
-
     LDR     R1, [R0]
+
+SignalContextRestore
     LDMIA   R1!, {R0, R2-R3}                  /* Restore secureContext, PSPLIM and LR from the current task stack. */
     MSR     PSPLIM, R2
     MOV     LR, R3

arch/arm/cortex-m33/iar/TZ/non_secure/los_interrupt.c

@@ -46,14 +46,14 @@ UINT32 g_intCount = 0;
 
 /*lint -restore*/
 #pragma location = ".data.vector"
-#pragma data_alignment=0x100
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
 /* *
  * @ingroup los_hwi
  * hardware interrupt form mapping handling function array.
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -105,18 +105,86 @@ WEAK VOID SysTick_Handler(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -130,8 +198,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -167,13 +235,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -193,7 +261,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -203,11 +271,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINTPTR intSave;
 
@@ -228,13 +296,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
 
     LOS_IntRestore(intSave);
 
@@ -242,13 +310,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -376,6 +444,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -392,6 +461,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -441,7 +511,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcNvicDump();
     OsExcMemPoolCheckInfo();
@@ -481,7 +553,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************

arch/arm/cortex-m33/iar/TZ/non_secure/los_timer.c

@@ -33,38 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,7 +84,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle = 0;
     UINTPTR intSave = LOS_IntLock();
@@ -95,17 +97,22 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m4/gcc/BUILD.gn

@@ -39,6 +39,7 @@ kernel_module(module_name) {
     "los_mpu.c",
     "los_timer.c",
   ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
 }
 
 config("public") {

arch/arm/cortex-m4/gcc/los_arch_atomic.h

@@ -40,12 +40,92 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    __asm__ __volatile__("ldrex %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%1]\n"
+                             "strex %0, %2, [%1]\n"
+                             : "=&r"(status)
+                             : "r"(v), "r"(setVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "add %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "sub %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
@@ -57,14 +137,14 @@ extern "C" {
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "strex   %1, %4, [%3]"
+        __asm__ __volatile__("ldrex %0, [%3]\n"
+                             "strex %1, %4, [%3]"
                              : "=&r"(prevVal), "=&r"(status), "+m"(*v)
                              : "r"(v), "r"(val)
                              : "cc");
@@ -73,42 +153,6 @@ STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -128,18 +172,18 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("1: ldrex %0, %2\n"
-                             "    mov %1, #0\n"
-                             "    cmp %0, %3\n"
-                             "    bne 2f\n"
-                             "    strex %1, %4, %2\n"
-                             "2:"
+        __asm__ __volatile__("ldrex %0, %2\n"
+                             "mov %1, #0\n"
+                             "cmp %0, %3\n"
+                             "bne 1f\n"
+                             "strex %1, %4, %2\n"
+                             "1:"
                              : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
                              : "r"(oldVal), "r"(val)
                              : "cc");
@@ -148,6 +192,101 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
     return prevVal != oldVal;
 }
 
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m4/gcc/los_arch_interrupt.h

@@ -109,7 +109,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -159,7 +160,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M4 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -169,7 +171,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -309,7 +312,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -342,25 +345,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_arch_interrupt
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_arch_interrupt
  * @brief: Default vector handling function.
@@ -528,7 +512,6 @@ VOID HalExcUsageFault(VOID);
 VOID HalExcSvcCall(VOID);
 VOID HalHwiInit(VOID);
 
-
 /**
  * @ingroup los_exc
  * Cortex-M exception types: An error occurred while the bus status register was being pushed.
@@ -665,15 +648,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m4/gcc/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m4/gcc/los_context.c

@@ -36,37 +36,27 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
-#include "los_timer.h"
-#include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
-
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -74,7 +64,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -82,19 +72,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -148,14 +128,27 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    UNUSED(stackTop);
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m4/gcc/los_dispatch.S

@@ -44,6 +44,15 @@
     .section .text
     .thumb
 
+.macro SIGNAL_CONTEXT_RESTORE
+    push    {r12, lr}
+    blx     OsSignalTaskContextRestore
+    pop     {r12, lr}
+    cmp     r0, #0
+    mov     r1, r0
+    bne     SignalContextRestore
+.endm
+
     .type HalStartToRun, %function
     .global HalStartToRun
 HalStartToRun:
@@ -88,10 +97,9 @@ __DisabledFPU:
 
     .fnend
 
-
-    .type HalIntLock, %function
-    .global HalIntLock
-HalIntLock:
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
     .fnstart
     .cantunwind
 
@@ -100,9 +108,9 @@ HalIntLock:
     BX LR
     .fnend
 
-    .type HalIntUnLock, %function
-    .global HalIntUnLock
-HalIntUnLock:
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
     .fnstart
     .cantunwind
 
@@ -111,9 +119,9 @@ HalIntUnLock:
     BX LR
     .fnend
 
-    .type HalIntRestore, %function
-    .global HalIntRestore
-HalIntRestore:
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
     .fnstart
     .cantunwind
 
@@ -121,9 +129,9 @@ HalIntRestore:
     BX LR
     .fnend
 
-    .type HalTaskSchedule, %function
-    .global HalTaskSchedule
-HalTaskSchedule:
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
     .fnstart
     .cantunwind
 
@@ -135,9 +143,6 @@ HalTaskSchedule:
     isb
    .fnend
 
-
-
-
     .type HalPendSV, %function
     .global HalPendSV
 HalPendSV:
@@ -148,6 +153,8 @@ HalPendSV:
     cpsid   I
 
 HalTaskSwitch:
+    SIGNAL_CONTEXT_RESTORE
+
     push    {r12, lr}
     blx     OsSchedTaskSwitch
     pop     {r12, lr}
@@ -176,8 +183,11 @@ __DisabledFPU1:
 
     ldr     r0, [r5, #4]
     str     r0, [r5]
-
     ldr     r1, [r0]
+
+SignalContextRestore:
+    ldr.w   r3, =OS_FPU_CPACR
+    ldr     r3, [r3]
     and     r3, r3, #OS_FPU_CPACR_ENABLE
     cmp     r3, #OS_FPU_CPACR_ENABLE
     bne     __DisabledFPU2

arch/arm/cortex-m4/gcc/los_interrupt.c

@@ -44,19 +44,14 @@
 UINT32 g_intCount = 0;
 
 /*lint -restore*/
-#ifdef __ICCARM__
-#pragma location = ".data.vector"
-#pragma data_alignment=0x100
-#elif defined(__CC_ARM) || defined(__GNUC__)
-LITE_OS_SEC_VEC
-#endif
+
 /* *
  * @ingroup los_hwi
  * Hardware interrupt form mapping handling function array.
  */
-STATIC HWI_PROC_FUNC __attribute__((aligned(0x100))) g_hwiForm[OS_VECTOR_CNT] = {0};
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -108,18 +103,86 @@ WEAK VOID SysTick_Handler(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -133,8 +196,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -168,13 +231,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
     g_intCount++;
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -194,7 +257,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -204,11 +267,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -229,13 +292,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
 
     LOS_IntRestore(intSave);
 
@@ -243,13 +306,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -257,7 +320,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
         return OS_ERRNO_HWI_NUM_INVALID;
     }
 
-    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+    HwiMask((IRQn_Type)hwiNum);
 
     intSave = LOS_IntLock();
 
@@ -378,6 +441,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -394,6 +458,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -443,7 +508,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcNvicDump();
     OsExcMemPoolCheckInfo();
@@ -483,7 +550,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* stack protector */

arch/arm/cortex-m4/gcc/los_mpu.c

@@ -49,22 +49,22 @@ typedef enum {
     MPU_AP_RO_USER_RO = 0x6,         /* Privileged:Read-only      Unprivileged:Read-only */
 } MpuApConfig;
 
-VOID HalMpuEnable(UINT32 defaultRegionEnable)
+VOID ArchMpuEnable(UINT32 defaultRegionEnable)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = (MPU_CTRL_ENABLE_Msk | ((defaultRegionEnable << MPU_CTRL_PRIVDEFENA_Pos) & MPU_CTRL_PRIVDEFENA_Msk));
     SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
-VOID HalMpuDisable(VOID)
+VOID ArchMpuDisable(VOID)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = 0;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
 
 STATIC VOID HalMpuRASRAddMemAttr(MPU_CFG_PARA *para, UINT32 *RASR)
@@ -147,7 +147,7 @@ STATIC UINT32 HalMpuGetRASR(UINT32 encodeSize, MPU_CFG_PARA *para)
     return RASR;
 }
 
-UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
+UINT32 ArchMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
 {
     UINT32 RASR;
     UINT32 RBAR;
@@ -175,9 +175,9 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     }
     RBAR = para->baseAddr & MPU_RBAR_ADDR_Msk;
     RASR = HalMpuGetRASR(encodeSize, para);
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
     MPU->RNR = RNR;
@@ -186,11 +186,11 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     __DSB();
     __ISB();
     g_regionNumBeUsed[regionId] = 1; /* Set mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-UINT32 HalMpuDisableRegion(UINT32 regionId)
+UINT32 ArchMpuDisableRegion(UINT32 regionId)
 {
     volatile UINT32 type;
     UINT32 intSave;
@@ -199,9 +199,9 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         return LOS_NOK;
     }
 
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (!g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
 
@@ -213,20 +213,20 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         __ISB();
     }
     g_regionNumBeUsed[regionId] = 0; /* clear mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-INT32 HalMpuUnusedRegionGet(VOID)
+INT32 ArchMpuUnusedRegionGet(VOID)
 {
     INT32 id;
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     for (id = 0; id < MPU_MAX_REGION_NUM; id++) {
         if (!g_regionNumBeUsed[id]) {
             break;
         }
     }
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 
     if (id == MPU_MAX_REGION_NUM) {
         return -1;

arch/arm/cortex-m4/gcc/los_timer.c

@@ -33,39 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -74,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -83,7 +84,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle = 0;
     UINT32 intSave = LOS_IntLock();
@@ -96,17 +97,22 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m4/iar/los_arch_atomic.h

@@ -40,12 +40,92 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    asm volatile("ldrex %0, [%1]\n"
+                 : "=&r"(val)
+                 : "r"(v)
+                 : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    asm volatile("1:ldrex %0, [%1]\n"
+                 "  strex %0, %2, [%1]\n"
+                 "  teq %0, #0\n"
+                 "  bne 1b"
+                 : "=&r"(status)
+                 : "r"(v), "r"(setVal)
+                 : "cc");
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "add %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(addVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "sub %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(subVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
@@ -57,58 +137,22 @@ extern "C" {
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "strex   %1, %4, [%3]"
-                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
-                             : "r"(v), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+        asm volatile("ldrex %0, [%2]\n"
+                     "strex %1, %3, [%2]"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(val)
+                     : "cc");
+    } while (status != 0);
 
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -128,22 +172,117 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("1: ldrex %0, %2\n"
-                             "    mov %1, #0\n"
-                             "    cmp %0, %3\n"
-                             "    bne 2f\n"
-                             "    strex %1, %4, %2\n"
-                             "2:"
-                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
-                             : "r"(oldVal), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+        asm volatile("ldrex %0, [%2]\n"
+                     "mov %1, #0\n"
+                     "cmp %0, %3\n"
+                     "bne 1f\n"
+                     "strex %1, %4, [%2]\n"
+                     "1:"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(oldVal), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
 
     return prevVal != oldVal;
 }
@@ -155,4 +294,3 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
 #endif /* __cplusplus */
 
 #endif /* _LOS_ARCH_ATOMIC_H */
-

arch/arm/cortex-m4/iar/los_arch_interrupt.h

@@ -109,7 +109,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -159,7 +160,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M4 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -169,7 +171,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -309,7 +312,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -342,25 +345,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_arch_interrupt
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_arch_interrupt
  * @brief: Default vector handling function.
@@ -528,7 +512,6 @@ VOID HalExcUsageFault(VOID);
 VOID HalExcSvcCall(VOID);
 VOID HalHwiInit(VOID);
 
-
 /**
  * @ingroup los_exc
  * Cortex-M exception types: An error occurred while the bus status register was being pushed.
@@ -665,15 +648,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m4/iar/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m4/iar/los_context.c

@@ -36,38 +36,30 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_timer.h"
 #include "los_debug.h"
 
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-        return;
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -75,7 +67,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -83,19 +75,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -149,14 +131,27 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
-    context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
+    context->uwLR = (UINTPTR)ArchSysExit;
+    context->uwPC = (UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    UNUSED(stackTop);
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m4/iar/los_dispatch.S

@@ -31,13 +31,14 @@
 
     PRESERVE8
 
-    EXPORT  HalIntLock
-    EXPORT  HalIntUnLock
-    EXPORT  HalIntRestore
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
     EXPORT  HalStartToRun
-    EXPORT  HalTaskSchedule
+    EXPORT  ArchTaskSchedule
     EXPORT  HalPendSV
     IMPORT  OsSchedTaskSwitch
+    IMPORT  OsSignalTaskContextRestore
     IMPORT  g_losTask
 
 OS_FPU_CPACR                EQU     0xE000ED88
@@ -52,6 +53,15 @@ OS_TASK_STATUS_RUNNING      EQU     0x0010
     THUMB
     REQUIRE8
 
+    MACRO SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+    ENDM
+
 HalStartToRun
     LDR     R4, =OS_NVIC_SYSPRI2
     LDR     R5, =OS_NVIC_PENDSV_PRI
@@ -90,21 +100,21 @@ __DisabledFPU
     BX      R6
 
 
-HalIntLock
+ArchIntLock
     MRS     R0, PRIMASK
     CPSID   I
     BX      LR
 
-HalIntUnLock
+ArchIntUnLock
     MRS     R0, PRIMASK
     CPSIE   I
     BX      LR
 
-HalIntRestore
+ArchIntRestore
     MSR     PRIMASK, R0
     BX      LR
 
-HalTaskSchedule
+ArchTaskSchedule
     LDR     R0, =OS_NVIC_INT_CTRL
     LDR     R1, =OS_NVIC_PENDSVSET
     STR     R1, [R0]
@@ -117,6 +127,8 @@ HalPendSV
     CPSID   I
 
 HalTaskSwitch
+    SIGNAL_CONTEXT_RESTORE
+
     PUSH    {R12, LR}
     BLX     OsSchedTaskSwitch
     POP     {R12, LR}
@@ -128,8 +140,8 @@ HalTaskSwitch
 
 TaskContextSwitch
     MOV     LR, R0
-    MRS     R0, PSP
 
+    MRS     R0, PSP
     STMFD   R0!, {R4-R12}
     LDR.W   R3, =OS_FPU_CPACR
     LDR     R3, [R3]
@@ -145,8 +157,11 @@ __DisabledFPU1
 
     LDR     R0, [R5, #4]
     STR     R0, [R5]
-
     LDR     R1, [R0]
+
+SignalContextRestore
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
     AND     R3, R3, #OS_FPU_CPACR_ENABLE
     CMP     R3, #OS_FPU_CPACR_ENABLE
     BNE     __DisabledFPU2

arch/arm/cortex-m4/iar/los_interrupt.c

@@ -47,7 +47,7 @@ UINT32 g_intCount = 0;
 /*lint -restore*/
 #ifdef __ICCARM__
 #pragma location = ".data.vector"
-#pragma data_alignment=0x100
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
 #elif defined(__CC_ARM) || defined(__GNUC__)
 LITE_OS_SEC_VEC
 #endif
@@ -57,7 +57,7 @@ LITE_OS_SEC_VEC
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -109,18 +109,86 @@ WEAK VOID SysTick_Handler(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -134,8 +202,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -169,13 +237,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
     g_intCount++;
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -195,7 +263,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -205,11 +273,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -230,13 +298,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
 
     LOS_IntRestore(intSave);
 
@@ -244,13 +312,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -379,6 +447,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -395,6 +464,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -444,7 +514,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcNvicDump();
     OsExcMemPoolCheckInfo();
@@ -484,7 +556,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************

arch/arm/cortex-m4/iar/los_mpu.c

@@ -49,22 +49,22 @@ typedef enum {
     MPU_AP_RO_USER_RO = 0x6,         /* Privileged:Read-only      Unprivileged:Read-only */
 } MpuApConfig;
 
-VOID HalMpuEnable(UINT32 defaultRegionEnable)
+VOID ArchMpuEnable(UINT32 defaultRegionEnable)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = (MPU_CTRL_ENABLE_Msk | ((defaultRegionEnable << MPU_CTRL_PRIVDEFENA_Pos) & MPU_CTRL_PRIVDEFENA_Msk));
     SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
-VOID HalMpuDisable(VOID)
+VOID ArchMpuDisable(VOID)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = 0;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
 
 STATIC VOID HalMpuRASRAddMemAttr(MPU_CFG_PARA *para, UINT32 *RASR)
@@ -147,7 +147,7 @@ STATIC UINT32 HalMpuGetRASR(UINT32 encodeSize, MPU_CFG_PARA *para)
     return RASR;
 }
 
-UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
+UINT32 ArchMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
 {
     UINT32 RASR;
     UINT32 RBAR;
@@ -175,9 +175,9 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     }
     RBAR = para->baseAddr & MPU_RBAR_ADDR_Msk;
     RASR = HalMpuGetRASR(encodeSize, para);
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
     MPU->RNR = RNR;
@@ -186,11 +186,11 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     __DSB();
     __ISB();
     g_regionNumBeUsed[regionId] = 1; /* Set mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-UINT32 HalMpuDisableRegion(UINT32 regionId)
+UINT32 ArchMpuDisableRegion(UINT32 regionId)
 {
     volatile UINT32 type;
     UINT32 intSave;
@@ -199,9 +199,9 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         return LOS_NOK;
     }
 
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (!g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
 
@@ -213,20 +213,20 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         __ISB();
     }
     g_regionNumBeUsed[regionId] = 0; /* clear mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-INT32 HalMpuUnusedRegionGet(VOID)
+INT32 ArchMpuUnusedRegionGet(VOID)
 {
     INT32 id;
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     for (id = 0; id < MPU_MAX_REGION_NUM; id++) {
         if (!g_regionNumBeUsed[id]) {
             break;
         }
     }
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 
     if (id == MPU_MAX_REGION_NUM) {
         return -1;

arch/arm/cortex-m4/iar/los_timer.c

@@ -33,39 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -74,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -83,7 +84,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle = 0;
     UINT32 intSave = LOS_IntLock();
@@ -96,17 +97,22 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m7/gcc/BUILD.gn

@@ -39,6 +39,7 @@ kernel_module(module_name) {
     "los_mpu.c",
     "los_timer.c",
   ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
 }
 
 config("public") {

arch/arm/cortex-m7/gcc/los_arch_atomic.h

@@ -40,12 +40,92 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    __asm__ __volatile__("ldrex %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%1]\n"
+                             "strex %0, %2, [%1]\n"
+                             : "=&r"(status)
+                             : "r"(v), "r"(setVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "add %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %1, [%2]\n"
+                             "sub %1, %1, %3\n"
+                             "strex %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
@@ -57,14 +137,14 @@ extern "C" {
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "strex   %1, %4, [%3]"
+        __asm__ __volatile__("ldrex %0, [%3]\n"
+                             "strex %1, %4, [%3]"
                              : "=&r"(prevVal), "=&r"(status), "+m"(*v)
                              : "r"(v), "r"(val)
                              : "cc");
@@ -73,42 +153,6 @@ STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -128,18 +172,18 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("1: ldrex %0, %2\n"
-                             "    mov %1, #0\n"
-                             "    cmp %0, %3\n"
-                             "    bne 2f\n"
-                             "    strex %1, %4, %2\n"
-                             "2:"
+        __asm__ __volatile__("ldrex %0, %2\n"
+                             "mov %1, #0\n"
+                             "cmp %0, %3\n"
+                             "bne 1f\n"
+                             "strex %1, %4, %2\n"
+                             "1:"
                              : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
                              : "r"(oldVal), "r"(val)
                              : "cc");
@@ -148,6 +192,101 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
     return prevVal != oldVal;
 }
 
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
 #ifdef __cplusplus
 #if __cplusplus
 }
@@ -155,4 +294,3 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
 #endif /* __cplusplus */
 
 #endif /* _LOS_ARCH_ATOMIC_H */
-

arch/arm/cortex-m7/gcc/los_arch_interrupt.h

@@ -109,7 +109,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -159,7 +160,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M7 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -169,7 +171,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -309,7 +312,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -342,25 +345,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_arch_interrupt
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_arch_interrupt
  * @brief: Default vector handling function.
@@ -528,7 +512,6 @@ VOID HalExcUsageFault(VOID);
 VOID HalExcSvcCall(VOID);
 VOID HalHwiInit(VOID);
 
-
 /**
  * @ingroup los_exc
  * Cortex-M exception types: An error occurred while the bus status register was being pushed.
@@ -665,15 +648,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m7/gcc/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m7/gcc/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,19 +73,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -146,14 +129,27 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    UNUSED(stackTop);
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m7/gcc/los_dispatch.S

@@ -35,8 +35,6 @@
  .fpu fpv5-d16
 //;.arch_extension sec
 
-
-
 .equ    OS_NVIC_INT_CTRL,            0xE000ED04
 .equ    OS_NVIC_SYSPRI2,             0xE000ED20
 .equ    OS_NVIC_PENDSV_PRI,          0xF0F00000
@@ -46,6 +44,15 @@
     .section .text
     .thumb
 
+.macro SIGNAL_CONTEXT_RESTORE
+    push    {r12, lr}
+    blx     OsSignalTaskContextRestore
+    pop     {r12, lr}
+    cmp     r0, #0
+    mov     r1, r0
+    bne     SignalContextRestore
+.endm
+
     .type HalStartToRun, %function
     .global HalStartToRun
 HalStartToRun:
@@ -86,9 +93,9 @@ HalStartToRun:
     .fnend
 
 
-    .type HalIntLock, %function
-    .global HalIntLock
-HalIntLock:
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
     .fnstart
     .cantunwind
 
@@ -97,9 +104,9 @@ HalIntLock:
     BX LR
     .fnend
 
-    .type HalIntUnLock, %function
-    .global HalIntUnLock
-HalIntUnLock:
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
     .fnstart
     .cantunwind
 
@@ -108,9 +115,9 @@ HalIntUnLock:
     BX LR
     .fnend
 
-    .type HalIntRestore, %function
-    .global HalIntRestore
-HalIntRestore:
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
     .fnstart
     .cantunwind
 
@@ -118,9 +125,9 @@ HalIntRestore:
     BX LR
     .fnend
 
-    .type HalTaskSchedule, %function
-    .global HalTaskSchedule
-HalTaskSchedule:
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
     .fnstart
     .cantunwind
 
@@ -142,6 +149,8 @@ HalPendSV:
     cpsid   I
 
 HalTaskSwitch:
+    SIGNAL_CONTEXT_RESTORE
+
     push    {r12, lr}
     blx     OsSchedTaskSwitch
     pop     {r12, lr}
@@ -167,9 +176,9 @@ TaskContextSwitch:
 
     ldr     r0, [r5, #4]
     str     r0, [r5]
-
     ldr     r1, [r0]
 
+ SignalContextRestore:
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
     vldmia   r1!, {d8-d15}

arch/arm/cortex-m7/gcc/los_interrupt.c

@@ -49,9 +49,9 @@ UINT32 g_intCount = 0;
  * @ingroup los_hwi
  * Hardware interrupt form mapping handling function array.
  */
-STATIC HWI_PROC_FUNC __attribute__((aligned(0x100))) g_hwiForm[OS_VECTOR_CNT] = {0};
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -98,18 +98,86 @@ VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
 #endif
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -123,8 +191,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -158,13 +226,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
     g_intCount++;
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -184,7 +252,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -194,11 +262,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -219,13 +287,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
 
     LOS_IntRestore(intSave);
 
@@ -233,13 +301,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -368,6 +436,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -384,6 +453,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -433,7 +503,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcNvicDump();
     OsExcMemPoolCheckInfo();
@@ -473,7 +545,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************

arch/arm/cortex-m7/gcc/los_mpu.c

@@ -49,22 +49,22 @@ typedef enum {
     MPU_AP_RO_USER_RO = 0x6,         /* Privileged:Read-only      Unprivileged:Read-only */
 } MpuApConfig;
 
-VOID HalMpuEnable(UINT32 defaultRegionEnable)
+VOID ArchMpuEnable(UINT32 defaultRegionEnable)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = (MPU_CTRL_ENABLE_Msk | ((defaultRegionEnable << MPU_CTRL_PRIVDEFENA_Pos) & MPU_CTRL_PRIVDEFENA_Msk));
     SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
-VOID HalMpuDisable(VOID)
+VOID ArchMpuDisable(VOID)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = 0;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
 
 STATIC VOID HalMpuRASRAddMemAttr(MPU_CFG_PARA *para, UINT32 *RASR)
@@ -147,7 +147,7 @@ STATIC UINT32 HalMpuGetRASR(UINT32 encodeSize, MPU_CFG_PARA *para)
     return RASR;
 }
 
-UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
+UINT32 ArchMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
 {
     UINT32 RASR;
     UINT32 RBAR;
@@ -175,9 +175,9 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     }
     RBAR = para->baseAddr & MPU_RBAR_ADDR_Msk;
     RASR = HalMpuGetRASR(encodeSize, para);
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
     MPU->RNR = RNR;
@@ -186,11 +186,11 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     __DSB();
     __ISB();
     g_regionNumBeUsed[regionId] = 1; /* Set mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-UINT32 HalMpuDisableRegion(UINT32 regionId)
+UINT32 ArchMpuDisableRegion(UINT32 regionId)
 {
     volatile UINT32 type;
     UINT32 intSave;
@@ -199,9 +199,9 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         return LOS_NOK;
     }
 
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (!g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
 
@@ -213,20 +213,20 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         __ISB();
     }
     g_regionNumBeUsed[regionId] = 0; /* clear mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-INT32 HalMpuUnusedRegionGet(VOID)
+INT32 ArchMpuUnusedRegionGet(VOID)
 {
     INT32 id;
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     for (id = 0; id < MPU_MAX_REGION_NUM; id++) {
         if (!g_regionNumBeUsed[id]) {
             break;
         }
     }
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 
     if (id == MPU_MAX_REGION_NUM) {
         return -1;

arch/arm/cortex-m7/gcc/los_timer.c

@@ -33,38 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,7 +84,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle = 0;
     UINT32 intSave = LOS_IntLock();
@@ -95,17 +97,22 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m7/iar/los_arch_atomic.h

@@ -40,12 +40,92 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+
+    asm volatile("ldrex %0, [%1]\n"
+                 : "=&r"(val)
+                 : "r"(v)
+                 : "cc");
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %0, [%1]\n"
+                     "strex %0, %2, [%1]\n"
+                     : "=&r"(status)
+                     : "r"(v), "r"(setVal)
+                     : "cc");
+    } while (status != 0);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "add %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(addVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        asm volatile("ldrex %1, [%2]\n"
+                     "sub %1, %1, %3\n"
+                     "strex %0, %1, [%2]"
+                     : "=&r"(status), "=&r"(val)
+                     : "r"(v), "r"(subVal)
+                     : "cc");
+    } while (status != 0);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
@@ -57,58 +137,22 @@ extern "C" {
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "strex   %1, %4, [%3]"
-                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
-                             : "r"(v), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+        asm volatile("ldrex %0, [%2]\n"
+                     "strex %1, %3, [%2]"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(val)
+                     : "cc");
+    } while (status != 0);
 
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -128,22 +172,117 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
 
     do {
-        __asm__ __volatile__("1: ldrex %0, %2\n"
-                             "    mov %1, #0\n"
-                             "    cmp %0, %3\n"
-                             "    bne 2f\n"
-                             "    strex %1, %4, %2\n"
-                             "2:"
-                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
-                             : "r"(oldVal), "r"(val)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
+        asm volatile("ldrex %0, [%2]\n"
+                     "mov %1, #0\n"
+                     "cmp %0, %3\n"
+                     "bne 1f\n"
+                     "strex %1, %4, [%2]\n"
+                     "1:"
+                     : "=&r"(prevVal), "=&r"(status)
+                     : "r"(v), "r"(oldVal), "r"(val)
+                     : "cc");
+    } while (status != 0);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
 
     return prevVal != oldVal;
 }
@@ -155,4 +294,3 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
 #endif /* __cplusplus */
 
 #endif /* _LOS_ARCH_ATOMIC_H */
-

arch/arm/cortex-m7/iar/los_arch_interrupt.h

@@ -109,7 +109,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000900
  *
- * Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a Cortex-M7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
  */
 #define OS_ERRNO_HWI_NUM_INVALID              LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
 
@@ -159,7 +160,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000905
  *
- * Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a Cortex-M7 platform is [0,15].
  */
 #define OS_ERRNO_HWI_PRIO_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
 
@@ -169,7 +171,8 @@ extern UINT32 _BootVectors[];
  *
  * Value: 0x02000906
  *
- * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
  */
 #define OS_ERRNO_HWI_MODE_INVALID             LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
 
@@ -309,7 +312,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -342,25 +345,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_arch_interrupt
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_arch_interrupt
  * @brief: Default vector handling function.
@@ -528,7 +512,6 @@ VOID HalExcUsageFault(VOID);
 VOID HalExcSvcCall(VOID);
 VOID HalHwiInit(VOID);
 
-
 /**
  * @ingroup los_exc
  * Cortex-M exception types: An error occurred while the bus status register was being pushed.
@@ -665,15 +648,18 @@ VOID HalHwiInit(VOID);
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m7/iar/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m7/iar/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,19 +73,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))
@@ -146,14 +129,27 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param)
+{
+    UNUSED(stackTop);
+    TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext));
+    (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext));
+
+    context->uwR0 = param;
+    context->uwPC = sigHandler;
+    context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m7/iar/los_dispatch.S

@@ -31,13 +31,14 @@
 
     PRESERVE8
 
-    EXPORT  HalIntLock
-    EXPORT  HalIntUnLock
-    EXPORT  HalIntRestore
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
     EXPORT  HalStartToRun
-    EXPORT  HalTaskSchedule
+    EXPORT  ArchTaskSchedule
     EXPORT  HalPendSV
     IMPORT  OsSchedTaskSwitch
+    IMPORT  OsSignalTaskContextRestore
     IMPORT  g_losTask
 
 OS_FPU_CPACR                EQU     0xE000ED88
@@ -52,6 +53,15 @@ OS_TASK_STATUS_RUNNING      EQU     0x0010
     THUMB
     REQUIRE8
 
+    MACRO SIGNAL_CONTEXT_RESTORE
+    PUSH    {R12, LR}
+    BLX     OsSignalTaskContextRestore
+    POP     {R12, LR}
+    CMP     R0, #0
+    MOV     R1, R0
+    BNE     SignalContextRestore
+    ENDM
+
 HalStartToRun
     LDR     R4, =OS_NVIC_SYSPRI2
     LDR     R5, =OS_NVIC_PENDSV_PRI
@@ -90,21 +100,21 @@ __DisabledFPU
     BX      R6
 
 
-HalIntLock
+ArchIntLock
     MRS     R0, PRIMASK
     CPSID   I
     BX      LR
 
-HalIntUnLock
+ArchIntUnLock
     MRS     R0, PRIMASK
     CPSIE   I
     BX      LR
 
-HalIntRestore
+ArchIntRestore
     MSR     PRIMASK, R0
     BX      LR
 
-HalTaskSchedule
+ArchTaskSchedule
     LDR     R0, =OS_NVIC_INT_CTRL
     LDR     R1, =OS_NVIC_PENDSVSET
     STR     R1, [R0]
@@ -117,6 +127,8 @@ HalPendSV
     CPSID   I
 
 HalTaskSwitch
+    SIGNAL_CONTEXT_RESTORE
+
     PUSH    {R12, LR}
     BLX     OsSchedTaskSwitch
     POP     {R12, LR}
@@ -145,8 +157,11 @@ __DisabledFPU1
 
     LDR     R0, [R5, #4]
     STR     R0, [R5]
-
     LDR     R1, [R0]
+
+SignalContextRestore
+    LDR.W   R3, =OS_FPU_CPACR
+    LDR     R3, [R3]
     AND     R3, R3, #OS_FPU_CPACR_ENABLE
     CMP     R3, #OS_FPU_CPACR_ENABLE
     BNE     __DisabledFPU2

arch/arm/cortex-m7/iar/los_interrupt.c

@@ -46,14 +46,14 @@ UINT32 g_intCount = 0;
 
 /*lint -restore*/
 #pragma location = ".data.vector"
-#pragma data_alignment=0x100
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
 /* *
  * @ingroup los_hwi
  * Hardware interrupt form mapping handling function array.
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -105,18 +105,86 @@ WEAK VOID SysTick_Handler(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_EnableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_DisableIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    if (priority > OS_HWI_PRIO_LOWEST) {
+        return OS_ERRNO_HWI_PRIO_INVALID;
+    }
+
+    NVIC_SetPriority((IRQn_Type)hwiNum, priority);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
+{
+    if (hwiNum >= OS_HWI_MAX_NUM) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+
+    NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
+
+    return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .triggerIrq     = HwiPending,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -130,8 +198,8 @@ inline UINT32 HalIsIntActive(VOID)
 /*lint -e529*/
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
-    PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
+    UINT32 irqNum = HwiNumGet();
+    PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, irqNum);
     while (1) {}
 }
 
@@ -165,13 +233,13 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
     g_intCount++;
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
 
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -191,7 +259,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -201,11 +269,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -226,13 +294,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    NVIC_EnableIRQ((IRQn_Type)hwiNum);
-    NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
+    HwiUnmask((IRQn_Type)hwiNum);
+    HwiSetPriority((IRQn_Type)hwiNum, hwiPrio);
 
     LOS_IntRestore(intSave);
 
@@ -240,13 +308,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -375,6 +443,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
     PRINTK("xPSR      = 0x%x\n", excInfo->context->uwxPSR);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -391,6 +460,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -440,7 +510,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcNvicDump();
     OsExcMemPoolCheckInfo();
@@ -480,7 +552,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************

arch/arm/cortex-m7/iar/los_mpu.c

@@ -49,22 +49,22 @@ typedef enum {
     MPU_AP_RO_USER_RO = 0x6,         /* Privileged:Read-only      Unprivileged:Read-only */
 } MpuApConfig;
 
-VOID HalMpuEnable(UINT32 defaultRegionEnable)
+VOID ArchMpuEnable(UINT32 defaultRegionEnable)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = (MPU_CTRL_ENABLE_Msk | ((defaultRegionEnable << MPU_CTRL_PRIVDEFENA_Pos) & MPU_CTRL_PRIVDEFENA_Msk));
     SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
-VOID HalMpuDisable(VOID)
+VOID ArchMpuDisable(VOID)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = 0;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
 
 STATIC VOID HalMpuRASRAddMemAttr(MPU_CFG_PARA *para, UINT32 *RASR)
@@ -147,7 +147,7 @@ STATIC UINT32 HalMpuGetRASR(UINT32 encodeSize, MPU_CFG_PARA *para)
     return RASR;
 }
 
-UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
+UINT32 ArchMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
 {
     UINT32 RASR;
     UINT32 RBAR;
@@ -175,9 +175,9 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     }
     RBAR = para->baseAddr & MPU_RBAR_ADDR_Msk;
     RASR = HalMpuGetRASR(encodeSize, para);
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
     MPU->RNR = RNR;
@@ -186,11 +186,11 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     __DSB();
     __ISB();
     g_regionNumBeUsed[regionId] = 1; /* Set mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-UINT32 HalMpuDisableRegion(UINT32 regionId)
+UINT32 ArchMpuDisableRegion(UINT32 regionId)
 {
     volatile UINT32 type;
     UINT32 intSave;
@@ -199,9 +199,9 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         return LOS_NOK;
     }
 
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (!g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
 
@@ -213,20 +213,20 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         __ISB();
     }
     g_regionNumBeUsed[regionId] = 0; /* clear mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-INT32 HalMpuUnusedRegionGet(VOID)
+INT32 ArchMpuUnusedRegionGet(VOID)
 {
     INT32 id;
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     for (id = 0; id < MPU_MAX_REGION_NUM; id++) {
         if (!g_regionNumBeUsed[id]) {
             break;
         }
     }
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 
     if (id == MPU_MAX_REGION_NUM) {
         return -1;

arch/arm/cortex-m7/iar/los_timer.c

@@ -33,38 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,7 +84,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle = 0;
     UINT32 intSave = LOS_IntLock();
@@ -95,17 +97,22 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/csky/v2/gcc/BUILD.gn

@@ -38,6 +38,7 @@ kernel_module(module_name) {
     "los_interrupt.c",
     "los_timer.c",
   ]
+  configs += [ "$LITEOSTOPDIR:warn_config" ]
 }
 
 config("public") {

arch/csky/v2/gcc/los_arch_atomic.h

@@ -40,12 +40,96 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    __asm__ __volatile__("ldw %0, (%1)\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    __asm__ __volatile__("stw %1, (%0, 0)"
+                         :
+                         : "r"(v), "r"(setVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldw %0, (%1)\n"
+                         "add %0, %0, %2\n"
+                         "stw %0, (%1, 0)"
+                         : "=&r"(val)
+                         : "r"(v), "r"(addVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldw %0, (%1)\n"
+                         "sub %0, %2\n"
+                         "stw %0, (%1, 0)"
+                         : "=&r"(val)
+                         : "r"(v), "r"(subVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
@@ -57,51 +141,22 @@ extern "C" {
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
-    INT32 prevVal;
+    INT32 prevVal = 0;
     UINT32 intSave;
 
     intSave = LOS_IntLock();
-    prevVal = *v;
-    *v = val;
+    __asm__ __volatile__("ldw %0, (%1)\n"
+                         "stw %2, (%1)"
+                         : "=&r"(prevVal)
+                         : "r"(v), "r"(val)
+                         : "cc");
     LOS_IntRestore(intSave);
 
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implement the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val;
-    UINT32 intSave;
-
-    intSave = LOS_IntLock();
-    *v -= 1;
-    val = *v;
-    LOS_IntRestore(intSave);
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -121,9 +176,109 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
-    INT32 prevVal;
+    INT32 prevVal = 0;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldw %0, (%1)\n"
+                         "cmpne %0, %2\n"
+                         "bt 1f\n"
+                         "stw %3, (%1)\n"
+                         "1:"
+                         : "=&r"(prevVal)
+                         : "r"(v), "r"(oldVal), "r"(val)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
     UINT32 intSave;
 
     intSave = LOS_IntLock();
@@ -143,4 +298,3 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
 #endif /* __cplusplus */
 
 #endif /* _LOS_ARCH_ATOMIC_H */
-

arch/csky/v2/gcc/los_arch_interrupt.h

@@ -218,7 +218,7 @@ extern VIC_TYPE *VIC_REG;
  */
 #define LOS_ERRNO_HWI_NUM_INVALID             OS_ERRNO_HWI_NUM_INVALID
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -251,25 +251,6 @@ extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
  */
 extern VOID HalInterrupt(VOID);
 
-/* *
- * @ingroup  los_arch_interrupt
- * @brief: Get an interrupt number.
- *
- * @par Description:
- * This API is used to get the current interrupt number.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param: None.
- *
- * @retval: Interrupt Indexes number.
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-extern UINT32 HalIntNumGet(VOID);
-
 /* *
  * @ingroup  los_arch_interrupt
  * @brief: Default vector handling function.

arch/csky/v2/gcc/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/csky/v2/gcc/los_context.c

@@ -36,37 +36,30 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 STATIC UINT32 g_sysNeedSched = FALSE;
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -74,7 +67,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -82,19 +75,9 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
-    TaskContext *context = NULL;
-    errno_t result;
-
-    /* initialize the task stack, write magic num to stack top */
-    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
-    if (result != EOK) {
-        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
-    }
-    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
-
-    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+    TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
 
     context->R0  = taskID;
     context->R1  = 0x01010101L;
@@ -110,13 +93,13 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->R11 = 0x11111111L;
     context->R12 = 0x12121212L;
     context->R13 = 0x13131313L;
-    context->R15 = (UINT32)HalSysExit;
+    context->R15 = (UINT32)ArchSysExit;
     context->EPSR = 0xe0000144L;
     context->EPC = (UINT32)OsTaskEntry;
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();
@@ -127,11 +110,11 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
 VOID HalIrqEndCheckNeedSched(VOID)
 {
     if (g_sysNeedSched && g_taskScheduled && LOS_CHECK_SCHEDULE) {
-        HalTaskSchedule();
+        ArchTaskSchedule();
     }
 }
 
-VOID HalTaskSchedule(VOID)
+VOID ArchTaskSchedule(VOID)
 {
     UINT32 intSave;
 

arch/csky/v2/gcc/los_interrupt.c

@@ -81,7 +81,7 @@ UINT32 HalSetVbr(UINT32 intSave)
     return intSave;
 }
 
-UINT32 HalIntLock(VOID)
+UINT32 ArchIntLock(VOID)
 {
     UINT32 intSave;
     __asm__ __volatile__(
@@ -93,7 +93,7 @@ UINT32 HalIntLock(VOID)
     return intSave;
 }
 
-UINT32 HalIntUnLock(VOID)
+UINT32 ArchIntUnLock(VOID)
 {
     UINT32 intSave;
     __asm__ __volatile__(
@@ -105,76 +105,91 @@ UINT32 HalIntUnLock(VOID)
     return intSave;
 }
 
-VOID HalIntRestore(UINT32 intSave)
+VOID ArchIntRestore(UINT32 intSave)
 {
     __asm__ __volatile__("mtcr %0, psr" : : "r"(intSave));
 }
 
-UINT32 HalIntLocked(VOID)
+UINT32 ArchIntLocked(VOID)
 {
     UINT32 intSave;
     __asm__ volatile("mfcr %0, psr" : "=r" (intSave) : : "memory");
     return !(intSave & (1 << INT_OFFSET));
 }
 
-UINT32 HalIrqUnmask(UINT32 hwiNum)
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
+
     if (!HwiNumValid(hwiNum)) {
         return LOS_ERRNO_HWI_NUM_INVALID;
     }
+
     intSave = LOS_IntLock();
     VIC_REG->ISER[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
     VIC_REG->ISSR[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
     LOS_IntRestore(intSave);
+
     return LOS_OK;
 }
 
-UINT32 HalIrqSetPriority(UINT32 hwiNum, UINT8 priority)
+STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
 {
     UINT32 intSave;
+
     if (!HwiNumValid(hwiNum)) {
         return LOS_ERRNO_HWI_NUM_INVALID;
     }
+
     if (!HWI_PRI_VALID(priority)) {
         return OS_ERRNO_HWI_PRIO_INVALID;
     }
+
     intSave = LOS_IntLock();
     VIC_REG->IPR[hwiNum / PRI_PER_REG] |= (((priority << PRI_OFF_IN_REG) << (hwiNum % PRI_PER_REG)) * PRI_OFF_PER_INT);
     LOS_IntRestore(intSave);
+
     return LOS_OK;
 }
 
-UINT32 HalIrqMask(HWI_HANDLE_T hwiNum)
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
+
     if (!HwiNumValid(hwiNum)) {
         return LOS_ERRNO_HWI_NUM_INVALID;
     }
+
     intSave = LOS_IntLock();
     VIC_REG->ICER[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
     LOS_IntRestore(intSave);
+
     return LOS_OK;
 }
 
-UINT32 HalIrqPending(UINT32 hwiNum)
+STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
+
     if (!HwiNumValid(hwiNum)) {
         return LOS_ERRNO_HWI_NUM_INVALID;
     }
+
     intSave = LOS_IntLock();
     VIC_REG->ISPR[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
     LOS_IntRestore(intSave);
+
     return LOS_OK;
 }
 
-UINT32 HalIrqClear(UINT32 hwiNum)
+STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
 {
     if (!HwiNumValid(hwiNum)) {
         return LOS_ERRNO_HWI_NUM_INVALID;
     }
+
     VIC_REG->ICPR[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
+
     return LOS_OK;
 }
 
@@ -184,7 +199,7 @@ UINT32 HalIrqClear(UINT32 hwiNum)
  */
 STATIC HWI_PROC_FUNC __attribute__((aligned(HWI_ALIGNSIZE))) g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -207,7 +222,7 @@ VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
         g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)IrqEntry;
         g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
         g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
-        HalIrqUnmask(num);
+        HwiUnmask(num);
     }
 }
 
@@ -227,24 +242,33 @@ VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
     if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
         g_hwiForm[num + OS_SYS_VECTOR_CNT] = IrqEntry;
         g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
-        HalIrqUnmask(num);
+        HwiUnmask(num);
     }
 }
 #endif
 
 /* ****************************************************************************
- Function    : HalIntNumGet
+ Function    : HwiNumGet
  Description : Get an interrupt number
  Input       : None
  Output      : None
  Return      : Interrupt Indexes number
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
+STATIC UINT32 HwiNumGet(VOID)
 {
     return HalGetPsr();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+HwiControllerOps g_archHwiOps = {
+    .triggerIrq     = HwiPending,
+    .enableIrq      = HwiUnmask,
+    .disableIrq     = HwiMask,
+    .setIrqPriority = HwiSetPriority,
+    .getCurIrqNum   = HwiNumGet,
+    .clearIrq       = HwiClear,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -258,7 +282,7 @@ inline UINT32 HalIsIntActive(VOID)
  **************************************************************************** */
 LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
 {
-    UINT32 irqNum = HalIntNumGet();
+    UINT32 irqNum = HwiNumGet();
     irqNum = (irqNum >> PSR_VEC_OFFSET) & MASK_8_BITS;
     PRINT_ERR("%s irqnum:%x\n", __FUNCTION__, irqNum);
     while (1) {}
@@ -290,12 +314,12 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
     g_intCount++;
     LOS_IntRestore(intSave);
 
-    hwiIndex = HalIntNumGet();
+    hwiIndex = HwiNumGet();
     hwiIndex = (hwiIndex >> PSR_VEC_OFFSET) & MASK_8_BITS;
     OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
 
     HalPreInterruptHandler(hwiIndex);
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -316,7 +340,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -326,11 +350,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -350,33 +374,33 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
         return OS_ERRNO_HWI_PRIO_INVALID;
     }
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
 #endif
-    HalIrqUnmask(hwiNum);
-    (VOID)HalIrqSetPriority(hwiNum, (UINT8)hwiPrio);
+    HwiUnmask(hwiNum);
+    (VOID)HwiSetPriority(hwiNum, (UINT8)hwiPrio);
     LOS_IntRestore(intSave);
 
     return LOS_OK;
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
     if (hwiNum >= OS_HWI_MAX_NUM) {
         return OS_ERRNO_HWI_NUM_INVALID;
     }
-    HalIrqMask(hwiNum);
+    HwiMask(hwiNum);
     intSave = LOS_IntLock();
     g_hwiHandlerForm[hwiNum + OS_SYS_VECTOR_CNT] = 0;
     LOS_IntRestore(intSave);
@@ -442,6 +466,7 @@ STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
            excContext->EPC);
 }
 
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
 {
     UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
@@ -458,6 +483,7 @@ STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
     }
     PRINTK("----- backtrace end -----\n");
 }
+#endif
 
 STATIC VOID OsExcMemPoolCheckInfo(VOID)
 {
@@ -507,7 +533,9 @@ STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
     OsExcTypeInfo(excInfo);
     OsExcCurTaskInfo(excInfo);
     OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
     OsExcBackTraceInfo(excInfo);
+#endif
     OsGetAllTskInfo();
     OsExcMemPoolCheckInfo();
 #endif
@@ -538,7 +566,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(EXC_CONTEXT_S *excBufAddr, UINT32 f
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* stack protector */

arch/csky/v2/gcc/los_timer.c

@@ -33,8 +33,6 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
 typedef struct {
@@ -44,8 +42,6 @@ typedef struct {
     UINT32 CALIB;
 } CORE_TIM_TYPE;
 
-#define OS_CYCLE_PER_TICK    (OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND)
-
 #define CORE_TIM_BASE        (0xE000E010UL)
 #define SysTick              ((CORE_TIM_TYPE *)CORE_TIM_BASE)
 
@@ -56,6 +52,23 @@ typedef struct {
 
 #define TIM_INT_NUM          1
 
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = TIM_INT_NUM,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
 /* ****************************************************************************
 Function    : HalTickStart
 Description : Configure Tick Interrupt Start
@@ -63,15 +76,12 @@ Input       : none
 output      : none
 return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
 **************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
-    if ((OS_SYS_CLOCK == 0) || (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    ArchTickTimer *tick = &g_archTickTimer;
+
+    tick->freq = OS_SYS_CLOCK;
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_CYCLE_PER_TICK;
     SysTick->LOAD = (OS_CYCLE_PER_TICK - 1);
     SysTick->VAL = 0;
     SysTick->CTRL |= (CORETIM_SOURCE | CORETIM_ENABLE | CORETIM_INTMASK);
@@ -79,16 +89,16 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     VIC_REG->IWER[0] = 0x1 << TIM_INT_NUM;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(TIM_INT_NUM, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(TIM_INT_NUM, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~CORETIM_ENABLE;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -96,7 +106,7 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= CORETIM_ENABLE;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 hwCycle;
     UINT32 intSave = LOS_IntLock();
@@ -106,16 +116,21 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~CORETIM_ENABLE;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= CORETIM_ENABLE;
 }
 
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
 VOID Wfi(VOID)
 {
     __asm__ volatile("wait");
@@ -126,7 +141,7 @@ VOID Dsb(VOID)
     __asm__ volatile("sync" : : : "memory");
 }
 
-UINT32 HalEnterSleep(VOID)
+UINT32 ArchEnterSleep(VOID)
 {
     Dsb();
     Wfi();

arch/include/los_arch.h

@@ -41,7 +41,7 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-VOID HalArchInit(VOID);
+VOID ArchInit(VOID);
 
 #ifdef __cplusplus
 #if __cplusplus

arch/include/los_atomic.h

@@ -33,6 +33,7 @@
 #define _LOS_ATOMIC_H
 
 #include "los_compiler.h"
+#include "los_arch_atomic.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -40,7 +41,26 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-
+#define LOS_AtomicRead ArchAtomicRead
+#define LOS_AtomicSet ArchAtomicSet
+#define LOS_AtomicAdd ArchAtomicAdd
+#define LOS_AtomicSub ArchAtomicSub
+#define LOS_AtomicInc ArchAtomicInc
+#define LOS_AtomicIncRet ArchAtomicIncRet
+#define LOS_AtomicDec ArchAtomicDec
+#define LOS_AtomicDecRet ArchAtomicDecRet
+#define LOS_Atomic64Read ArchAtomic64Read
+#define LOS_Atomic64Set ArchAtomic64Set
+#define LOS_Atomic64Add ArchAtomic64Add
+#define LOS_Atomic64Sub ArchAtomic64Sub
+#define LOS_Atomic64Inc ArchAtomic64Inc
+#define LOS_Atomic64IncRet ArchAtomic64IncRet
+#define LOS_Atomic64Dec ArchAtomic64Dec
+#define LOS_Atomic64DecRet ArchAtomic64DecRet
+#define LOS_AtomicXchg32bits ArchAtomicXchg32bits
+#define LOS_AtomicXchg64bits ArchAtomicXchg64bits
+#define LOS_AtomicCmpXchg32bits ArchAtomicCmpXchg32bits
+#define LOS_AtomicCmpXchg64bits ArchAtomicCmpXchg64bits
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/include/los_context.h

@@ -65,7 +65,7 @@ extern "C" {
  * <ul><li>los_context.h: the header file that contains the API declaration.</li></ul>
  * @see None.
  */
-extern VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack);
+VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack);
 
 /**
  * @ingroup  los_context
@@ -84,7 +84,7 @@ extern VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack);
  * <ul><li>los_context.h: the header file that contains the API declaration.</li></ul>
  * @see None.
  */
-LITE_OS_SEC_TEXT_MINOR NORETURN VOID HalSysExit(VOID);
+LITE_OS_SEC_TEXT_MINOR NORETURN VOID ArchSysExit(VOID);
 
 /**
  * @ingroup  los_context
@@ -103,10 +103,10 @@ LITE_OS_SEC_TEXT_MINOR NORETURN VOID HalSysExit(VOID);
  * <ul><li>los_context.h: the header file that contains the API declaration.</li></ul>
  * @see None.
  */
-extern VOID HalTaskSchedule(VOID);
+VOID ArchTaskSchedule(VOID);
 
-typedef VOID (*OS_TICK_HANDLER)(VOID);
-UINT32 HalStartSchedule(VOID);
+UINT32 ArchStartSchedule(VOID);
+VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param);
 
 #ifdef __cplusplus
 #if __cplusplus

arch/include/los_interrupt.h

@@ -40,14 +40,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-/* *
- * @ingroup los_interrupt
- * Configuration item for interrupt with argument
- */
-#ifndef OS_HWI_WITH_ARG
-#define OS_HWI_WITH_ARG                       0
-#endif
-
 typedef UINT32 HWI_HANDLE_T;
 
 typedef UINT16 HWI_PRIOR_T;
@@ -56,31 +48,49 @@ typedef UINT16 HWI_MODE_T;
 
 typedef UINT32 HWI_ARG_T;
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 typedef VOID (*HWI_PROC_FUNC)(VOID *parm);
 #else
 typedef VOID (*HWI_PROC_FUNC)(void);
 #endif
 
+typedef struct {
+    UINT32 (*triggerIrq)(HWI_HANDLE_T hwiNum);
+    UINT32 (*clearIrq)(HWI_HANDLE_T hwiNum);
+    UINT32 (*enableIrq)(HWI_HANDLE_T hwiNum);
+    UINT32 (*disableIrq)(HWI_HANDLE_T hwiNum);
+    UINT32 (*setIrqPriority)(HWI_HANDLE_T hwiNum, UINT8 priority);
+    UINT32 (*getCurIrqNum)(VOID);
+} HwiControllerOps;
+
+extern HwiControllerOps g_archHwiOps;
+
 /* stack protector */
 extern UINT32 __stack_chk_guard;
 
 extern VOID __stack_chk_fail(VOID);
 
-UINT32 HalIsIntActive(VOID);
-#define OS_INT_ACTIVE    (HalIsIntActive())
+UINT32 ArchIsIntActive(VOID);
+#define OS_INT_ACTIVE    (ArchIsIntActive())
 #define OS_INT_INACTIVE  (!(OS_INT_ACTIVE))
-#define LOS_HwiCreate HalHwiCreate
-#define LOS_HwiDelete HalHwiDelete
+#define LOS_HwiCreate ArchHwiCreate
+#define LOS_HwiDelete ArchHwiDelete
+#define LOS_HwiTrigger ArchIntTrigger
+#define LOS_HwiEnable ArchIntEnable
+#define LOS_HwiDisable ArchIntDisable
+#define LOS_HwiClear ArchIntClear
+#define LOS_HwiSetPriority ArchIntSetPriority
 
-UINT32 HalIntLock(VOID);
-#define LOS_IntLock HalIntLock
+UINT32 ArchIntLock(VOID);
+#define LOS_IntLock ArchIntLock
 
-VOID HalIntRestore(UINT32 intSave);
-#define LOS_IntRestore HalIntRestore
+VOID ArchIntRestore(UINT32 intSave);
+#define LOS_IntRestore ArchIntRestore
 
-UINT32 HalIntUnLock(VOID);
-#define LOS_IntUnLock HalIntUnLock
+UINT32 ArchIntUnLock(VOID);
+#define LOS_IntUnLock ArchIntUnLock
+
+#define LOS_HwiOpsGet ArchIntOpsGet
 
 /**
  * @ingroup  los_interrupt
@@ -105,7 +115,7 @@ UINT32 HalIntUnLock(VOID);
  * <ul><li>los_interrupt.h: the header file that contains the API declaration.</li></ul>
  * @see None.
  */
-extern UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum);
+UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum);
 
 /**
  * @ingroup  los_interrupt
@@ -137,11 +147,56 @@ extern UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum);
  * <ul><li>los_interrupt.h: the header file that contains the API declaration.</li></ul>
  * @see None.
  */
-extern UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                           HWI_PRIOR_T hwiPrio,
-                           HWI_MODE_T mode,
-                           HWI_PROC_FUNC handler,
-                           HWI_ARG_T arg);
+UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                     HWI_PRIOR_T hwiPrio,
+                     HWI_MODE_T mode,
+                     HWI_PROC_FUNC handler,
+                     HWI_ARG_T arg);
+
+STATIC INLINE UINT32 ArchIntTrigger(HWI_HANDLE_T hwiNum)
+{
+    if (g_archHwiOps.triggerIrq == NULL) {
+        return LOS_NOK;
+    }
+    return g_archHwiOps.triggerIrq(hwiNum);
+}
+
+STATIC INLINE UINT32 ArchIntEnable(HWI_HANDLE_T hwiNum)
+{
+    if (g_archHwiOps.enableIrq == NULL) {
+        return LOS_NOK;
+    }
+    return g_archHwiOps.enableIrq(hwiNum);
+}
+
+STATIC INLINE UINT32 ArchIntDisable(HWI_HANDLE_T hwiNum)
+{
+    if (g_archHwiOps.disableIrq == NULL) {
+        return LOS_NOK;
+    }
+    return g_archHwiOps.disableIrq(hwiNum);
+}
+
+STATIC INLINE UINT32 ArchIntClear(HWI_HANDLE_T hwiNum)
+{
+    if (g_archHwiOps.clearIrq == NULL) {
+        return LOS_NOK;
+    }
+    return g_archHwiOps.clearIrq(hwiNum);
+}
+
+STATIC INLINE UINT32 ArchIntSetPriority(HWI_HANDLE_T hwiNum, HWI_PRIOR_T priority)
+{
+    if (g_archHwiOps.setIrqPriority == NULL) {
+        return LOS_NOK;
+    }
+    return g_archHwiOps.setIrqPriority(hwiNum, priority);
+}
+
+STATIC INLINE HwiControllerOps *ArchIntOpsGet(VOID)
+{
+    return &g_archHwiOps;
+}
 
 #ifdef __cplusplus
 #if __cplusplus

arch/include/los_mpu.h

@@ -79,11 +79,11 @@ typedef struct {
     MpuMemType memType;
 } MPU_CFG_PARA;
 
-VOID HalMpuEnable(UINT32 defaultRegionEnable);
-VOID HalMpuDisable();
-UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para);
-UINT32 HalMpuDisableRegion(UINT32 regionId);
-INT32 HalMpuUnusedRegionGet(VOID);
+VOID ArchMpuEnable(UINT32 defaultRegionEnable);
+VOID ArchMpuDisable(VOID);
+UINT32 ArchMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para);
+UINT32 ArchMpuDisableRegion(UINT32 regionId);
+INT32 ArchMpuUnusedRegionGet(VOID);
 
 #ifdef __cplusplus
 #if __cplusplus

arch/include/los_timer.h

@@ -33,6 +33,7 @@
 #define _LOS_TIMER_H
 
 #include "los_compiler.h"
+#include "los_interrupt.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -52,55 +53,36 @@ extern "C" {
 #define RTC_CALIBRATE_SLEEP_TIME 8
 #define MACHINE_CYCLE_DEALAY_TIMES (LOSCFG_BASE_CORE_TICK_PER_SECOND << 2)
 
-VOID HalTickLock(VOID);
+typedef struct {
+    UINT32        freq;
+    INT32         irqNum;
+    UINT32        (*init)(HWI_PROC_FUNC tickHandler);
+    UINT64        (*getCycle)(UINT32 *period);
+    VOID          (*reload)(UINT64 time);
+    VOID          (*lock)(VOID);
+    VOID          (*unlock)(VOID);
+    HWI_PROC_FUNC tickHandler;
+} ArchTickTimer;
 
-VOID HalTickUnlock(VOID);
-
-UINT32 HalEnterSleep(VOID);
+UINT32 ArchEnterSleep(VOID);
 
 /**
  * @ingroup los_timer
- * @brief Get systick cycle.
+ * @brief Get tick timer control block.
  *
  * @par Description:
- * This API is used to get systick cycle and return current tick period.
+ * This API is used to get tick timer control block.
  *
- * @attention
- * <ul>
- * <li>None.</li>
- * </ul>
- *
- * @param: period [OUT] current tick period.
- *
- * @retval current tick count.
+ * @param  None
  *
+ * @retval #tick timer control block
  * @par Dependency:
  * <ul><li>los_timer.h: the header file that contains the API declaration.</li></ul>
- * @see
+ * @see None.
  */
-UINT64 HalGetTickCycle(UINT32 *period);
+ArchTickTimer *ArchSysTickTimerGet(VOID);
 
-/**
- * @ingroup los_timer
- * @brief reconfig systick, and clear SysTick_IRQn.
- *
- * @par Description:
- * <ul>
- * <li>This API is used to reconfig systick, and clear SysTick_IRQn.</li>
- * </ul>
- * @attention
- * <ul>
- * <li>None.</li>
- * </ul>
- *
- * @param  nextResponseTime  [IN] tick period
- *
- * @retval None.
- * @par Dependency:
- * <ul><li>los_timer.h: the header file that contains the API declaration.</li></ul>
- * @see None
- */
-extern VOID HalSysTickReload(UINT64 nextResponseTime);
+#define LOS_SysTickTimerGet ArchSysTickTimerGet
 
 #ifdef __cplusplus
 #if __cplusplus

arch/risc-v/nuclei/gcc/los_arch_atomic.h

@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("lr.w %0, (%1)\n"
+                         "fence rw, rw\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "memory");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("amoswap.w %0, %2, (%1)\n"
+                         : "=r"(prevVal)
+                         : "r"(v), "r"(setVal)
+                         : "memory");
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("amoadd.w %0, %2, (%1)\n"
+                         "lw %0, (%1)\n"
+                         "fence rw, rw\n"
+                         : "=&r"(val)
+                         : "r"(v), "r"(addVal)
+                         : "memory");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("amoadd.w %0, %2, (%1)\n"
+                         "lw %0, (%1)\n"
+                         "fence rw, rw\n"
+                         : "=&r"(val)
+                         : "r"(v), "r"(-subVal)
+                         : "memory");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("lw %0, 0(%1)\n"
+                         "amoswap.w %0, %2, (%1)\n"
+                         : "=&r"(prevVal)
+                         : "r"(v), "r"(val)
+                         : "memory");
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    __asm__ __volatile__("lw %0, 0(%1)\n"
+                         "bne %0, %2, 1f\n"
+                         "amoswap.w %0, %3, (%1)\n"
+                         "1:"
+                         : "=&r"(prevVal)
+                         : "r"(v), "r"(oldVal), "r"(val)
+                         : "memory");
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/risc-v/nuclei/gcc/los_arch_interrupt.h

@@ -166,7 +166,7 @@ extern VOID HalHwiDefaultHandler(VOID);
  *
  * Value: 0x02000909
  *
- * * Solution:check the input params hwiMode and irqParam of HalHwiCreate or HalHwiDelete whether adapt the current
+ * * Solution:check the input params hwiMode and irqParam of ArchHwiCreate or ArchHwiDelete whether adapt the current
  * hwi.
  */
 #define OS_ERRNO_HWI_SHARED_ERROR LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x09)