!527 支持IAR C++ thread_local特性

Merge pull request !527 from JerryH/iar_thread_local

.gitignore

@@ -14,3 +14,8 @@ targets/cortex-m7_nucleo_f767zi_gcc/build
 *.o
 *.d
 *.su
+
+# Menuconfig temp files
+/config.h
+/.config
+/.config.old

BUILD.gn

@@ -27,59 +27,282 @@
 # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import("config.gni")
+import("//build/lite/config/component/lite_component.gni")
+
+LITEOS_MENUCONFIG_H = rebase_path("$root_out_dir/config.h")
+
+declare_args() {
+  liteos_name = "OHOS_Image"
+  liteos_kernel_only = false
+}
+
+import("liteos.gni")
+
+liteos_arch_cflags = []
+if (defined(LOSCFG_ARCH_ARM)) {
+  mcpu = LOSCFG_ARCH_CPU
+  if (defined(LOSCFG_ARCH_ARM_AARCH64) && defined(LOSCFG_ARCH_FPU_DISABLE)) {
+    mcpu += "+nofp"
+  }
+  liteos_arch_cflags += [ "-mcpu=$mcpu" ]
+  if (defined(LOSCFG_ARCH_ARM_AARCH32) && defined(LOSCFG_ARCH_FPU)) {
+    liteos_arch_cflags += [ "-mfpu=$LOSCFG_ARCH_FPU" ]
+  }
+}
+
+cc = "$ohos_current_cc_command " + string_join(" ", liteos_arch_cflags)
+if (ohos_build_compiler == "clang") {
+  cc += " --target=$target_triple"
+}
+
+config("arch_config") {
+  cflags = liteos_arch_cflags
+  asmflags = cflags
+  ldflags = cflags
+  if (defined(LOSCFG_ARCH_ARM_AARCH32)) {
+    if (!defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+      cflags += [ "-mthumb-interwork" ]
+    }
+  }
+  if (defined(LOSCFG_THUMB)) {
+    cflags += [ "-mthumb" ]
+    if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+      cflags += [ "-mimplicit-it=thumb" ]
+    } else {
+      cflags += [ "-Wa,-mimplicit-it=thumb" ]
+    }
+  }
+}
+
+config("stdinc_config") {
+  std_include = exec_script("//build/lite/run_shell_cmd.py",
+                            [ "$cc -print-file-name=include" ],
+                            "trim string")
+  cflags = [
+    "-isystem",
+    std_include,
+  ]
+  cflags += [ "-nostdinc" ]
+  asmflags = cflags
+  if (defined(LOSCFG_LIBC_NEWLIB)) {
+    cflags -= [ "-nostdinc" ]
+  }
+}
+
+config("ssp_config") {
+  cflags = []
+  if (defined(LOSCFG_CC_STACKPROTECTOR_ALL)) {
+    cflags += [ "-fstack-protector-all" ]
+  } else if (defined(LOSCFG_CC_STACKPROTECTOR_STRONG)) {
+    cflags += [ "-fstack-protector-strong" ]
+  } else if (defined(LOSCFG_CC_STACKPROTECTOR)) {
+    cflags += [
+      "-fstack-protector",
+      "--param",
+      "ssp-buffer-size=4",
+    ]
+  } else {
+    cflags += [ "-fno-stack-protector" ]
+  }
+  asmflags = cflags
+}
+
+config("optimize_config") {
+  cflags = []
+  if (defined(LOSCFG_COMPILE_DEBUG)) {
+    cflags += [
+      "-g",
+      "-gdwarf-2",
+    ]
+    optimization_cflag = "-O0"
+  }
+  if (defined(LOSCFG_COMPILE_OPTIMIZE)) {
+    optimization_cflag = "-O2"
+  }
+  if (defined(LOSCFG_COMPILE_OPTIMIZE_SIZE)) {
+    if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+      optimization_cflag = "-Oz"
+    } else {
+      optimization_cflag = "-Os"
+    }
+  }
+  if (defined(LOSCFG_COMPILE_LTO)) {
+    if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+      cflags += [ "-flto=thin" ]
+    } else {
+      #cflags += [ "-flto" ]
+    }
+  }
+  cflags += [ optimization_cflag ]
+  asmflags = cflags
+}
+
+config("kconfig_config") {
+  cflags = [
+    "-imacros",
+    "$LITEOS_MENUCONFIG_H",
+  ]
+  asmflags = cflags
+}
+
+config("warn_config") {
+  cflags = [
+    "-Wall",
+    "-Werror",
+    "-Wpointer-arith",
+    "-Wstrict-prototypes",
+    "-Winvalid-pch",
+    "-Wno-address-of-packed-member",
+  ]
+  asmflags = cflags
+}
+
+config("dialect_config") {
+  cflags_c = [ "-std=c99" ]
+  cflags_cc = [ "-std=c++11" ]
+}
+
+config("misc_config") {
+  defines = [ "__LITEOS__" ]
+  defines += [ "__LITEOS_M__" ]
+  if (!defined(LOSCFG_DEBUG_VERSION)) {
+    defines += [ "NDEBUG" ]
+  }
+
+  cflags = [
+    "-fno-pic",
+    "-fno-builtin",
+    "-fms-extensions",
+    "-fno-strict-aliasing",
+    "-fno-common",
+    "-fsigned-char",
+    "-ffunction-sections",
+    "-fdata-sections",
+    "-fno-exceptions",
+    "-fno-omit-frame-pointer",
+  ]
+
+  if (!defined(LOSCFG_COMPILER_CLANG_LLVM)) {
+    cflags += [ "-fno-aggressive-loop-optimizations" ]
+  }
+
+  asmflags = cflags
+  asmflags += [ "-DCLZ=CLZ" ]
+}
 
 config("los_config") {
-  cflags = [ "-Werror" ]
+  configs = [
+    #":arch_config",
+    ":kconfig_config",
 
-  include_dirs = [
-    "//kernel/liteos_m/kernel/include",
-    "//kernel/liteos_m/kernel/arch/include",
-    "//kernel/liteos_m/utils",
-    "//third_party/bounds_checking_function/include",
+    ":stdinc_config",
+    ":dialect_config",
+    ":optimize_config",
+    ":ssp_config",
+
+    #":warn_config",
+    ":misc_config",
   ]
 }
 
+cmd = "if [ -f $device_path/BUILD.gn ]; then echo true; else echo false; fi"
+HAVE_DEVICE_SDK = exec_script("//build/lite/run_shell_cmd.py", [ cmd ], "value")
+
+# board and soc decoupling feature, device_path should contains board
+BOARD_SOC_FEATURE = device_path != string_replace(device_path, "/board/", "")
+
+config("public") {
+  configs = [
+    "arch:public",
+    "kernel:public",
+    "kal:public",
+    "components:public",
+    "utils:public",
+  ]
+
+  if (BOARD_SOC_FEATURE) {
+    configs += [ "//device/board/$device_company:public" ]
+    configs += [ "//device/soc/$LOSCFG_SOC_COMPANY:public" ]
+  } else {
+    if (HAVE_DEVICE_SDK) {
+      configs += [ "$device_path:public" ]
+    }
+  }
+}
+
+group("modules") {
+  deps = [
+    "arch",
+    "components",
+    "kal",
+    "kernel",
+    "testsuites",
+    "utils",
+    HDFTOPDIR,
+  ]
+
+  if (BOARD_SOC_FEATURE) {
+    deps += [ "//device/board/$device_company" ]
+    deps += [ "//device/soc/$LOSCFG_SOC_COMPANY" ]
+  } else {
+    if (HAVE_DEVICE_SDK) {
+      deps += [ device_path ]
+    }
+  }
+}
+
+# when HAVE_DEVICE_SDK is not reached, gn raises an error. so we just use it as
+# not needed
+not_needed([ "HAVE_DEVICE_SDK" ])
+
+static_library("libkernel") {
+  deps = [ ":modules" ]
+  complete_static_lib = false
+}
+
 group("kernel") {
-  deps = [
-    "kernel:kernel",
-    "utils:utils",
-    "//third_party/bounds_checking_function:libsec_static",
+  deps = [ ":libkernel" ]
+}
+
+group("liteos_m") {
+}
+
+executable("liteos") {
+  configs += [
+    ":public",
+    ":los_config",
   ]
-  if (enable_ohos_kernel_liteos_m_cppsupport) {
-    deps += [ "components/cppsupport:cppsupport" ]
-  }
-  if (enable_ohos_kernel_liteos_m_cpup) {
-    deps += [ "components/cpup:cpup" ]
-  }
-  if (enable_ohos_kernel_liteos_m_exchook) {
-    deps += [ "components/exchook:exchook" ]
-  }
-  if (enable_ohos_kernel_liteos_m_backtrace) {
-    deps += [ "components/backtrace:backtrace" ]
-  }
-  if (enable_ohos_kernel_liteos_m_fs) {
-    deps += [ "components/fs:fs" ]
-  }
-  if (enable_ohos_kernel_liteos_m_pm) {
-    deps += [ "components/power:pm" ]
-  }
-  if (enable_ohos_kernel_liteos_m_trace) {
-    deps += [ "components/trace:trace" ]
-  }
-  if (enable_ohos_kernel_liteos_m_kal) {
-    deps += [ "kal:kal" ]
-  }
-  if (enable_ohos_kernel_liteos_m_shell) {
-    deps += [ "components/shell:shell" ]
-  }
-  if (enable_ohos_kernel_liteos_m_test) {
-    deps += [ "testsuits:test" ]
-  }
-  if (enable_ohos_kernel_liteos_m_lwip) {
-    deps += [ ohos_kernel_liteos_m_lwip_path ]
-  }
-  if (enable_ohos_kernel_liteos_m_dynlink) {
-    deps += [ "components/dynlink:dynlink" ]
+
+  ldflags = [
+    "-static",
+    "-Wl,--gc-sections",
+    "-Wl,-Map=$liteos_name.map",
+  ]
+
+  output_dir = target_out_dir
+
+  if (liteos_kernel_only) {
+    deps = [ ":kernel" ]
+  } else {
+    deps = [ "//build/lite:ohos" ]
   }
 }
+
+copy("copy_liteos") {
+  deps = [ ":liteos" ]
+  sources = [ "$target_out_dir/unstripped/bin/liteos" ]
+  outputs = [ "$root_out_dir/$liteos_name" ]
+}
+
+build_ext_component("build_kernel_image") {
+  deps = [ ":copy_liteos" ]
+  exec_path = rebase_path(root_out_dir)
+
+  objcopy = "${compile_prefix}objcopy$toolchain_cmd_suffix"
+  objdump = "${compile_prefix}objdump$toolchain_cmd_suffix"
+
+  command = "$objcopy -O binary $liteos_name $liteos_name.bin"
+  command +=
+      " && sh -c '$objdump -t $liteos_name | sort >$liteos_name.sym.sorted'"
+  command += " && sh -c '$objdump -d $liteos_name >$liteos_name.asm'"
+}

Kconfig

@@ -0,0 +1,655 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+mainmenu "Huawei LiteOS Configuration"
+
+menu "Compiler"
+choice
+    prompt "Compiler type"
+    default COMPILER_GCC
+    help
+      Choose compiler type.
+
+config COMPILER_GCC
+    bool "GCC"
+
+config CROSS_COMPILE
+    string "GCC cross-compile toolchain prefix"
+    depends on COMPILER_GCC
+    default "arm-none-eabi-" if ARCH_ARM_AARCH32
+
+config COMPILER_CLANG_LLVM
+    bool "Clang"
+
+config LLVM_TARGET
+    string "Clang LLVM target"
+    depends on COMPILER_CLANG_LLVM
+    default "arm-liteos-ohos" if ARCH_ARM_AARCH32
+
+endchoice
+
+config COMPILE_DEBUG
+    bool "Enable debug options"
+    default n
+    help
+      Answer Y to add -g option in compile command.
+
+config COMPILE_OPTIMIZE
+    bool "Enable code optimization options"
+    default y
+    help
+      Answer Y to add optimization options for efficient code.
+      The final binary size will be smaller and execute faster.
+      But the debugging experience may be worst somehow.
+
+config COMPILE_OPTIMIZE_SIZE
+    bool "Enable code size optimization options" if COMPILE_OPTIMIZE
+    default y
+    help
+      Answer Y to add optimization options for small code size.
+      The final binary size will be smaller.
+      But the compile time may be a bit longer.
+
+config COMPILE_LTO
+    bool "Enable link time optimization (LTO)" if COMPILE_OPTIMIZE_SIZE
+    default y
+    help
+      Answer Y to add lto options for more smaller code size.
+      The final binary size will be smaller.
+      But the compile time may be much longer.
+
+endmenu
+
+menu "Platform"
+
+######################### config options of bsp #####################
+config PLATFORM
+    string
+    default "virt"            if PLATFORM_QEMU_ARM_VIRT_CM7 || PLATFORM_QEMU_ARM_VIRT_CM4 || PRODUCT_QEMU_RISCV32_VIRT || PLATFORM_QEMU_CSKY_SMARTL || PLATFORM_QEMU_XTENSA_ESP32
+
+config PRODUCT_NAME
+    string
+    default "arm_virt" if PRODUCT_QEMU_ARM
+    default "arm_mps2_an386" if PRODUCT_QEMU_ARM_MPS2_AN386
+    default "riscv32_virt" if PRODUCT_QEMU_RISCV32_VIRT
+    default "csky_smartl_e802" if PRODUCT_QEMU_CSKY_SMARTL_E802
+    default "xtensa_esp32" if PRODUCT_QEMU_XTENSA_ESP32
+
+config DEVICE_COMPANY
+    string
+    default "qemu" if PLATFORM_QEMU_ARM_VIRT_CM7 || PLATFORM_QEMU_ARM_VIRT_CM4 || PRODUCT_QEMU_RISCV32_VIRT || PLATFORM_QEMU_CSKY_SMARTL || PLATFORM_QEMU_XTENSA_ESP32
+
+choice
+    prompt "Chip"
+    default PLATFORM_QEMU_ARM_VIRT_CM7
+    help
+      Qemu ARM Virt variants (based on different CPU types):
+       - qemu_arm_virt_cm7
+       - qemu_arm_virt_cm4
+       - qemu_riscv32_virt
+       - qemu_csky_smartl
+       - qemu_xtensa_esp32
+
+config PLATFORM_QEMU_ARM_VIRT_CM7
+    bool "qemu_arm_virt_cm7"
+    select ARCH_CORTEX_M7
+    help
+        QEMU ARM Virtual Platform using Cortex-M7 CPU.
+
+config PLATFORM_QEMU_ARM_VIRT_CM4
+    bool "qemu_arm_virt_cm4"
+    select ARCH_CORTEX_M4
+    help
+        QEMU ARM Virtual Platform using Cortex-M4 CPU.
+
+config PLATFORM_QEMU_RISCV32_VIRT
+    bool "qemu_riscv32_virt"
+    select ARCH_RISCV32
+    help
+        QEMU RISCV Virtual Platform using riscv32 CPU.
+
+config PLATFORM_QEMU_CSKY_SMARTL
+    bool "qemu_csky_smartl"
+    select ARCH_CSKY
+    help
+        QEMU SmartL Virtual Platform using csky CPU.
+
+config PLATFORM_QEMU_XTENSA_ESP32
+    bool "qemu_xtensa_esp32"
+    select ARCH_XTENSA
+    help
+        QEMU ESP32 Virtual Platform using xtensa CPU.
+
+endchoice
+
+choice
+    prompt "Product"
+    help
+      Select your target board.
+
+config PRODUCT_QEMU_ARM
+    bool "arm_virt" if PLATFORM_QEMU_ARM_VIRT_CM7
+
+config PRODUCT_QEMU_ARM_MPS2_AN386
+    bool "arm_mps2_an386" if PLATFORM_QEMU_ARM_VIRT_CM4
+
+config PRODUCT_QEMU_RISCV32_VIRT
+    bool "riscv32_virt" if PLATFORM_QEMU_RISCV32_VIRT
+
+config PRODUCT_QEMU_CSKY_SMARTL_E802
+    bool "csky_smartl_e802" if PLATFORM_QEMU_CSKY_SMARTL
+
+config PRODUCT_QEMU_XTENSA_ESP32
+    bool "xtensa_esp32" if PLATFORM_QEMU_XTENSA_ESP32
+
+endchoice
+
+
+######################### config options of cpu arch ################
+source "arch/Kconfig"
+
+# Device Kconfig import
+osource "$(DEVICE_PATH)/Kconfig"
+
+config SOC_COMPANY
+    string "SoC company name to locate soc build path"
+    help
+      This option specifies the SoC company name, used to locate the build path for soc. This option is set by the
+      SoC's Kconfig file, and should be exactly the same with SoC company path, and the user should generally avoid
+       modifying it via the menu configuration.
+
+orsource "../../device/board/*/Kconfig.liteos_m.shields"
+
+orsource "../../device/board/$(BOARD_COMPANY)/Kconfig.liteos_m.defconfig.boards"
+
+choice
+    prompt "Board Selection"
+
+orsource "../../device/board/$(BOARD_COMPANY)/Kconfig.liteos_m.boards"
+
+endchoice
+
+orsource "../../device/soc/*/Kconfig.liteos_m.defconfig"
+
+choice
+    prompt "SoC Series Selection"
+
+orsource "../../device/soc/*/Kconfig.liteos_m.series"
+
+endchoice
+
+orsource "../../device/soc/*/Kconfig.liteos_m.soc"
+
+config QUICK_START
+    bool "Enable QUICK_START"
+    default n
+    depends on DRIVERS && FS_VFS
+    help
+      Answer Y to enable LiteOS support quick start.
+endmenu
+
+######################### config options of kernel #####################
+menu "Kernel"
+
+######################### config options of extended #####################
+
+config KERNEL_EXTKERNEL
+    bool "Enable Extend Kernel"
+    default y
+    help
+      This option will enable extend Kernel of LiteOS.  Extend kernel include
+      cppsupport, cpup, etc. You can select one or some
+      of them.
+
+config KERNEL_BACKTRACE
+    bool "Enable Backtrace"
+    default n
+    depends on KERNEL_EXTKERNEL
+    help
+      If you wish to build LiteOS with support for backtrace.
+
+choice
+    prompt "Select Backtrace Type"
+    depends on KERNEL_BACKTRACE
+
+config BACKTRACE_TYPE_1
+    bool "1: Call stack analysis for cortex-m series by scanning the stack"
+    depends on ARCH_ARM && !ARCH_ARM9
+
+config BACKTRACE_TYPE_2
+    bool "2: Call stack analysis for risc-v by using frame pointer"
+    depends on ARCH_RISCV
+
+config BACKTRACE_TYPE_3
+    bool "3: Call stack analysis for risc-v by scanning the stack"
+    depends on ARCH_RISCV
+
+config BACKTRACE_TYPE_4
+    bool "4: Call stack analysis for xtensa by scanning the stack"
+    depends on ARCH_XTENSA
+
+config BACKTRACE_TYPE_5
+    bool "5: Call stack analysis for c-sky by scanning the stack"
+    depends on ARCH_CSKY
+
+config BACKTRACE_TYPE_6
+    bool "6: Call stack analysis for arm9 by scanning the stack"
+    depends on ARCH_ARM9
+
+endchoice
+
+config BACKTRACE_TYPE
+    int
+    default 0 if ! KERNEL_BACKTRACE
+    default 1 if BACKTRACE_TYPE_1
+    default 2 if BACKTRACE_TYPE_2
+    default 3 if BACKTRACE_TYPE_3
+    default 4 if BACKTRACE_TYPE_4
+    default 5 if BACKTRACE_TYPE_5
+    default 6 if BACKTRACE_TYPE_6
+
+config BACKTRACE_DEPTH
+    int "Backtrace depth"
+    default 15
+    depends on KERNEL_BACKTRACE
+
+config KERNEL_CPPSUPPORT
+    bool "Enable C++ Support"
+    default n
+    depends on KERNEL_EXTKERNEL
+    help
+      If you wish to build LiteOS with support for C++.
+
+config BASE_CORE_CPUP
+    bool
+    default n
+
+config KERNEL_CPUP
+    bool "Enable Cpup"
+    default n
+    depends on KERNEL_EXTKERNEL
+    select BASE_CORE_CPUP
+    help
+      If you wish to build LiteOS with support for cpup.
+
+config CPUP_INCLUDE_IRQ
+    bool "Enable Cpup include irq"
+    default y
+    depends on KERNEL_CPUP
+    help
+      If you wish to include irq usage for cpup.
+
+config DYNLINK
+    bool "Enable Dynamic Link Feature"
+    default n
+    depends on KERNEL_EXTKERNEL && ARCH_ARM
+    help
+      If you wish to build LiteOS with support for dynamic link.
+
+config KERNEL_PM
+    bool "Enable Power Management"
+    default n
+    depends on KERNEL_EXTKERNEL
+    help
+      Configuration item for low power frame tailoring.
+      If you wish to build LiteOS with support for power management.
+
+config KERNEL_PM_TASK_PTIORITY
+    int "Power Management Task Priority"
+    default 1
+    range 1 31
+    depends on KERNEL_PM
+    help
+      Configuration item for priority of low-power task.
+
+config KERNEL_PM_TASK_STACKSIZE
+    int "Power Management Task Stack Size"
+    default 1024
+    depends on KERNEL_PM
+    help
+      Configuration item for stack size of low-power task.
+
+config KERNEL_PM_DEBUG
+    bool "Power Management Debug"
+    default n
+    depends on KERNEL_PM
+    help
+      Configuration item for low power frame debug tailoring.
+
+config DEBUG_HOOK
+    bool
+    default n
+
+config PLATFORM_EXC
+    bool "Enable Hook Feature"
+    default n
+    depends on KERNEL_EXTKERNEL
+    select DEBUG_HOOK
+
+config KERNEL_LMK
+    bool "Enable Low Memory Killer"
+    default n
+    depends on KERNEL_EXTKERNEL
+    help
+      Configuration item for low momery killer tailoring.
+      If you wish to build LiteOS with support for low memory killer.
+
+config KERNEL_LMK_DEBUG
+    bool "Low Memory Killer Debug"
+    default n
+    depends on KERNEL_LMK
+    help
+      Configuration item forlow memory killer debug tailoring.
+
+######################### config options of trace #########################
+source "components/trace/Kconfig"
+
+######################### config options of lms #########################
+source "components/lms/Kconfig"
+
+endmenu
+
+######################### config options of lib ########################
+menu "Lib"
+config LIB_LIBC
+    bool "Enable Libc"
+    default y
+    help
+      Answer Y to enable libc for full code.
+
+endmenu
+
+
+######################### config options of compatibility ##############
+menu "Compat"
+
+rsource "kal/Kconfig"
+
+endmenu
+
+######################## config options of filesystem ##################
+menu "FileSystem"
+
+rsource "components/fs/Kconfig"
+
+endmenu
+
+######################## config options of net ############################
+menu "Net"
+config NET_LWIP
+    bool "Enable Lwip"
+    default n
+    select NET_LWIP_SACK
+
+    help
+      Answer Y to enable LiteOS support lwip.
+
+config NET_LWIP_SACK
+    bool
+    default n
+
+endmenu
+
+######################## config options of debug ########################
+menu "Debug"
+config GDB
+    bool "Enable gdb functions"
+    default n
+    help
+      Answer Y to enable gdb functions.
+
+config PLATFORM_ADAPT
+    bool "Enable Os_adapt"
+    default y
+    help
+      Answer Y to add os_adapt.c to LiteOS.
+
+config ENABLE_OOM_LOOP_TASK
+    bool "Enable Oom loop task"
+    default n
+    depends on KERNEL_VM
+    help
+      Answer Y to enable oom loop kthread to check system out of memory.
+
+config DO_ALIGN
+    bool "Enable do align for hi3518e"
+    default y
+    depends on PLATFORM_HI3518EV200
+    help
+      Answer Y to enable do align for hi3518e.
+
+
+config ENABLE_MAGICKEY
+    bool "Enable MAGIC KEY"
+    default y
+    help
+      Answer Y to enable LiteOS Magic key.
+        ctrl + r : Magic key check switch;
+        ctrl + z : Show all magic op key;
+        ctrl + t : Show task information;
+        ctrl + p : System panic;
+        ctrl + e : Check system memory pool.
+
+config THUMB
+    bool "Enable Thumb"
+    default n
+    depends on ARCH_ARM
+    help
+      Answer Y to build thumb version.  This will make LiteOS smaller.
+
+config PLATFORM_DVFS
+    bool "Enable Dvfs"
+    default n
+    depends on  COMPAT_LINUXKPI
+    help
+      Answer Y to enable LiteOS support dynamic voltage and frequency scaling feature for
+      low power consumption.
+
+config SAVE_EXCINFO
+    bool "Enable Saving Exception Information"
+    default n
+    help
+      Answer Y to enable LiteOS support saving exception information to storage medium.
+
+config DEBUG_VERSION
+    bool "Enable a Debug Version"
+    default y
+    help
+      If you do not select this option that means you enable a release version for LiteOS.
+      It also means you do not want to use debug modules, like shell,telnet,tftp,nfs and
+      memory check, etc.
+      If you select this option that means you enable a debug version for LiteOS.
+      That means you want a opposite behaviour compared to release version.
+
+config DEBUG_KERNEL
+    bool "Enable Debug LiteOS Kernel Resource"
+    default n
+    depends on DEBUG_VERSION
+    help
+      If you select this option that means you enable debugging kernel resource.
+      It also means you want to get queue, mutex, semaphore, memory debug information.
+      That means you want a opposite behaviour compared to release version.
+
+config DEBUG_QUEUE
+    bool "Enable Queue Debugging"
+    default n
+    depends on DEBUG_KERNEL
+    help
+      Answer Y to enable debug queue.
+
+config DEBUG_DEADLOCK
+    bool "Enable Mutex Deadlock Debugging"
+    default n
+    depends on DEBUG_KERNEL
+    help
+      Answer Y to enable debug mutex deadlock.
+
+config DEBUG_SEMAPHORE
+    bool "Enable Semaphore Debugging"
+    default n
+    depends on DEBUG_KERNEL
+    help
+      Answer Y to enable debug semaphore.
+
+source "components/shell/Kconfig"
+config NET_LWIP_SACK_TFTP
+    bool "Enable Tftp"
+    default y
+    depends on SHELL && NET_LWIP_SACK && DEBUG_VERSION
+    help
+      Answer Y to enable LiteOS support tftp cmd and tftp tool.
+osource "net/telnet/Kconfig"
+config SCHED_DEBUG
+    bool "Enable sched debug Feature"
+    default n
+    depends on DEBUG_VERSION
+    help
+      If you wish to build LiteOS with support for sched debug.
+
+config USER_INIT_DEBUG
+    bool "Enable user init Debug"
+    default n
+    depends on DEBUG_VERSION
+
+config SHELL_CMD_DEBUG
+    bool "Enable shell cmd Debug"
+    default n
+    depends on DEBUG_VERSION && SHELL
+
+config USB_DEBUG
+    bool "Enable USB Debug"
+    default n
+    depends on SHELL && DRIVERS_USB && DEBUG_VERSION
+    help
+      Answer Y to enable LiteOS support usb debug.
+      use shell command to open the specified debug level print.
+config MEM_DEBUG
+    bool "Enable MEM Debug"
+    default n
+    depends on DEBUG_VERSION
+    help
+      Answer Y to enable LiteOS support mem debug.
+
+config MEM_LEAKCHECK
+    bool "Enable Function call stack of Mem operation recorded"
+    default n
+    depends on DEBUG_VERSION && MEM_DEBUG
+    select KERNEL_BACKTRACE
+    help
+      Answer Y to enable record the LR of Function call stack of Mem operation, it can check the mem leak through the infomations of mem node.
+config BASE_MEM_NODE_INTEGRITY_CHECK
+    bool "Enable integrity check or not"
+    default n
+    depends on DEBUG_VERSION && MEM_DEBUG
+config MEM_WATERLINE
+    bool "Enable memory pool waterline or not"
+    default n
+    depends on DEBUG_VERSION && MEM_DEBUG
+
+config VM_OVERLAP_CHECK
+    bool "Enable VM overlap check or not"
+    default n
+    depends on DEBUG_VERSION && MEM_DEBUG
+    help
+      Answer Y to enable vm overlap check.
+
+endmenu
+
+######################## config options os drivers ########################
+menu "Driver"
+source "drivers/Kconfig"
+endmenu
+
+######################## config options os security #######################
+menu "Security"
+osource "security/Kconfig"
+config SECURE_TRUSTZONE
+    bool "Enable ARM TrustZone"
+    default n
+    depends on ARCH_ARM
+config SECURE_HEAP_SIZE
+    int "TrustZone Heap Size (bytes)"
+    default 2048
+    depends on SECURE_TRUSTZONE
+config SECURE_STACK_DEFAULT_SIZE
+    int "TrustZone Stack Size (bytes)"
+    default 512
+    depends on SECURE_TRUSTZONE
+    help
+      The secure stack must be allocated before the task calls non-secure functions.
+endmenu
+
+menu "Test"
+config TEST
+    bool
+    default n
+config KERNEL_TEST
+    bool "Enable Kernel Test"
+    default n
+    select TEST
+config KERNEL_TEST_FULL
+    bool "Full Kernel Test"
+    default n
+    depends on KERNEL_TEST
+endmenu
+
+menu "Stack Smashing Protector (SSP) Compiler Feature"
+
+choice
+    prompt "Enable stack buffer overflow detection"
+    default  CC_STACKPROTECTOR_STRONG
+    ---help---
+    This option turns on the -fstack-protector GCC feature. This
+    feature puts, at the beginning of functions, a canary value on
+    the stack just before the return address, and validates
+    the value just before actually returning.  Stack based buffer
+    overflows (that need to overwrite this return address) now also
+    overwrite the canary, which gets detected and the attack is then
+    neutralized via a kernel panic.
+
+    This feature requires gcc version 4.2 or above, or a distribution
+    gcc with the feature backported. Older versions are automatically
+    detected and for those versions, this configuration option is
+    ignored. (and a warning is printed during bootup)
+
+config CC_NO_STACKPROTECTOR
+    bool "-fno-stack-protector"
+
+config CC_STACKPROTECTOR
+    bool "-fstack-protector"
+
+config CC_STACKPROTECTOR_STRONG
+    bool "-fstack-protector-strong"
+
+config CC_STACKPROTECTOR_ALL
+    bool "-fstack-protector-all"
+
+endchoice
+
+endmenu

Makefile

@@ -0,0 +1,122 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+LITEOSTOPDIR := $(realpath $(dir $(lastword $(MAKEFILE_LIST))))
+export LITEOSTOPDIR
+
+LITEOS_TARGET = liteos
+HIDE := @
+KCONFIG_CMDS := $(notdir $(wildcard $(dir $(shell which menuconfig))*config))
+
+ohos_kernel ?= liteos_m
+$(foreach line,$(shell hb env | sed 's/\[OHOS INFO\]/ohos/g;s/ /_/g;s/:_/=/g' || true),$(eval $(line)))
+ifneq ($(ohos_kernel),liteos_m)
+$(error The selected product ($(ohos_product)) is not a liteos_m kernel type product)
+endif
+
+ifeq ($(PRODUCT_PATH),)
+PRODUCT_PATH:=$(ohos_product_path)
+endif
+
+ifeq ($(DEVICE_PATH),)
+DEVICE_PATH:=$(ohos_device_path)
+endif
+
+ifeq ($(BOARD_COMPANY),)
+BOARD_COMPANY:=$(ohos_device_company)
+endif
+
+ifeq ($(TEE:1=y),y)
+tee = _tee
+endif
+ifeq ($(RELEASE:1=y),y)
+CONFIG ?= $(PRODUCT_PATH)/kernel_configs/release$(tee).config
+else
+CONFIG ?= $(PRODUCT_PATH)/kernel_configs/debug$(tee).config
+endif
+
+KCONFIG_CONFIG ?= $(CONFIG)
+LITEOS_MENUCONFIG_H ?= $(LITEOSTOPDIR)/config.h
+LITEOS_CONFIG_FILE ?= $(LITEOSTOPDIR)/.config
+
+# export los_config.mk related environment variables
+export LITEOS_MENUCONFIG_H
+export LITEOS_CONFIG_FILE
+export BOARD_COMPANY
+export DEVICE_PATH
+export PRODUCT_PATH
+
+# export kconfig related environment variables
+export CONFIG_=LOSCFG_
+export srctree=$(LITEOSTOPDIR)
+
+-include $(LITEOS_CONFIG_FILE)
+
+define HELP =
+Usage: make [TARGET]... [PARAMETER=VALUE]...
+
+Targets:
+    help:       display this help and exit
+    clean:      clean compiled objects
+    cleanall:   clean all build outputs
+    all:        do build (Default target)
+    update_config:  update product kernel config (use menuconfig)
+    xxconfig:   invoke xxconfig command of kconfiglib (xxconfig is one of $(KCONFIG_CMDS))
+
+Parameters:
+    TEE:        boolean value(1 or y for true), enable tee
+    RELEASE:    boolean value(1 or y for true), build release version
+    CONFIG:     kernel config file to be use
+    args:       arguments for xxconfig command
+endef
+export HELP
+
+all:
+	$(HIDE)hb build -f --gn-args "liteos_kernel_only=true liteos_name=\"$(LITEOS_TARGET)\""
+
+help:
+	$(HIDE)echo "$$HELP"
+
+$(filter-out menuconfig,$(KCONFIG_CMDS)):
+	$(HIDE)$@ $(args)
+
+$(LITEOS_CONFIG_FILE): $(KCONFIG_CONFIG)
+	$(HIDE)env KCONFIG_CONFIG=$< genconfig --config-out $@ --header-path $(LITEOS_MENUCONFIG_H)
+
+update_config menuconfig:
+	$(HIDE)test -f "$(CONFIG)" && cp -v "$(CONFIG)" .config && menuconfig $(args) && savedefconfig --out "$(CONFIG)"
+
+clean:
+	$(HIDE)hb clean
+	$(HIDE)echo "clean $(LOSCFG_PLATFORM) finish"
+
+cleanall: clean
+	$(HIDE)echo "clean all done"
+
+.PHONY: all clean cleanall help update_config $(KCONFIG_CMDS) $(KCONFIG_CONFIG)

OAT.xml

@@ -29,11 +29,11 @@
         </policylist>
         <filefilterlist>
             <filefilter name="defaultFilter" desc="文件属于FreeBSD仓库软连接，本仓库屏蔽告警，在FreeBSD仓库进行处理">
-                <filteritem type="filepath" name="kernel/arch/risc-v/nuclei/gcc/nmsis/Library/.*" desc="文件属于三方芯片的二进制代码，属于社区贡献，不用提供额外的说明"/>
+                <filteritem type="filepath" name="arch/risc-v/nuclei/gcc/nmsis/Library/.*" desc="文件属于三方芯片的二进制代码，属于社区贡献，不用提供额外的说明"/>
                 <filteritem type="filepath" name="targets/riscv_nuclei_demo_soc_gcc/.*" desc="文件属于nuclei三方芯片的源代码，文件头说明跟随liteos_m/LICENSE，不用额外说明"/>
                 <filteritem type="filepath" name="targets/riscv_nuclei_gd32vf103_soc_gcc/.*" desc="文件属于nuclei三方芯片的源代码，文件头说明跟随liteos_m/LICENSE，不用额外说明"/>
                 <filteritem type="filepath" name="NOTICE" desc="NOTICE文件"/>
-                <filteritem type="filepath" name="kernel/arch/risc-v/nuclei" desc="该文件的license为apache 2.0符合"/>
+                <filteritem type="filepath" name="arch/risc-v/nuclei" desc="该文件的license为apache 2.0符合"/>
             </filefilter>
             <filefilter name="defaultFilter" desc="Files not to check">
                 <!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->

README.md

@@ -1,77 +1,134 @@
-# LiteOS Cortex-M<a name="EN-US_TOPIC_0000001096757661"></a>
+# LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a>
 
 -   [Introduction](#section11660541593)
 -   [Directory Structure](#section161941989596)
 -   [Constraints](#section119744591305)
 -   [Usage](#section3732185231214)
+-   [Contribution](#section1371123476307)
 -   [Repositories Involved](#section1371113476307)
 
 ## Introduction<a name="section11660541593"></a>
 
-The OpenHarmony LiteOS Cortex-M is the kernel designed for the lightweight operating system \(OS\) for the Internet of Things \(IoT\) field. It features small size, low power consumption, and high performance. In addition, it has a simple code structure, including the minimum kernel function set, kernel abstraction layer, optional components, and project directory, and is divided into the hardware-related and hardware-irrelevant layers. The hardware-related layers provide unified hardware abstraction layer \(HAL\) interfaces to improve hardware adaptability. The combination and classification of different compilation toolchains and chip architectures meet the requirements of the Artificial Intelligence of Things \(AIoT\) field for rich hardware and compilation toolchains.  [Figure1](#fig0865152210223)  shows the architecture of the OpenHarmony LiteOS Cortex-M kernel.
+OpenHarmony LiteOS-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It features small footprint, low power consumption, and high performance. It has a simple code structure, including the minimum kernel function set, kernel abstraction layer, optional components, and project directory. The LiteOS-M kernel is divided into the hardware layer and hardware-irrelevant layers. The hardware layer provides a unified hardware abstraction layer (HAL) interface for easier hardware adaptation. A range of compilation toolchains can be used with different chip architectures to meet the expansion of diversified hardware and compilation toolchains in the Artificial Intelligence of Things (AIoT) field.
+**Figure1** shows the architecture of the LiteOS-M kernel.
 
-**Figure  1**  Architecture of OpenHarmony the LiteOS Cortex-M kernel<a name="fig0865152210223"></a>  
-![](figures/architecture-of-openharmony-the-liteos-cortex-m-kernel.png "architecture-of-openharmony-the-liteos-cortex-m-kernel")
+**Figure 1** Architecture of the OpenHarmony LiteOS-M kernel<a name="fig0865152210223"></a>
+
+![](figures/architecture-of-openharmony-the-liteos-cortex-m-kernel.png "OpenHarmony-LiteOS-M Kernel Architecture")
 
 ## Directory Structure<a name="section161941989596"></a>
 
-The directory structure is listed as below, for the detailed directories, please refer to [arch_spec.md](arch_spec.md).
+The directory structure is as follows. For more details, see [arch_spec.md](arch_spec.md).
 
 ```
 /kernel/liteos_m
+├── arch                 # Code of the kernel instruction architecture layer
+│   ├── arm              # Code of the ARM32 architecture
+│   │   ├── arm9         # Code of the ARM9 architecture
+│   │   ├── cortex-m3    # Code of the cortex-m3 architecture
+│   │   ├── cortex-m33   # Code of the cortex-m33 architecture
+│   │   ├── cortex-m4    # Code of the cortex-m4 architecture
+│   │   ├── cortex-m7    # Code of the cortex-m7 architecture
+│   │   └── include      # Arm architecture public header file directory
+│   ├── csky             # Code of the csky architecture
+│   │   └── v2           # Code of the csky v2 architecture
+│   ├── include          # APIs exposed externally
+│   ├── risc-v           # Code of the risc-v architecture
+│   │   ├── nuclei       # Code of the nuclei system technology risc-v architecture
+│   │   └── riscv32      # Code of the risc-v architecture
+│   └── xtensa           # Code of the xtensa architecture
+│       └── lx6          # Code of the lx6 xtensa architecture
 ├── components           # Optional components
 │   ├── backtrace        # Backtrace support
 │   ├── cppsupport       # C++ support
-│   ├── cpup             # CPU possession (CPUP)
-│   ├── dynlink          # Dynamic loader & linker
-│   ├── exchook          # Exception hook
-│   ├── fs               # File system
-│   └── net              # Network support
+│   ├── cpup             # CPU percent (CPUP)
+│   ├── dynlink          # Dynamic loading and linking
+│   ├── exchook          # Exception hooks
+│   ├── fs               # File systems
+│   ├── lmk              # Low memory killer functions
+│   ├── lms              # Lite memory sanitizer functions
+│   ├── net              # Networking functions
+│   ├── power            # Power management
+│   ├── shell            # Shell function
+│   ├── fs               # File systems
+│   └── trace            # Trace tool
+├── drivers              # driver Kconfig
 ├── kal                  # Kernel abstraction layer
-│   ├── cmsis            # CMSIS-compliant API support
+│   ├── cmsis            # CMSIS API support
 │   └── posix            # POSIX API support
-├── kernel               # Minimum function set support
-│   ├── arch             # Code of the kernel instruction architecture layer
-│   │   ├── arm          # Code of the ARM32 architecture
-│   │   └── include      # APIs exposed externally
+├── kernel               # Minimum kernel function set
 │   ├── include          # APIs exposed externally
-│   └── src              # Source code of the minimum function set of the kernel
+│   └── src              # Source code of the minimum kernel function set
 ├── targets              # Board-level projects
-├── utils                # Common code
+├── testsuites           # Kernel testsuites
+├── tools                # Kernel tools
+├── utils                # Common directory
 ```
 
 ## Constraints<a name="section119744591305"></a>
 
-Programming languages: C and C++
+OpenHarmony LiteOS-M supports only C and C++.
 
-Currently applicable architectures: Cortex-M3, Cortex-M4, Cortex-M7, and RISC-V
+Applicable architecture: See the directory structure for the arch layer.
+
+As for dynamic loading module, the shared library to be loaded needs signature verification or source restriction to ensure security.
 
 ## Usage<a name="section3732185231214"></a>
 
-LiteOS Cortex-M provides projects for three chip architectures, which are located in the  **targets**  directory. The methods of compiling and using these projects are as follows:
+The OpenHarmony LiteOS-M kernel build system is a modular build system based on Generate Ninja (GN) and Ninja. It supports module-based configuration, tailoring, and assembling, and helps you build custom products. This document describes how to build a LiteOS-M project based on GN and Ninja. For details about the methods such as GCC+gn, IAR, and Keil MDK, visit the community websites.
+
+### Setting Up the Environment
+
+Before setting up the environment for a development board, you must set up the basic system environment for OpenHarmony first. The basic system environment includes the OpenHarmony build environment and development environment. For details, see [Setting Up Development Environment](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/quick-start/quickstart-lite-env-setup.md).
+
+### Obtaining the OpenHarmony Source Code
+
+For details about how to obtain the source code, see [Source Code Acquisition](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/get-code/sourcecode-acquire.md). This document assumes that the clone directory is `~/openHarmony` after the complete OpenHarmony repository code is obtained.
+
+### Example projects that are already supported
+
+Qemu simulator: `arm_mps2_an386、esp32、riscv32_virt、SmartL_E802`, For details about how to compile and run, see [qemu guide](https://gitee.com/openharmony/device_qemu)
+
+Bestechnic: `bes2600`, For details about how to compile and run, see [Bestechnic developer guide](https://gitee.com/openharmony/device_soc_bestechnic)
+
+### Community Porting Project Links
+
+The LiteOS-M kernel porting projects for specific development boards are provided by community developers. The following provides the links to these projects. If you have porting projects for more development boards, you can provide your links to share your projects.
 
 -   Cortex-M3:
 
-The  **kernel/liteos\_m/targets/cortex-m3\_stm32f103\_simulator\_keil**  directory is the Keil project directory created based on the STM32F103 chip architecture. You can download and install Keil development tools from the Internet. To compile the Cortex-M3 project, go to the  **cortex-m3\_stm32f103\_simulator\_keil/project**  directory and double-click the  **los\_demo.uvproj**  file to open the desired project. After the compilation is successful, burn the file to the corresponding board using JLINK or STM32 ST-LINK Utility.
+    - STM32F103 https://gitee.com/rtos_lover/stm32f103_simulator_keil
+
+        This repository provides the Keil project code for building the OpenHarmony LiteOS-M kernel based on the STM32F103 chip architecture. This code supports build in Keil MDK mode.
 
 -   Cortex-M4:
 
-The  **kernel/liteos\_m/targets/cortex-m4\_stm32f429ig\_fire-challenger\_iar**  directory is the IAR project directory created based on the STM32F429IG chip architecture. You can download and install IAR development tools from the Internet. To compile the Cortex-M4 project, go to the  **cortex-m4\_stm32f429ig\_fire-challenger\_iar/project**  directory and double-click the  **los\_demo.eww**  file to open the desired project. After the compilation is successful, burn the file to the corresponding board using JLINK or STM32 ST-LINK Utility.
+    - STM32F429IGTb https://gitee.com/harylee/stm32f429ig_firechallenger
+
+        This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the STM32F429IGTb development board. The code supports build in Ninja, GCC, and IAR modes.
 
 -   Cortex-M7:
 
-The  **kernel/liteos\_m/targets/cortex-m7\_nucleo\_f767zi\_gcc**  directory is the Makefile project directory created based on the STM32F767ZI chip architecture. The compilation commands are as follows:
+    - Nucleo-F767ZI https://gitee.com/harylee/nucleo_f767zi
 
-```
-cd kernel/liteos_m/targets/cortex-m7_nucleo_f767zi_gcc
-make clean; make
-```
+        This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the Nucleo-F767ZI development board. The code supports build in Ninja, GCC, and IAR modes.
 
-After the compilation is successful, the executable file  **NUCLEO-F767.hex**  is generated in the  **cortex-m7\_nucleo\_f767zi\_gcc/build**  directory. Burn the file to the corresponding board using STM32 ST-LINK Utility.
+## Contribution<a name="section1371123476307"></a>
+
+[How to involve](https://gitee.com/openharmony/docs/blob/HEAD/en/contribute/contribution.md)
+
+[Commit message spec](https://gitee.com/openharmony/kernel_liteos_m/wikis/Commit%20message%E8%A7%84%E8%8C%83)
+
+[Liteos-M kernel coding style guide](https://gitee.com/openharmony/kernel_liteos_m/wikis/OpenHarmony%E8%BD%BB%E5%86%85%E6%A0%B8%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83)
+
+How to contribute a chip based on Liteos-M kernel:
+
+[ Board-Level Directory Specifications](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-chip-board-overview.md)
+
+[Mini System SoC Porting Guide](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-minichip.md)
 
 ## Repositories Involved<a name="section1371113476307"></a>
 
-[Kernel subsystem](https://gitee.com/openharmony/docs/blob/master/en/readme/kernel.md)
+[Kernel Subsystem](https://gitee.com/openharmony/docs/blob/HEAD/en/readme/kernel-subsystem.md)
 
 **kernel\_liteos\_m**
-

README_zh.md

@@ -4,6 +4,7 @@
 -   [目录](#section161941989596)
 -   [约束](#section119744591305)
 -   [使用说明](#section3732185231214)
+-   [贡献](#section1371123476307)
 -   [相关仓](#section1371113476307)
 
 ## 简介<a name="section11660541593"></a>
@@ -19,24 +20,45 @@ OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系
 
 ```
 /kernel/liteos_m
+├── arch                 # 内核指令架构层目录
+│   ├── arm              # arm 架构代码
+│   │   ├── arm9         # arm9 架构代码
+│   │   ├── cortex-m3    # cortex-m3架构代码
+│   │   ├── cortex-m33   # cortex-m33架构代码
+│   │   ├── cortex-m4    # cortex-m4架构代码
+│   │   ├── cortex-m7    # cortex-m7架构代码
+│   │   └── include      # arm架构公共头文件目录
+│   ├── csky             # csky架构代码
+│   │   └── v2           # csky v2架构代码
+│   ├── include          # 架构层对外接口存放目录
+│   ├── risc-v           # risc-v 架构
+│   │   ├── nuclei       # 芯来科技risc-v架构代码
+│   │   └── riscv32      # risc-v官方通用架构代码
+│   └── xtensa           # xtensa 架构代码
+│       └── lx6          # xtensa lx6架构代码
 ├── components           # 可选组件
-│   ├── backtrace        # 回溯栈支持
+│   ├── backtrace        # 栈回溯功能
 │   ├── cppsupport       # C++支持
 │   ├── cpup             # CPUP功能
 │   ├── dynlink          # 动态加载与链接
 │   ├── exchook          # 异常钩子
 │   ├── fs               # 文件系统
-│   └── net              # Network功能
+│   ├── lmk              # Low memory killer 机制
+│   ├── lms              # Lite memory sanitizer 机制
+│   ├── net              # Network功能
+│   ├── power            # 低功耗管理
+│   ├── shell            # shell功能
+│   └── trace            # trace 工具
+├── drivers              # 驱动框架Kconfig
 ├── kal                  # 内核抽象层
 │   ├── cmsis            # cmsis标准接口支持
 │   └── posix            # posix标准接口支持
 ├── kernel               # 内核最小功能集支持
-│   ├── arch             # 内核指令架构层代码
-│   │   ├── arm          # arm32架构的代码
-│   │   └── include      # 对外接口存放目录
 │   ├── include          # 对外接口存放目录
 │   └── src              # 内核最小功能集源码
 ├── targets              # 板级工程目录
+├── testsuites           # 内核测试用例
+├── tools                # 内核工具
 ├── utils                # 通用公共目录
 ```
 
@@ -44,58 +66,28 @@ OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系
 
 开发语言：C/C++；
 
-适用架构：当前只适用于cortex-m3、cortex-m4、cortex-m7、risc-v芯片架构。
+适用架构：详见目录结构arch层。
+
+动态加载模块：待加载的共享库需要验签或者限制来源，确保安全性。
 
 ## 使用说明<a name="section3732185231214"></a>
 
-OpenHarmony LiteOS-M内核的编译构建系统是一个基于gn和ninja的组件化构建系统，支持按组件配置、裁剪和拼装，按需构建出定制化的产品。本文主要介绍如何基于gn和ninja编译LiteOS-M工程，GCC+Makefile、IAR、Keil MDK等编译方式可以参考社区爱好者贡献的站点。
+OpenHarmony
+LiteOS-M内核的编译构建系统是一个基于gn和ninja的组件化构建系统，支持按组件配置、裁剪和拼装，按需构建出定制化的产品。本文主要介绍如何基于gn和ninja编译LiteOS-M工程，GCC+gn、IAR、Keil MDK等编译方式可以参考社区爱好者贡献的站点。
 
 ### 搭建系统基础环境
 
-在搭建各个开发板环境前，需要完成OpenHarmony系统基础环境搭建。系统基础环境主要是指OpenHarmony的编译环境和开发环境，详细介绍请参考官方站点[Ubuntu编译环境准备](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/quick-start/quickstart-lite-env-setup-linux.md)。开发者需要根据环境搭建文档，完成下述软件的安装：Python3.7+、gn、ninja、hb。对于LiteOS-M内核，还需要安装Make构建工具和[ARM GCC编译工具链](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads)。
+在搭建各个开发板环境前，需要完成OpenHarmony系统基础环境搭建。系统基础环境主要是指OpenHarmony的编译环境和开发环境，详细介绍请参考官方站点[开发环境准备](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/quick-start/quickstart-lite-env-setup.md)。开发者需要根据环境搭建文档完成环境搭建。
 
 ### 获取OpenHarmony源码
 
-开发者需要在Linux服务器上通过Git克隆获取OpenHarmony最新源码，详细的源码获取方式，请见[源码获取](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/get-code/sourcecode-acquire.md)。获取OpenHarmony完整仓代码后，假设克隆目录为`~/openHarmony`。
+详细的源码获取方式，请见[源码获取](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/get-code/sourcecode-acquire.md)。获取OpenHarmony完整仓代码后，假设克隆目录为`~/openHarmony`。
 
-### 获取示例工程源码
+### 已支持的示例工程
 
-以开发板Nucleo-F767Zi为例，演示如何编译运行`OpenHarmony LiteOS-M`内核工程。在本地目录，执行下述命令克隆示例代码。
+Qemu模拟器: `arm_mps2_an386、esp32、riscv32_virt、SmartL_E802`, 编译运行详见: [Qemu指导](https://gitee.com/openharmony/device_qemu)
 
-```
-git clone https://gitee.com/harylee/nucleo_f767zi.git
-```
-
-假设克隆到的代码目录为`~/nucleo_f767zi`。 执行如下命令把代码目录的`device`、`vendor`目录复制到`openHarmony`工程的相应目录。
-
-```
-mkdir ~/openHarmony/device/st
-
-cp -r ~/nucleo_f767zi/device/st/nucleo_f767zi ~/openHarmony/device/st/nucleo_f767zi
-
-chmod +x ~/openHarmony/device/st/nucleo_f767zi/build.sh
-
-cp -r ~/nucleo_f767zi/vendor/st ~/openHarmony/vendor/st
-```
-
-关于示例代码目录的说明，可以参考资料站点[板级目录规范](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/transplant-chip-board-overview.md)。如果需要自行移植开发板，请参考[板级系统移植](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/transplant-chip-board.md)。
-
-### 编译运行
-
-编译运行前，交叉编译工具链`bin`目录配置到`PATH`环境变量中或者配置`device/st/nucleo_f767zi/liteos_m/config.gni`文件中`board_toolchain_path`配置项为交叉编译工具链`bin`目录。
-在`OpenHarmony`根目录，执行`hb set`设置产品路径，选择`nucleo_f767zi`产品，然后执行`hb build`开启编译。如下：
-
-```
-user@dev:~/OpenHarmony$ hb set
-
-[OHOS INFO] Input code path: # 直接按回车，然后选择nucleo_f767zi产品即可
-
-OHOS Which product do you need? nucleo_f767zi@st
-
-user@dev:~/OpenHarmony$ hb build
-```
-
-最终的镜像生成在`~/openHarmony/out/nucleo_f767zi/`目录中，通过`STM32 ST-LINK Utility`软件将镜像文件下载至单板查看运行效果。
+恒玄科技: `bes2600`, 编译运行详见: [恒玄开发指导](https://gitee.com/openharmony/device_soc_bestechnic)
 
 ### 社区移植工程链接
 
@@ -119,9 +111,25 @@ LiteOS-M内核移植的具体开发板的工程由社区开发者提供，可以
 
         该仓包含OpenHarmony LiteOS-M内核移植支持`Nucleo-F767ZI`开发板的工程代码，支持Ninja、GCC、IAR等方式进行编译。
 
+## 贡献<a name="section1371123476307"></a>
+
+[如何贡献](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/contribute/%E5%8F%82%E4%B8%8E%E8%B4%A1%E7%8C%AE.md)
+
+[Commit message规范](https://gitee.com/openharmony/kernel_liteos_m/wikis/Commit%20message%E8%A7%84%E8%8C%83)
+
+[Liteos-M 内核编码规范](https://gitee.com/openharmony/kernel_liteos_m/wikis/OpenHarmony%E8%BD%BB%E5%86%85%E6%A0%B8%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83)
+
+如何基于Liteos-M内核贡献一款芯片:
+
+[板级目录规范](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/porting/porting-chip-board-overview.md)
+
+[轻量系统芯片移植指导](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/porting-minichip.md)
+
+[轻量系统芯片移植案例](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/porting-minichip-cases.md)
+
 ## 相关仓<a name="section1371113476307"></a>
 
-[内核子系统](https://gitee.com/openharmony/docs/blob/master/zh-cn/readme/%E5%86%85%E6%A0%B8%E5%AD%90%E7%B3%BB%E7%BB%9F.md)
+[内核子系统](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/readme/%E5%86%85%E6%A0%B8%E5%AD%90%E7%B3%BB%E7%BB%9F.md)
 
 **kernel\_liteos\_m**
 

arch/BUILD.gn

@@ -0,0 +1,52 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+config("arch_config") {
+  include_dirs = [ "include" ]
+}
+
+module_group("arch") {
+  modules = []
+  if ("$board_cpu" == "arm9" || "$board_cpu" == "cortex-m3" ||
+      "$board_cpu" == "cortex-m4" || "$board_cpu" == "cortex-m7" ||
+      "$board_cpu" == "cortex-m33") {
+    modules += [ "arm" ]
+  } else if ("$board_cpu" == "ck802" || "$board_cpu" == "e802") {
+    modules += [ "csky" ]
+  } else if ("$board_cpu" == "") {
+    if ("$board_arch" == "rv32imac" || "$board_arch" == "rv32imafdc") {
+      modules += [ "risc-v" ]
+    } else if ("$board" == "esp32") {
+      modules += [ "xtensa" ]
+    }
+  }
+  configs = [ ":arch_config" ]
+}

arch/Kconfig

@@ -0,0 +1,53 @@
+config ARCH_ARM
+   bool
+
+rsource "arm/Kconfig"
+
+config ARCH_CSKY
+   bool
+
+config ARCH_RISCV
+   bool
+
+config ARCH_RISCV32
+   bool
+   select ARCH_RISCV
+
+config ARCH_XTENSA
+   bool
+
+comment "Extra Configurations"
+
+config ARCH_FPU_DISABLE
+    bool "Disable Floating Pointer Unit"
+    default n
+    help
+      This option will bypass floating procedure in system.
+
+config ARCH_SECURE_MONITOR_MODE
+    bool "Run On Secure Monitor Mode"
+    default n
+    depends on ARCH_ARM_AARCH64
+    help
+      This option will make the system run on EL3.
+
+config ARCH_INTERRUPT_PREEMPTION
+    bool "Enable Interrupt Preemption"
+    default n
+    depends on ARCH_ARM_AARCH64
+    help
+      This option will support high priority interrupt preemption.
+
+config IRQ_USE_STANDALONE_STACK
+    bool "Use Interrupt Stack"
+    default y
+    depends on ARCH_ARM_AARCH64 || ARCH_ARM_AARCH32
+    help
+      This option will support using standalone interrupt stack.
+
+config ARCH_UNALIGNED_EXC
+    bool "Enable Unaligned Exception"
+    default y
+    depends on ARCH_ARM
+    help
+     This option will enable unaligned exception.

arch/arm/BUILD.gn

@@ -0,0 +1,39 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+config("arm_config") {
+  include_dirs = [ "include" ]
+}
+
+module_group("arm") {
+  modules = [ "$board_cpu/gcc" ]
+  configs = [ ":arm_config" ]
+}

arch/arm/Kconfig

@@ -0,0 +1,108 @@
+# ARM Architecture
+
+#
+# ARM has 32-bit(Aarch32) and 64-bit(Aarch64) implementations
+#
+config ARCH_ARM_AARCH32
+    bool
+    select ARCH_ARM
+    help
+      32-bit ARM architecture implementations, Except the M-profile.
+      It is not limited to ARMv7-A but also ARMv7-R, ARMv8-A 32-bit and etc.
+
+#
+# Architecture Versions
+#
+config ARCH_ARM_V7M
+    bool
+
+config ARCH_ARM_V5TE
+    bool
+
+config ARCH_ARM_VER
+    string
+    default "armv7-m" if ARCH_ARM_V7M
+    default "armv5te" if ARCH_ARM_V5TE
+
+#
+# VFP Hardware
+#
+config ARCH_FPU_VFP_V3
+    bool
+    help
+      An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
+      VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support code.
+
+config ARCH_FPU_VFP_V4
+    bool
+    help
+      An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
+      VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support code.
+      VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to the features of VFPv3.
+
+config ARCH_FPU_VFP_D16
+    bool
+    depends on ARCH_ARM_AARCH32
+    help
+      VPU implemented with 16 doubleword registers (16 x 64-bit).
+
+config ARCH_FPU_VFP_D32
+    bool
+    depends on ARCH_ARM_AARCH32
+    help
+      VPU implemented with 32 doubleword registers (32 x 64-bit).
+
+config ARCH_FPU_VFP_NEON
+    bool
+    help
+      Advanced SIMD extension (NEON) support.
+
+config ARCH_FPU
+    string
+    default "vfpv3"       if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D32
+    default "vfpv3-d16"   if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D16
+    default "neon-vfpv4"  if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32 && ARCH_FPU_VFP_NEON
+    default "vfpv4"       if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32
+    default "vfpv4-d16"   if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D16
+
+#
+# Supported Processor Cores
+#
+config ARCH_CORTEX_M3
+    bool
+    select ARCH_ARM_V7M
+    select ARCH_ARM_AARCH32
+
+config ARCH_CORTEX_M4
+    bool
+    select ARCH_ARM_V7M
+    select ARCH_ARM_AARCH32
+
+config ARCH_CORTEX_M7
+    bool
+    select ARCH_ARM_V7M
+    select ARCH_ARM_AARCH32
+    select ARCH_FPU_VFP_V4
+    select ARCH_FPU_VFP_D32
+    select ARCH_FPU_VFP_NEON
+
+config ARCH_CORTEX_M33
+    bool
+    select ARCH_ARM_V7M
+    select ARCH_ARM_AARCH32
+    select ARCH_FPU_VFP_V4
+    select ARCH_FPU_VFP_D32
+    select ARCH_FPU_VFP_NEON
+
+config ARCH_ARM9
+    bool
+    select ARCH_ARM_V5TE
+    select ARCH_ARM_AARCH32
+
+config ARCH_CPU
+    string
+    default "cortex-m3" if ARCH_CORTEX_M3
+    default "cortex-m4" if ARCH_CORTEX_M4
+    default "cortex-m7" if ARCH_CORTEX_M7
+    default "cortex-m33" if ARCH_CORTEX_M33
+    default "arm9" if ARCH_ARM9

arch/arm/arm9/gcc/BUILD.gn

@@ -27,9 +27,10 @@
 # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import("//kernel/liteos_m/config.gni")
+import("//kernel/liteos_m/liteos.gni")
 
-static_library("arch") {
+module_name = "arch"
+kernel_module(module_name) {
   sources = [
     "los_context.c",
     "los_dispatch.S",
@@ -38,6 +39,8 @@ static_library("arch") {
     "los_timer.c",
     "reset_vector.S",
   ]
-
-  configs += [ "$LITEOSTOPDIR:los_config" ]
+}
+
+config("public") {
+  include_dirs = [ "." ]
 }

arch/arm/arm9/gcc/los_arch_atomic.h

@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    LOS_IntRestore(intSave);
+    return *v;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicXchg32bits(Atomic *v, INT32 val)
+{
+    INT32 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(Atomic *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */
+

arch/arm/arm9/gcc/los_arch_interrupt.h

@@ -171,7 +171,7 @@ extern UINT32 g_intCount;
  */
 #define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_hwi
  * Set interrupt vector table.
@@ -282,7 +282,7 @@ typedef struct TagExcContext {
 
 typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
 VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
-VOID HalHwiInit();
+VOID HalHwiInit(VOID);
 
 /**
  * @ingroup los_exc
@@ -322,15 +322,18 @@ VOID HalHwiInit();
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/arm9/gcc/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/arm9/gcc/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,7 +73,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
     TaskContext *context = NULL;
     LosTaskCB *taskCB = OS_TCB_FROM_TID(taskID);
@@ -109,7 +102,7 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->r11 = 0x11111111L;
     context->r12 = 0x12121212L;
     context->sp = (UINTPTR)topStack + stackSize;
-    context->lr = (UINTPTR)HalSysExit;
+    context->lr = (UINTPTR)ArchSysExit;
 
     if ((UINTPTR)taskCB->taskEntry & 0x01) {
         context->pc = (UINTPTR)OsTaskEntryThumb;
@@ -122,7 +115,7 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();
@@ -131,7 +124,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
     return LOS_OK; /* never return */
 }
 
-LITE_OS_SEC_TEXT_INIT VOID HalTaskSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchTaskSchedule(VOID)
 {
     __asm__ __volatile__("swi 0");
 }

arch/arm/arm9/gcc/los_interrupt.c

@@ -64,7 +64,7 @@ ExcInfo g_excInfo = {0};
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -126,7 +126,7 @@ LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
     return (31 - CLZ(status));
 }
 
-inline UINT32 HalIsIntActive(VOID)
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -181,7 +181,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -201,7 +201,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -211,11 +211,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -232,7 +232,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
@@ -244,13 +244,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -414,7 +414,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************
@@ -431,7 +431,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
     UINT32 val;
 
     for (val = OS_SYS_VECTOR_CNT; val < OS_VECTOR_CNT; val++) {
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
         g_hwiForm[val].pfnHook = HalHwiDefaultHandler;
         g_hwiForm[val].uwParam = 0;
 #else
@@ -447,7 +447,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
     return;
 }
 
-UINT32 HalIntLock(VOID)
+UINT32 ArchIntLock(VOID)
 {
     UINT32 ret;
     UINT32 temp;
@@ -461,12 +461,12 @@ UINT32 HalIntLock(VOID)
     return ret;
 }
 
-VOID HalIntRestore(UINT32 intSave)
+VOID ArchIntRestore(UINT32 intSave)
 {
     __asm__ __volatile__("MSR CPSR_c, %0" : : "r"(intSave));
 }
 
-UINT32 HalIntUnLock(VOID)
+UINT32 ArchIntUnLock(VOID)
 {
     UINT32 intSave;
 

arch/arm/arm9/gcc/los_timer.c

@@ -29,8 +29,8 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "los_timer.h"
 #include "los_config.h"
-#include "los_sched.h"
 #include "los_arch_context.h"
 #include "los_arch_interrupt.h"
 #include "los_reg.h"
@@ -51,18 +51,31 @@
 #define OS_TIMER_READ_CTL_ADDR      (OS_TIMER_REG_BASE + 16)
 #define OS_TIMER_READ_VAL_ADDR      (OS_TIMER_REG_BASE + 20)
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = OS_TIMER_IRQ_NUM,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 intSave = LOS_IntLock();
     UINT32 value;
 
+    ArchTickTimer *tick = &g_archTickTimer;
+    tick->freq = OS_SYS_CLOCK;
+
     READ_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
     value &= ~(OS_TIMER_32K_CLK_BIT);
     WRITE_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
@@ -77,13 +90,13 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     value |= OS_TIMER_ENABLE; // Enable timer.
     WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
 
-    (VOID)HalHwiCreate(OS_TIMER_IRQ_NUM, 0, 0, (HWI_PROC_FUNC)handler, 0);
+    (VOID)ArchHwiCreate(OS_TIMER_IRQ_NUM, 0, 0, (HWI_PROC_FUNC)handler, 0);
     LOS_IntRestore(intSave);
 
     return LOS_OK;
 }
 
-STATIC VOID HalClockIrqClear(VOID)
+STATIC VOID SysTickClockIrqClear(VOID)
 {
     UINT32 mask = OS_TIMER_INT_MASK << OS_TIMER_INT_POS;
     UINT32 status;
@@ -94,15 +107,15 @@ STATIC VOID HalClockIrqClear(VOID)
     } while (status & mask);
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
-    HalTickLock();
+    SysTickLock();
     WRITE_UINT32(nextResponseTime, OS_TIMER_PERIOD_REG_ADDR);
-    HalClockIrqClear();
-    HalTickUnlock();
+    SysTickClockIrqClear();
+    SysTickUnlock();
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
     UINT32 val;
 
@@ -118,7 +131,7 @@ WEAK UINT64 HalGetTickCycle(UINT32 *period)
     return (UINT64)val;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     UINT32 value;
 
@@ -129,7 +142,7 @@ WEAK VOID HalTickLock(VOID)
     WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     UINT32 value;
 
@@ -140,7 +153,12 @@ WEAK VOID HalTickUnlock(VOID)
     WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     dsb();
     wfi();

arch/arm/cortex-m3/keil/los_arch_atomic.h

@@ -40,24 +40,112 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldrex   %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("1:ldrex   %0, [%2]\n"
+                         "  strex   %0, %3, [%2]\n"
+                         "  teq %0, #0\n"
+                         "  beq 1b"
+                         : "=&r"(status), "+m"(*v)
+                         : "r"(v), "r"(setVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "add   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "sub   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
  * @param  v       [IN] The variable pointer.
- * @param  val       [IN] The exchange value.
+ * @param  val     [IN] The exchange value.
  *
  * @retval #INT32       The previous value of the atomic variable
  * @par Dependency:
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
@@ -73,42 +161,6 @@ STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implementating the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -120,7 +172,7 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  *
  * @param  v       [IN] The variable pointer.
  * @param  val     [IN] The new value.
- * @param  oldVal      [IN] The old value.
+ * @param  oldVal  [IN] The old value.
  *
  * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
  * @retval FALSE The previous value of the atomic variable is equal to oldVal.
@@ -128,7 +180,7 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
@@ -148,6 +200,101 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
     return prevVal != oldVal;
 }
 
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
 #ifdef __cplusplus
 #if __cplusplus
 }
@@ -155,4 +302,3 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
 #endif /* __cplusplus */
 
 #endif /* _LOS_ARCH_ATOMIC_H */
-

arch/arm/cortex-m3/keil/los_arch_interrupt.h

@@ -309,7 +309,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -375,8 +375,7 @@ extern UINT32 HalIntNumGet(VOID);
  *
  * @retval:None.
  * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li
-></ul>
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
  * @see None.
  */
 extern VOID HalHwiDefaultHandler(VOID);
@@ -521,33 +520,13 @@ typedef struct TagExcContext {
 typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
 VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
 
-/**
- * @ingroup  los_arch_interrupt
- * @brief: Exception initialization.
- *
- * @par Description:
- * This API is used to configure the exception function vector table.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param uwArraySize [IN] Memory size of exception.
- *
- * @retval: None
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-VOID OsExcInit(VOID);
-
 VOID HalExcNMI(VOID);
 VOID HalExcHardFault(VOID);
 VOID HalExcMemFault(VOID);
 VOID HalExcBusFault(VOID);
 VOID HalExcUsageFault(VOID);
 VOID HalExcSvcCall(VOID);
-VOID HalHwiInit();
-
+VOID HalHwiInit(VOID);
 
 /**
  * @ingroup los_exc
@@ -681,19 +660,22 @@ VOID HalHwiInit();
  * @ingroup los_exc
  * Exception information structure
  *
- * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
+ * Description: Exception information saved when an exception is triggered on the Cortex-M3 platform.
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m3/keil/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m3/keil/los_context.c

@@ -37,35 +37,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -73,15 +66,15 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
-               topStack    --- Top of task's stack
+               topStack   --- Top of task's stack
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
     TaskContext *context = NULL;
     errno_t result;
@@ -147,14 +140,14 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m3/keil/los_dispatch.S

@@ -31,11 +31,11 @@
 
         PRESERVE8
 
-        EXPORT  HalIntLock
-        EXPORT  HalIntUnLock
-        EXPORT  HalIntRestore
+        EXPORT  ArchIntLock
+        EXPORT  ArchIntUnLock
+        EXPORT  ArchIntRestore
         EXPORT  HalStartToRun
-        EXPORT  HalTaskSchedule
+        EXPORT  ArchTaskSchedule
         EXPORT  HalPendSV
         IMPORT  OsSchedTaskSwitch
         IMPORT  g_losTask
@@ -77,21 +77,21 @@ HalStartToRun
     BX      R6
 
 
-HalIntLock
+ArchIntLock
     MRS     R0, PRIMASK
     CPSID   I
     BX      LR
 
-HalIntUnLock
+ArchIntUnLock
     MRS     R0, PRIMASK
     CPSIE   I
     BX      LR
 
-HalIntRestore
+ArchIntRestore
     MSR     PRIMASK, R0
     BX      LR
 
-HalTaskSchedule
+ArchTaskSchedule
     LDR     R0, =OS_NVIC_INT_CTRL
     LDR     R1, =OS_NVIC_PENDSVSET
     STR     R1, [R0]

arch/arm/cortex-m3/keil/los_exc.S

@@ -195,10 +195,10 @@ _hwiActiveCheck
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as pid
 
 _ExcInMSP
-    CMP   LR, #0XFFFFFFED
+    CMP   LR, #0xFFFFFFE9
     BNE   _NoFloatInMsp
     ADD   R3, R13, #104
     PUSH  {R3}

arch/arm/cortex-m3/keil/los_interrupt.c

@@ -28,12 +28,11 @@
  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-
 #include "los_interrupt.h"
-#include "securec.h"
 #include <stdarg.h>
-#include "los_arch_interrupt.h"
+#include "securec.h"
 #include "los_context.h"
+#include "los_arch_interrupt.h"
 #include "los_debug.h"
 #include "los_hook.h"
 #include "los_task.h"
@@ -47,17 +46,17 @@ UINT32 g_intCount = 0;
 /*lint -restore*/
 #ifdef __ICCARM__
 #pragma location = ".data.vector"
-#pragma data_alignment=0x100
 #elif defined(__CC_ARM) || defined(__GNUC__)
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
 LITE_OS_SEC_VEC
 #endif
 /* *
  * @ingroup los_hwi
- * hardware interrupt form mapping handling function array.
+ * Hardware interrupt form mapping handling function array.
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -66,7 +65,7 @@ typedef struct {
 
 /* *
  * @ingroup los_hwi
- * hardware interrupt handler form mapping handling function array.
+ * Hardware interrupt handler form mapping handling function array.
  */
 STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
 
@@ -120,7 +119,7 @@ LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -166,9 +165,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 #endif
 
     intSave = LOS_IntLock();
-
     g_intCount++;
-
     LOS_IntRestore(intSave);
 
     hwiIndex = HalIntNumGet();
@@ -177,7 +174,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -197,7 +194,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -207,11 +204,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -232,7 +229,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
@@ -246,13 +243,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -276,6 +273,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
 #define BUSFAULT                        (1 << 17)
 #define MEMFAULT                        (1 << 16)
 #define DIV0FAULT                       (1 << 4)
+#define UNALIGNFAULT                    (1 << 3)
 #define HARDFAULT_IRQN                  (-13)
 
 ExcInfo g_excInfo = {0};
@@ -485,7 +483,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************
@@ -495,7 +493,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
 {
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;
@@ -523,8 +521,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 
     /* Enable USGFAULT, BUSFAULT, MEMFAULT */
     *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+	
     /* Enable DIV 0 and unaligned exception */
-    *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
+#ifdef LOSCFG_ARCH_UNALIGNED_EXC
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
+#else
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
+#endif
 
     return;
 }

arch/arm/cortex-m3/keil/los_timer.c

@@ -34,38 +34,40 @@
 #include "ARMCM3.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -74,7 +76,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -83,27 +85,35 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
-    UINT32 hwCycle;
+    UINT32 hwCycle = 0;
     UINT32 intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
     *period = SysTick->LOAD;
-    hwCycle = *period - SysTick->VAL;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
     LOS_IntRestore(intSave);
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m33/gcc/BUILD.gn

@@ -0,0 +1,38 @@
+# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+#    conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+#    of conditions and the following disclaimer in the documentation and/or other materials
+#    provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+#    to endorse or promote products derived from this software without specific prior written
+#    permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_group("gcc") {
+  if (defined(LOSCFG_SECURE_TRUSTZONE)) {
+    modules = [ "TZ" ]
+  } else {
+    modules = [ "NTZ" ]
+  }
+}

arch/arm/cortex-m33/gcc/NTZ/BUILD.gn

@@ -27,9 +27,10 @@
 # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import("//kernel/liteos_m/config.gni")
+import("//kernel/liteos_m/liteos.gni")
 
-static_library("arch") {
+module_name = "arch"
+kernel_module(module_name) {
   sources = [
     "los_context.c",
     "los_dispatch.S",
@@ -37,6 +38,8 @@ static_library("arch") {
     "los_interrupt.c",
     "los_timer.c",
   ]
-
-  configs += [ "$LITEOSTOPDIR:los_config" ]
+}
+
+config("public") {
+  include_dirs = [ "." ]
 }

arch/arm/cortex-m33/gcc/NTZ/los_arch_atomic.h

@@ -40,24 +40,112 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldrex   %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("1:ldrex   %0, [%2]\n"
+                         "  strex   %0, %3, [%2]\n"
+                         "  teq %0, #0\n"
+                         "  beq 1b"
+                         : "=&r"(status), "+m"(*v)
+                         : "r"(v), "r"(setVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "add   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "sub   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
  * @param  v       [IN] The variable pointer.
- * @param  val       [IN] The exchange value.
+ * @param  val     [IN] The exchange value.
  *
  * @retval #INT32       The previous value of the atomic variable
  * @par Dependency:
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
@@ -73,42 +161,6 @@ STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implementating the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -120,7 +172,7 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  *
  * @param  v       [IN] The variable pointer.
  * @param  val     [IN] The new value.
- * @param  oldVal      [IN] The old value.
+ * @param  oldVal  [IN] The old value.
  *
  * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
  * @retval FALSE The previous value of the atomic variable is equal to oldVal.
@@ -128,7 +180,7 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
@@ -148,6 +200,101 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
     return prevVal != oldVal;
 }
 
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
 #ifdef __cplusplus
 #if __cplusplus
 }
@@ -155,4 +302,3 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
 #endif /* __cplusplus */
 
 #endif /* _LOS_ARCH_ATOMIC_H */
-

arch/arm/cortex-m33/gcc/NTZ/los_arch_interrupt.h

@@ -309,7 +309,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -375,8 +375,7 @@ extern UINT32 HalIntNumGet(VOID);
  *
  * @retval:None.
  * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li
-></ul>
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
  * @see None.
  */
 extern VOID HalHwiDefaultHandler(VOID);
@@ -521,33 +520,13 @@ typedef struct TagExcContext {
 typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
 VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
 
-/**
- * @ingroup  los_arch_interrupt
- * @brief: Exception initialization.
- *
- * @par Description:
- * This API is used to configure the exception function vector table.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param uwArraySize [IN] Memory size of exception.
- *
- * @retval: None
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-VOID OsExcInit(VOID);
-
 VOID HalExcNMI(VOID);
 VOID HalExcHardFault(VOID);
 VOID HalExcMemFault(VOID);
 VOID HalExcBusFault(VOID);
 VOID HalExcUsageFault(VOID);
 VOID HalSVCHandler(VOID);
-VOID HalHwiInit();
-
+VOID HalHwiInit(VOID);
 
 /**
  * @ingroup los_exc
@@ -681,19 +660,22 @@ VOID HalHwiInit();
  * @ingroup los_exc
  * Exception information structure
  *
- * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
+ * Description: Exception information saved when an exception is triggered on the Cortex-M33 platform.
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m33/gcc/NTZ/los_arch_timer.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */

arch/arm/cortex-m33/gcc/NTZ/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,15 +65,15 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
-               topStack    --- Top of task's stack
+               topStack   --- Top of task's stack
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
     TaskContext *context = NULL;
     errno_t result;
@@ -146,14 +139,14 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m33/gcc/NTZ/los_dispatch.S

@@ -94,9 +94,9 @@ __DisabledFPU:
     .fnend
 
 
-    .type HalIntLock, %function
-    .global HalIntLock
-HalIntLock:
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
     .fnstart
     .cantunwind
 
@@ -105,9 +105,9 @@ HalIntLock:
     BX LR
     .fnend
 
-    .type HalIntUnLock, %function
-    .global HalIntUnLock
-HalIntUnLock:
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
     .fnstart
     .cantunwind
 
@@ -116,9 +116,9 @@ HalIntUnLock:
     BX LR
     .fnend
 
-    .type HalIntRestore, %function
-    .global HalIntRestore
-HalIntRestore:
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
     .fnstart
     .cantunwind
 
@@ -126,9 +126,9 @@ HalIntRestore:
     BX LR
     .fnend
 
-    .type HalTaskSchedule, %function
-    .global HalTaskSchedule
-HalTaskSchedule:
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
     .fnstart
     .cantunwind
 

arch/arm/cortex-m33/gcc/NTZ/los_exc.S

@@ -268,7 +268,7 @@ _hwiActiveCheck:
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
     .fnend
 
     .type _ExcInMSP, %function
@@ -276,16 +276,13 @@ _hwiActiveCheck:
 _ExcInMSP:
     .fnstart
     .cantunwind
-    CMP   LR, #0XFFFFFFED
+    CMP   LR, #0xFFFFFFE9
     BNE   _NoFloatInMsp
     ADD   R3, R13, #104
     PUSH  {R3}
     MRS   R12, PRIMASK                  // store message-->exc: disable int?
     PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
     B     _handleEntry
   .fnend
 
@@ -324,7 +321,7 @@ _hwiActiveCheckNext:
 
     LDR  R2, =g_taskScheduled
     LDR  R2, [R2]
-    TST  R2, #1         // OS_FLG_BGD_ACTIVE
+    TST  R2, #1                         // OS_FLG_BGD_ACTIVE
     BEQ  _ExcInMSP                      // if exc occured in Init then branch
 
 
@@ -337,14 +334,11 @@ _hwiActiveCheckNext:
 
     MRS   R3,  PSP
     ADD   R12, R3, #104
-    PUSH  {R12}    // save task SP
+    PUSH  {R12}                         // save task SP
 
     MRS   R12, PRIMASK
     PUSH {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
 
     // copy auto saved task register
 
@@ -360,12 +354,12 @@ _hwiActiveCheckNext:
 _NoFloatInPsp:
     .fnstart
     .cantunwind
-    MOV   R2,  R13                           //no auto push floating registers
+    MOV   R2,  R13                      // no auto push floating registers
     SUB   R13, #32                      // add 8 Bytes reg(for STMFD)
 
     MRS   R3,  PSP
     ADD   R12, R3, #32
-    PUSH  {R12}    // save task SP
+    PUSH  {R12}                         // save task SP
 
     MRS   R12, PRIMASK
     PUSH {R4-R12}

arch/arm/cortex-m33/gcc/NTZ/los_interrupt.c

@@ -47,11 +47,11 @@ UINT32 g_intCount = 0;
 
 /* *
  * @ingroup los_hwi
- * hardware interrupt form mapping handling function array.
+ * Hardware interrupt form mapping handling function array.
  */
-STATIC HWI_PROC_FUNC __attribute__((aligned(0x100))) g_hwiForm[OS_VECTOR_CNT] = {0};
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -60,7 +60,7 @@ typedef struct {
 
 /* *
  * @ingroup los_hwi
- * hardware interrupt handler form mapping handling function array.
+ * Hardware interrupt handler form mapping handling function array.
  */
 STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
 
@@ -109,7 +109,7 @@ LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -164,7 +164,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -184,7 +184,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -194,11 +194,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -219,7 +219,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
@@ -233,13 +233,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
 #define BUSFAULT                        (1 << 17)
 #define MEMFAULT                        (1 << 16)
 #define DIV0FAULT                       (1 << 4)
+#define UNALIGNFAULT                    (1 << 3)
 #define HARDFAULT_IRQN                  (-13)
 
 ExcInfo g_excInfo = {0};
@@ -472,7 +473,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************
@@ -482,7 +483,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
 {
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;
@@ -510,8 +511,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 
     /* Enable USGFAULT, BUSFAULT, MEMFAULT */
     *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+	
     /* Enable DIV 0 and unaligned exception */
-    *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
+#ifdef LOSCFG_ARCH_UNALIGNED_EXC
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
+#else
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
+#endif
 
     return;
 }

arch/arm/cortex-m33/gcc/NTZ/los_timer.c

@@ -33,38 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,27 +84,35 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
-    UINT32 hwCycle;
+    UINT32 hwCycle = 0;
     UINT32 intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
     *period = SysTick->LOAD;
-    hwCycle = *period - SysTick->VAL;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
     LOS_IntRestore(intSave);
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m33/gcc/TZ/BUILD.gn

@@ -27,9 +27,10 @@
 # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import("//kernel/liteos_m/config.gni")
+import("//kernel/liteos_m/liteos.gni")
 
-static_library("arch") {
+module_name = "arch"
+kernel_module(module_name) {
   sources = [
     "non_secure/los_context.c",
     "non_secure/los_dispatch.S",
@@ -40,9 +41,11 @@ static_library("arch") {
   ]
 
   include_dirs = [
-    "./non_secure",
-    "./secure",
+    "non_secure",
+    "secure",
   ]
-
-  configs += [ "$LITEOSTOPDIR:los_config" ]
+}
+
+config("public") {
+  include_dirs = [ "non_secure" ]
 }

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_atomic.h

@@ -40,24 +40,112 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldrex   %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("1:ldrex   %0, [%2]\n"
+                         "  strex   %0, %3, [%2]\n"
+                         "  teq %0, #0\n"
+                         "  beq 1b"
+                         : "=&r"(status), "+m"(*v)
+                         : "r"(v), "r"(setVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "add   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "sub   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
  * @param  v       [IN] The variable pointer.
- * @param  val       [IN] The exchange value.
+ * @param  val     [IN] The exchange value.
  *
  * @retval #INT32       The previous value of the atomic variable
  * @par Dependency:
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
@@ -73,42 +161,6 @@ STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implementating the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -120,7 +172,7 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  *
  * @param  v       [IN] The variable pointer.
  * @param  val     [IN] The new value.
- * @param  oldVal      [IN] The old value.
+ * @param  oldVal  [IN] The old value.
  *
  * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
  * @retval FALSE The previous value of the atomic variable is equal to oldVal.
@@ -128,7 +180,7 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
@@ -148,6 +200,101 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
     return prevVal != oldVal;
 }
 
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
 #ifdef __cplusplus
 #if __cplusplus
 }
@@ -155,4 +302,3 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
 #endif /* __cplusplus */
 
 #endif /* _LOS_ARCH_ATOMIC_H */
-

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_context.h

@@ -43,7 +43,7 @@ extern "C" {
 
 typedef struct TagTskContext {
     UINT32 secureContext;
-    UINT32 stackLmit;
+    UINT32 stackLimit;
     UINT32 excReturn;
 #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined(__FPU_USED) && (__FPU_USED == 1U)))

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_interrupt.h

@@ -309,7 +309,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -375,8 +375,7 @@ extern UINT32 HalIntNumGet(VOID);
  *
  * @retval:None.
  * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li
-></ul>
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
  * @see None.
  */
 extern VOID HalHwiDefaultHandler(VOID);
@@ -521,33 +520,13 @@ typedef struct TagExcContext {
 typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
 VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
 
-/**
- * @ingroup  los_arch_interrupt
- * @brief: Exception initialization.
- *
- * @par Description:
- * This API is used to configure the exception function vector table.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param uwArraySize [IN] Memory size of exception.
- *
- * @retval: None
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-VOID OsExcInit(VOID);
-
 VOID HalExcNMI(VOID);
 VOID HalExcHardFault(VOID);
 VOID HalExcMemFault(VOID);
 VOID HalExcBusFault(VOID);
 VOID HalExcUsageFault(VOID);
 VOID HalSVCHandler(VOID);
-VOID HalHwiInit();
-
+VOID HalHwiInit(VOID);
 
 /**
  * @ingroup los_exc
@@ -681,19 +660,22 @@ VOID HalHwiInit();
  * @ingroup los_exc
  * Exception information structure
  *
- * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
+ * Description: Exception information saved when an exception is triggered on the Cortex-M33 platform.
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m33/gcc/TZ/non_secure/los_arch_timer.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */

arch/arm/cortex-m33/gcc/TZ/non_secure/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,15 +65,15 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
-               topStack    --- Top of task's stack
+               topStack   --- Top of task's stack
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
     TaskContext *context = NULL;
     errno_t result;
@@ -132,6 +125,10 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->NO_NAME = 0xAA000011;
 #endif
 
+    context->secureContext = 0UL;
+    context->stackLimit = (UINT32)topStack;
+    context->excReturn = 0xFFFFFFBC;
+
     context->uwR4 = 0x04040404L;
     context->uwR5 = 0x05050505L;
     context->uwR6 = 0x06060606L;
@@ -146,14 +143,14 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m33/gcc/TZ/non_secure/los_dispatch.S

@@ -76,9 +76,9 @@ __DisabledFPU1:
     CPSIE   I
     BX      R3
 
-    .type HalIntLock, %function
-    .global HalIntLock
-HalIntLock:
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
     .fnstart
     .cantunwind
 
@@ -87,9 +87,9 @@ HalIntLock:
     BX LR
     .fnend
 
-    .type HalIntUnLock, %function
-    .global HalIntUnLock
-HalIntUnLock:
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
     .fnstart
     .cantunwind
 
@@ -98,9 +98,9 @@ HalIntUnLock:
     BX LR
     .fnend
 
-    .type HalIntRestore, %function
-    .global HalIntRestore
-HalIntRestore:
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
     .fnstart
     .cantunwind
 
@@ -108,9 +108,9 @@ HalIntRestore:
     BX LR
     .fnend
 
-    .type HalTaskSchedule, %function
-    .global HalTaskSchedule
-HalTaskSchedule:
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
     .fnstart
     .cantunwind
 

arch/arm/cortex-m33/gcc/TZ/non_secure/los_exc.S

@@ -252,7 +252,7 @@ _hwiActiveCheck:
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
     .fnend
 
     .type _ExcInMSP, %function
@@ -260,16 +260,13 @@ _hwiActiveCheck:
 _ExcInMSP:
     .fnstart
     .cantunwind
-    CMP   LR, #0XFFFFFFED
+    CMP   LR, #0xFFFFFFE9
     BNE   _NoFloatInMsp
     ADD   R3, R13, #104
     PUSH  {R3}
     MRS   R12, PRIMASK                  // store message-->exc: disable int?
     PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
     B     _handleEntry
   .fnend
 
@@ -308,7 +305,7 @@ _hwiActiveCheckNext:
 
     LDR  R2, =g_taskScheduled
     LDR  R2, [R2]
-    TST  R2, #1         // OS_FLG_BGD_ACTIVE
+    TST  R2, #1                         // OS_FLG_BGD_ACTIVE
     BEQ  _ExcInMSP                      // if exc occured in Init then branch
 
 
@@ -321,14 +318,11 @@ _hwiActiveCheckNext:
 
     MRS   R3,  PSP
     ADD   R12, R3, #104
-    PUSH  {R12}    // save task SP
+    PUSH  {R12}                         // save task SP
 
     MRS   R12, PRIMASK
     PUSH {R4-R12}
-#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined(__FPU_USED) && (__FPU_USED == 1U)))
     VPUSH {D8-D15}
-#endif
 
     // copy auto saved task register
 
@@ -344,12 +338,12 @@ _hwiActiveCheckNext:
 _NoFloatInPsp:
     .fnstart
     .cantunwind
-    MOV   R2,  R13                           //no auto push floating registers
+    MOV   R2,  R13                      // no auto push floating registers
     SUB   R13, #32                      // add 8 Bytes reg(for STMFD)
 
     MRS   R3,  PSP
     ADD   R12, R3, #32
-    PUSH  {R12}    // save task SP
+    PUSH  {R12}                         // save task SP
 
     MRS   R12, PRIMASK
     PUSH {R4-R12}

arch/arm/cortex-m33/gcc/TZ/non_secure/los_interrupt.c

@@ -47,11 +47,11 @@ UINT32 g_intCount = 0;
 
 /* *
  * @ingroup los_hwi
- * hardware interrupt form mapping handling function array.
+ * Hardware interrupt form mapping handling function array.
  */
-STATIC HWI_PROC_FUNC __attribute__((aligned(0x100))) g_hwiForm[OS_VECTOR_CNT] = {0};
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -60,7 +60,7 @@ typedef struct {
 
 /* *
  * @ingroup los_hwi
- * hardware interrupt handler form mapping handling function array.
+ * Hardware interrupt handler form mapping handling function array.
  */
 STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
 
@@ -109,7 +109,7 @@ LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -164,7 +164,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -184,7 +184,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -194,11 +194,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -219,7 +219,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
@@ -233,13 +233,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -263,6 +263,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
 #define BUSFAULT                        (1 << 17)
 #define MEMFAULT                        (1 << 16)
 #define DIV0FAULT                       (1 << 4)
+#define UNALIGNFAULT                    (1 << 3)
 #define HARDFAULT_IRQN                  (-13)
 
 ExcInfo g_excInfo = {0};
@@ -472,7 +473,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************
@@ -482,7 +483,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
 {
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;
@@ -510,8 +511,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 
     /* Enable USGFAULT, BUSFAULT, MEMFAULT */
     *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+	
     /* Enable DIV 0 and unaligned exception */
-    *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
+#ifdef LOSCFG_ARCH_UNALIGNED_EXC
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
+#else
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
+#endif
 
     return;
 }

arch/arm/cortex-m33/gcc/TZ/non_secure/los_timer.c

@@ -33,38 +33,39 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
-#include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(g_cyclesPerTick);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +74,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,27 +83,35 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
-    UINT32 hwCycle;
+    UINT32 hwCycle = 0；
     UINT32 intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
     *period = SysTick->LOAD;
-    hwCycle = *period - SysTick->VAL;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
     LOS_IntRestore(intSave);
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m33/iar/NTZ/los_arch_atomic.h

@@ -40,24 +40,112 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldrex   %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("1:ldrex   %0, [%2]\n"
+                         "  strex   %0, %3, [%2]\n"
+                         "  teq %0, #0\n"
+                         "  beq 1b"
+                         : "=&r"(status), "+m"(*v)
+                         : "r"(v), "r"(setVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "add   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "sub   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable.
  *
  * @par Description:
- * This API is used to implement the atomic exchange for 32-bit variable and return the previous value of the atomic variable.
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
  * @attention
  * <ul>The pointer v must not be NULL.</ul>
  *
  * @param  v       [IN] The variable pointer.
- * @param  val       [IN] The exchange value.
+ * @param  val     [IN] The exchange value.
  *
  * @retval #INT32       The previous value of the atomic variable
  * @par Dependency:
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
@@ -73,42 +161,6 @@ STATIC INLINE INT32 HalAtomicXchg32bits(volatile INT32 *v, INT32 val)
     return prevVal;
 }
 
-/**
- * @ingroup  los_arch_atomic
- * @brief Atomic auto-decrement.
- *
- * @par Description:
- * This API is used to implementating the atomic auto-decrement and return the result of auto-decrement.
- * @attention
- * <ul>
- * <li>The pointer v must not be NULL.</li>
- * <li>The value which v point to must not be INT_MIN to avoid overflow after reducing 1.</li>
- * </ul>
- *
- * @param  v      [IN] The addSelf variable pointer.
- *
- * @retval #INT32  The return value of variable auto-decrement.
- * @par Dependency:
- * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
-{
-    INT32 val = 0;
-    UINT32 status = 0;
-
-    do {
-        __asm__ __volatile__("ldrex   %0, [%3]\n"
-                             "sub   %0, %0, #1\n"
-                             "strex   %1, %0, [%3]"
-                             : "=&r"(val), "=&r"(status), "+m"(*v)
-                             : "r"(v)
-                             : "cc");
-    } while (__builtin_expect(status != 0, 0));
-
-    return val;
-}
-
 /**
  * @ingroup  los_arch_atomic
  * @brief Atomic exchange for 32-bit variable with compare.
@@ -120,7 +172,7 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  *
  * @param  v       [IN] The variable pointer.
  * @param  val     [IN] The new value.
- * @param  oldVal      [IN] The old value.
+ * @param  oldVal  [IN] The old value.
  *
  * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
  * @retval FALSE The previous value of the atomic variable is equal to oldVal.
@@ -128,7 +180,7 @@ STATIC INLINE INT32 HalAtomicDecRet(volatile INT32 *v)
  * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
  * @see
  */
-STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
 {
     INT32 prevVal = 0;
     UINT32 status = 0;
@@ -148,6 +200,101 @@ STATIC INLINE BOOL HalAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 ol
     return prevVal != oldVal;
 }
 
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
 #ifdef __cplusplus
 #if __cplusplus
 }

arch/arm/cortex-m33/iar/NTZ/los_arch_interrupt.h

@@ -309,7 +309,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_hwi
  * Set interrupt vector table.
@@ -521,33 +521,13 @@ typedef struct TagExcContext {
 typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
 VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
 
-/**
- * @ingroup  los_hwi
- * @brief: Exception initialization.
- *
- * @par Description:
- * This API is used to configure the exception function vector table.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param uwArraySize [IN] Memory size of exception.
- *
- * @retval: None
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-VOID OsExcInit(VOID);
-
 VOID HalExcNMI(VOID);
 VOID HalExcHardFault(VOID);
 VOID HalExcMemFault(VOID);
 VOID HalExcBusFault(VOID);
 VOID HalExcUsageFault(VOID);
 VOID HalSVCHandler(VOID);
-VOID HalHwiInit();
-
+VOID HalHwiInit(VOID);
 
 /**
  * @ingroup los_exc
@@ -685,15 +665,18 @@ VOID HalHwiInit();
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m33/iar/NTZ/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }
@@ -51,3 +49,4 @@ UINT32 HalTickStart(OS_TICK_HANDLER handler);
 #endif /* __cplusplus */
 
 #endif /* _LOS_ARCH_TIMER_H */
+

arch/arm/cortex-m33/iar/NTZ/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,7 +73,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
     TaskContext *context = NULL;
     errno_t result;
@@ -146,14 +139,14 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m33/iar/NTZ/los_dispatch.S

@@ -31,11 +31,11 @@
 
     PRESERVE8
 
-    EXPORT  HalIntLock
-    EXPORT  HalIntUnLock
-    EXPORT  HalIntRestore
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
     EXPORT  HalStartToRun
-    EXPORT  HalTaskSchedule
+    EXPORT  ArchTaskSchedule
     EXPORT  HalPendSV
     IMPORT  OsSchedTaskSwitch
     IMPORT  g_losTask
@@ -90,21 +90,21 @@ __DisabledFPU
     BX      R6
 
 
-HalIntLock
+ArchIntLock
     MRS     R0, PRIMASK
     CPSID   I
     BX      LR
 
-HalIntUnLock
+ArchIntUnLock
     MRS     R0, PRIMASK
     CPSIE   I
     BX      LR
 
-HalIntRestore
+ArchIntRestore
     MSR     PRIMASK, R0
     BX      LR
 
-HalTaskSchedule
+ArchTaskSchedule
     LDR     R0, =OS_NVIC_INT_CTRL
     LDR     R1, =OS_NVIC_PENDSVSET
     STR     R1, [R0]

arch/arm/cortex-m33/iar/NTZ/los_exc.S

@@ -198,7 +198,7 @@ _hwiActiveCheck
     ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as uwPid
 
 _ExcInMSP
-    CMP   LR, #0XFFFFFFED
+    CMP   LR, #0xFFFFFFE9
     BNE   _NoFloatInMsp
     ADD   R3, R13, #104
     PUSH  {R3}

arch/arm/cortex-m33/iar/NTZ/los_interrupt.c

@@ -46,14 +46,14 @@ UINT32 g_intCount = 0;
 
 /*lint -restore*/
 #pragma location = ".data.vector"
-#pragma data_alignment=0x100
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
 /* *
  * @ingroup los_hwi
  * hardware interrupt form mapping handling function array.
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -116,7 +116,7 @@ LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -173,7 +173,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -193,7 +193,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -203,11 +203,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINTPTR intSave;
 
@@ -228,7 +228,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
@@ -242,13 +242,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -481,7 +481,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************
@@ -491,7 +491,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
 {
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;

arch/arm/cortex-m33/iar/NTZ/los_timer.c

@@ -33,38 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,27 +84,35 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
-    UINT32 hwCycle;
+    UINT32 hwCycle = 0;
     UINTPTR intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
     *period = SysTick->LOAD;
-    hwCycle = *period - SysTick->VAL;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
     LOS_IntRestore(intSave);
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_atomic.h

@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldrex   %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("1:ldrex   %0, [%2]\n"
+                         "  strex   %0, %3, [%2]\n"
+                         "  teq %0, #0\n"
+                         "  beq 1b"
+                         : "=&r"(status), "+m"(*v)
+                         : "r"(v), "r"(setVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "add   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "sub   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("ldrex   %0, [%3]\n"
+                             "strex   %1, %4, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("1: ldrex %0, %2\n"
+                             "    mov %1, #0\n"
+                             "    cmp %0, %3\n"
+                             "    bne 2f\n"
+                             "    strex %1, %4, %2\n"
+                             "2:"
+                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
+                             : "r"(oldVal), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_interrupt.h

@@ -309,7 +309,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_hwi
  * Set interrupt vector table.
@@ -521,33 +521,13 @@ typedef struct TagExcContext {
 typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
 VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
 
-/**
- * @ingroup  los_hwi
- * @brief: Exception initialization.
- *
- * @par Description:
- * This API is used to configure the exception function vector table.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param uwArraySize [IN] Memory size of exception.
- *
- * @retval: None
- * @par Dependency:
- * <ul><li>los_hwi.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-VOID OsExcInit(VOID);
-
 VOID HalExcNMI(VOID);
 VOID HalExcHardFault(VOID);
 VOID HalExcMemFault(VOID);
 VOID HalExcBusFault(VOID);
 VOID HalExcUsageFault(VOID);
 VOID HalSVCHandler(VOID);
-VOID HalHwiInit();
-
+VOID HalHwiInit(VOID);
 
 /**
  * @ingroup los_exc
@@ -685,15 +665,18 @@ VOID HalHwiInit();
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m33/iar/TZ/non_secure/los_arch_timer.h

@@ -34,7 +34,7 @@
 
 #include "los_config.h"
 #include "los_compiler.h"
-#include "los_context.h"
+#include "los_timer.h"
 
 #ifdef __cplusplus
 #if __cplusplus
@@ -42,8 +42,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-UINT32 HalTickStart(OS_TICK_HANDLER handler);
-
 #ifdef __cplusplus
 #if __cplusplus
 }
@@ -51,3 +49,4 @@ UINT32 HalTickStart(OS_TICK_HANDLER handler);
 #endif /* __cplusplus */
 
 #endif /* _LOS_ARCH_TIMER_H */
+

arch/arm/cortex-m33/iar/TZ/non_secure/los_context.c

@@ -36,35 +36,28 @@
 #include "los_task.h"
 #include "los_sched.h"
 #include "los_interrupt.h"
-#include "los_arch_timer.h"
 #include "los_debug.h"
 
 /* ****************************************************************************
- Function    : HalArchInit
+ Function    : ArchInit
  Description : arch init function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalArchInit(VOID)
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
 {
-    UINT32 ret;
     HalHwiInit();
-
-    ret = HalTickStart(OsTickHandler);
-    if (ret != LOS_OK) {
-        PRINT_ERR("Tick start failed!\n");
-    }
 }
 
 /* ****************************************************************************
- Function    : HalSysExit
+ Function    : ArchSysExit
  Description : Task exit function
  Input       : None
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
 {
     LOS_IntLock();
     while (1) {
@@ -72,7 +65,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalTskStackInit
+ Function    : ArchTskStackInit
  Description : Task stack initialization function
  Input       : taskID     --- TaskID
                stackSize  --- Total size of the stack
@@ -80,7 +73,7 @@ LITE_OS_SEC_TEXT_MINOR VOID HalSysExit(VOID)
  Output      : None
  Return      : Context pointer
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
 {
     TaskContext *context = NULL;
     errno_t result;
@@ -150,14 +143,14 @@ LITE_OS_SEC_TEXT_INIT VOID *HalTskStackInit(UINT32 taskID, UINT32 stackSize, VOI
     context->uwR2 = 0x02020202L;
     context->uwR3 = 0x03030303L;
     context->uwR12 = 0x12121212L;
-    context->uwLR = (UINT32)(UINTPTR)HalSysExit;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
     context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
     context->uwxPSR = 0x01000000L;
 
     return (VOID *)context;
 }
 
-LITE_OS_SEC_TEXT_INIT UINT32 HalStartSchedule(VOID)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
 {
     (VOID)LOS_IntLock();
     OsSchedStart();

arch/arm/cortex-m33/iar/TZ/non_secure/los_dispatch.S

@@ -31,10 +31,10 @@
 
     PRESERVE8
 
-    EXPORT  HalIntLock
-    EXPORT  HalIntUnLock
-    EXPORT  HalIntRestore
-    EXPORT  HalTaskSchedule
+    EXPORT  ArchIntLock
+    EXPORT  ArchIntUnLock
+    EXPORT  ArchIntRestore
+    EXPORT  ArchTaskSchedule
     EXPORT  HalPendSV
     EXPORT  HalSVCHandler
     EXPORT  HalStartFirstTask
@@ -91,21 +91,21 @@ __DisabledFPU1
     CPSIE   I
     BX      R3
 
-HalIntLock
+ArchIntLock
     MRS     R0, PRIMASK
     CPSID   I
     BX      LR
 
-HalIntUnLock
+ArchIntUnLock
     MRS     R0, PRIMASK
     CPSIE   I
     BX      LR
 
-HalIntRestore
+ArchIntRestore
     MSR     PRIMASK, R0
     BX      LR
 
-HalTaskSchedule
+ArchTaskSchedule
     LDR     R0, =OS_NVIC_INT_CTRL
     LDR     R1, =OS_NVIC_PENDSVSET
     STR     R1, [R0]

arch/arm/cortex-m33/iar/TZ/non_secure/los_exc.S

@@ -184,10 +184,10 @@ _hwiActiveCheck
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               ; calculate R2 (hwi number) as pid
 
 _ExcInMSP
-    CMP   LR, #0XFFFFFFED
+    CMP   LR, #0xFFFFFFE9
     BNE   _NoFloatInMsp
     ADD   R3, R13, #104
     PUSH  {R3}

arch/arm/cortex-m33/iar/TZ/non_secure/los_interrupt.c

@@ -46,14 +46,14 @@ UINT32 g_intCount = 0;
 
 /*lint -restore*/
 #pragma location = ".data.vector"
-#pragma data_alignment=0x100
+#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
 /* *
  * @ingroup los_hwi
  * hardware interrupt form mapping handling function array.
  */
 STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -116,7 +116,7 @@ LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -173,7 +173,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -193,7 +193,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -203,11 +203,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINTPTR intSave;
 
@@ -228,7 +228,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
@@ -242,13 +242,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -481,7 +481,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* ****************************************************************************
@@ -491,7 +491,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
 {
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;

arch/arm/cortex-m33/iar/TZ/non_secure/los_timer.c

@@ -33,38 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,27 +84,35 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
-    UINT32 hwCycle;
+    UINT32 hwCycle = 0;
     UINTPTR intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
     *period = SysTick->LOAD;
-    hwCycle = *period - SysTick->VAL;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
     LOS_IntRestore(intSave);
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();

arch/arm/cortex-m4/gcc/BUILD.gn

@@ -27,9 +27,10 @@
 # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import("//kernel/liteos_m/config.gni")
+import("//kernel/liteos_m/liteos.gni")
 
-static_library("arch") {
+module_name = "arch"
+kernel_module(module_name) {
   sources = [
     "los_context.c",
     "los_dispatch.S",
@@ -38,6 +39,8 @@ static_library("arch") {
     "los_mpu.c",
     "los_timer.c",
   ]
-
-  configs += [ "$LITEOSTOPDIR:los_config" ]
+}
+
+config("public") {
+  include_dirs = [ "." ]
 }

arch/arm/cortex-m4/gcc/los_arch_atomic.h

@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldrex   %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("1:ldrex   %0, [%2]\n"
+                         "  strex   %0, %3, [%2]\n"
+                         "  teq %0, #0\n"
+                         "  beq 1b"
+                         : "=&r"(status), "+m"(*v)
+                         : "r"(v), "r"(setVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "add   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "sub   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("ldrex   %0, [%3]\n"
+                             "strex   %1, %4, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("1: ldrex %0, %2\n"
+                             "    mov %1, #0\n"
+                             "    cmp %0, %3\n"
+                             "    bne 2f\n"
+                             "    strex %1, %4, %2\n"
+                             "2:"
+                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
+                             : "r"(oldVal), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */

arch/arm/cortex-m4/gcc/los_arch_interrupt.h

@@ -309,7 +309,7 @@ extern UINT32 _BootVectors[];
  */
 #define OS_EXC_SYS_TICK                       15
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 /* *
  * @ingroup los_arch_interrupt
  * Set interrupt vector table.
@@ -375,8 +375,7 @@ extern UINT32 HalIntNumGet(VOID);
  *
  * @retval:None.
  * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li
-></ul>
+ * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
  * @see None.
  */
 extern VOID HalHwiDefaultHandler(VOID);
@@ -521,33 +520,13 @@ typedef struct TagExcContext {
 typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
 VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
 
-/**
- * @ingroup  los_arch_interrupt
- * @brief: Exception initialization.
- *
- * @par Description:
- * This API is used to configure the exception function vector table.
- *
- * @attention:
- * <ul><li>None.</li></ul>
- *
- * @param uwArraySize [IN] Memory size of exception.
- *
- * @retval: None
- * @par Dependency:
- * <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
- * @see None.
- */
-VOID OsExcInit(VOID);
-
 VOID HalExcNMI(VOID);
 VOID HalExcHardFault(VOID);
 VOID HalExcMemFault(VOID);
 VOID HalExcBusFault(VOID);
 VOID HalExcUsageFault(VOID);
 VOID HalExcSvcCall(VOID);
-VOID HalHwiInit();
-
+VOID HalHwiInit(VOID);
 
 /**
  * @ingroup los_exc
@@ -685,15 +664,18 @@ VOID HalHwiInit();
  *
  */
 typedef struct TagExcInfo {
-    /**< Exception occurrence phase: 0 means that an exception occurs in initialization, 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+    /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+     * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
     UINT16 phase;
     /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
     UINT16 type;
     /**< If the exact address access error indicates the wrong access address when the exception occurred */
     UINT32 faultAddr;
-    /**< An exception occurs in an interrupt, indicating the interrupt number. An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+    /**< An exception occurs in an interrupt, indicating the interrupt number.
+     * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
     UINT32 thrdPid;
-    /**< Number of nested exceptions. Currently only registered hook functions are supported when an exception is entered for the first time */
+    /**< Number of nested exceptions. Currently only registered hook functions are supported
+     * when an exception is entered for the first time */
     UINT16 nestCnt;
     /**< reserve */
     UINT16 reserved;

arch/arm/cortex-m4/gcc/los_arch_timer.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */

arch/arm/cortex-m4/gcc/los_context.c

@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+
+/* ****************************************************************************
+ Function    : ArchInit
+ Description : arch init function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+    HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function    : ArchSysExit
+ Description : Task exit function
+ Input       : None
+ Output      : None
+ Return      : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+    LOS_IntLock();
+    while (1) {
+    }
+}
+
+/* ****************************************************************************
+ Function    : ArchTskStackInit
+ Description : Task stack initialization function
+ Input       : taskID     --- TaskID
+               stackSize  --- Total size of the stack
+               topStack   --- Top of task's stack
+ Output      : None
+ Return      : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+    TaskContext *context = NULL;
+    errno_t result;
+
+    /* initialize the task stack, write magic num to stack top */
+    result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
+    if (result != EOK) {
+        printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
+    }
+    *((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
+
+    context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
+
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined(__FPU_USED) && (__FPU_USED == 1U)))
+    context->S16 = 0xAA000010;
+    context->S17 = 0xAA000011;
+    context->S18 = 0xAA000012;
+    context->S19 = 0xAA000013;
+    context->S20 = 0xAA000014;
+    context->S21 = 0xAA000015;
+    context->S22 = 0xAA000016;
+    context->S23 = 0xAA000017;
+    context->S24 = 0xAA000018;
+    context->S25 = 0xAA000019;
+    context->S26 = 0xAA00001A;
+    context->S27 = 0xAA00001B;
+    context->S28 = 0xAA00001C;
+    context->S29 = 0xAA00001D;
+    context->S30 = 0xAA00001E;
+    context->S31 = 0xAA00001F;
+    context->S0 = 0xAA000000;
+    context->S1 = 0xAA000001;
+    context->S2 = 0xAA000002;
+    context->S3 = 0xAA000003;
+    context->S4 = 0xAA000004;
+    context->S5 = 0xAA000005;
+    context->S6 = 0xAA000006;
+    context->S7 = 0xAA000007;
+    context->S8 = 0xAA000008;
+    context->S9 = 0xAA000009;
+    context->S10 = 0xAA00000A;
+    context->S11 = 0xAA00000B;
+    context->S12 = 0xAA00000C;
+    context->S13 = 0xAA00000D;
+    context->S14 = 0xAA00000E;
+    context->S15 = 0xAA00000F;
+    context->FPSCR = 0x00000000;
+    context->NO_NAME = 0xAA000011;
+#endif
+
+    context->uwR4 = 0x04040404L;
+    context->uwR5 = 0x05050505L;
+    context->uwR6 = 0x06060606L;
+    context->uwR7 = 0x07070707L;
+    context->uwR8 = 0x08080808L;
+    context->uwR9 = 0x09090909L;
+    context->uwR10 = 0x10101010L;
+    context->uwR11 = 0x11111111L;
+    context->uwPriMask = 0;
+    context->uwR0 = taskID;
+    context->uwR1 = 0x01010101L;
+    context->uwR2 = 0x02020202L;
+    context->uwR3 = 0x03030303L;
+    context->uwR12 = 0x12121212L;
+    context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
+    context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
+    context->uwxPSR = 0x01000000L;
+
+    return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+    (VOID)LOS_IntLock();
+    OsSchedStart();
+    HalStartToRun();
+    return LOS_OK; /* never return */
+}
+

arch/arm/cortex-m4/gcc/los_dispatch.S

@@ -30,7 +30,7 @@
  */
 .syntax unified
 .arch armv7e-m
-.fpu fpv5-d16
+.fpu fpv4-sp-d16
 .thumb
 
 .equ    OS_FPU_CPACR,                0xE000ED88
@@ -89,9 +89,9 @@ __DisabledFPU:
     .fnend
 
 
-    .type HalIntLock, %function
-    .global HalIntLock
-HalIntLock:
+    .type ArchIntLock, %function
+    .global ArchIntLock
+ArchIntLock:
     .fnstart
     .cantunwind
 
@@ -100,9 +100,9 @@ HalIntLock:
     BX LR
     .fnend
 
-    .type HalIntUnLock, %function
-    .global HalIntUnLock
-HalIntUnLock:
+    .type ArchIntUnLock, %function
+    .global ArchIntUnLock
+ArchIntUnLock:
     .fnstart
     .cantunwind
 
@@ -111,9 +111,9 @@ HalIntUnLock:
     BX LR
     .fnend
 
-    .type HalIntRestore, %function
-    .global HalIntRestore
-HalIntRestore:
+    .type ArchIntRestore, %function
+    .global ArchIntRestore
+ArchIntRestore:
     .fnstart
     .cantunwind
 
@@ -121,9 +121,9 @@ HalIntRestore:
     BX LR
     .fnend
 
-    .type HalTaskSchedule, %function
-    .global HalTaskSchedule
-HalTaskSchedule:
+    .type ArchTaskSchedule, %function
+    .global ArchTaskSchedule
+ArchTaskSchedule:
     .fnstart
     .cantunwind
 

arch/arm/cortex-m4/gcc/los_exc.S

@@ -29,9 +29,10 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
- .syntax unified
- .arch armv7e-m
- .thumb
+.syntax unified
+.arch armv7e-m
+.fpu fpv4-sp-d16
+.thumb
 .section .text
 
 
@@ -267,7 +268,7 @@ _hwiActiveCheck:
     RBIT  R2, R3
     CLZ   R2, R2
     AND   R12, R12, #1
-    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as uwPid
+    ADD   R2, R2, R12, LSL #5               // calculate R2 (hwi number) as pid
     .fnend
 
     .type _ExcInMSP, %function
@@ -275,13 +276,13 @@ _hwiActiveCheck:
 _ExcInMSP:
     .fnstart
     .cantunwind
-    CMP   LR, #0XFFFFFFED
+    CMP   LR, #0xFFFFFFE9
     BNE   _NoFloatInMsp
     ADD   R3, R13, #104
     PUSH  {R3}
     MRS   R12, PRIMASK                  // store message-->exc: disable int?
     PUSH {R4-R12}                       // store message-->exc: {R4-R12}
-    #VPUSH {D8-D15}                     // FPU
+    VPUSH {D8-D15}                      // FPU
     B     _handleEntry
   .fnend
 
@@ -337,12 +338,13 @@ _hwiActiveCheckNext:
 
     MRS   R12, PRIMASK
     PUSH {R4-R12}
+    VPUSH {D8-D15}                      // FPU
 
     // copy auto saved task register
 
-    LDMFD R3!, {R4-R11}                  // R4-R11 store PSP reg(auto push when exc in task)
-    #VLDMIA  R3!, {D8-D15}               // FPU
-    #VSTMDB  R2!, {D8-D15}               // FPU
+    LDMFD R3!, {R4-R11}                 // R4-R11 store PSP reg(auto push when exc in task)
+    VLDMIA  R3!, {D8-D15}               // FPU
+    VSTMDB  R2!, {D8-D15}               // FPU
     STMFD R2!, {R4-R11}
     B     _handleEntry
   .fnend
@@ -352,7 +354,7 @@ _hwiActiveCheckNext:
 _NoFloatInPsp:
     .fnstart
     .cantunwind
-    MOV   R2,  R13                      //no auto push floating registers
+    MOV   R2,  R13                      // no auto push floating registers
     SUB   R13, #32                      // add 8 Bytes reg(for STMFD)
 
     MRS   R3,  PSP

arch/arm/cortex-m4/gcc/los_interrupt.c

@@ -44,19 +44,14 @@
 UINT32 g_intCount = 0;
 
 /*lint -restore*/
-#ifdef __ICCARM__
-#pragma location = ".data.vector"
-#pragma data_alignment=0x100
-#elif defined(__CC_ARM) || defined(__GNUC__)
-LITE_OS_SEC_VEC
-#endif
+
 /* *
  * @ingroup los_hwi
- * hardware interrupt form mapping handling function array.
+ * Hardware interrupt form mapping handling function array.
  */
-STATIC HWI_PROC_FUNC __attribute__((aligned(0x100))) g_hwiForm[OS_VECTOR_CNT] = {0};
+STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
 
 typedef struct {
     HWI_PROC_FUNC pfnHandler;
@@ -65,7 +60,7 @@ typedef struct {
 
 /* *
  * @ingroup los_hwi
- * hardware interrupt handler form mapping handling function array.
+ * Hardware interrupt handler form mapping handling function array.
  */
 STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
 
@@ -119,7 +114,7 @@ LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
     return __get_IPSR();
 }
 
-inline UINT32 HalIsIntActive(VOID)
+inline UINT32 ArchIsIntActive(VOID)
 {
     return (g_intCount > 0);
 }
@@ -174,7 +169,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 
     HalPreInterruptHandler(hwiIndex);
 
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
         g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
     }
@@ -194,7 +189,7 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
 }
 
 /* ****************************************************************************
- Function    : HalHwiCreate
+ Function    : ArchHwiCreate
  Description : create hardware interrupt
  Input       : hwiNum   --- hwi num to create
                hwiPrio  --- priority of the hwi
@@ -204,11 +199,11 @@ LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
-                                          HWI_PRIOR_T hwiPrio,
-                                          HWI_MODE_T mode,
-                                          HWI_PROC_FUNC handler,
-                                          HWI_ARG_T arg)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+                                           HWI_PRIOR_T hwiPrio,
+                                           HWI_MODE_T mode,
+                                           HWI_PROC_FUNC handler,
+                                           HWI_ARG_T arg)
 {
     UINT32 intSave;
 
@@ -229,7 +224,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
     }
 
     intSave = LOS_IntLock();
-#if (OS_HWI_WITH_ARG == 1)
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
     OsSetVector(hwiNum, handler, arg);
 #else
     OsSetVector(hwiNum, handler);
@@ -243,13 +238,13 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiCreate(HWI_HANDLE_T hwiNum,
 }
 
 /* ****************************************************************************
- Function    : HalHwiDelete
+ Function    : ArchHwiDelete
  Description : Delete hardware interrupt
  Input       : hwiNum   --- hwi num to delete
  Output      : None
  Return      : LOS_OK on success or error code on failure
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
 {
     UINT32 intSave;
 
@@ -273,6 +268,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 HalHwiDelete(HWI_HANDLE_T hwiNum)
 #define BUSFAULT                        (1 << 17)
 #define MEMFAULT                        (1 << 16)
 #define DIV0FAULT                       (1 << 4)
+#define UNALIGNFAULT                    (1 << 3)
 #define HARDFAULT_IRQN                  (-13)
 
 ExcInfo g_excInfo = {0};
@@ -482,7 +478,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U
 
     OsDoExcHook(EXC_INTERRUPT);
     OsExcInfoDisplay(&g_excInfo);
-    HalSysExit();
+    ArchSysExit();
 }
 
 /* stack protector */
@@ -502,7 +498,7 @@ WEAK VOID __stack_chk_fail(VOID)
  Output      : None
  Return      : None
  **************************************************************************** */
-LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
 {
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
     UINT32 index;
@@ -530,8 +526,13 @@ LITE_OS_SEC_TEXT_INIT VOID HalHwiInit()
 
     /* Enable USGFAULT, BUSFAULT, MEMFAULT */
     *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
+	
     /* Enable DIV 0 and unaligned exception */
-    *(volatile UINT32 *)OS_NVIC_CCR |= DIV0FAULT;
+#ifdef LOSCFG_ARCH_UNALIGNED_EXC
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
+#else
+    *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
+#endif
 
     return;
 }

arch/arm/cortex-m4/gcc/los_mpu.c

@@ -49,22 +49,22 @@ typedef enum {
     MPU_AP_RO_USER_RO = 0x6,         /* Privileged:Read-only      Unprivileged:Read-only */
 } MpuApConfig;
 
-VOID HalMpuEnable(UINT32 defaultRegionEnable)
+VOID ArchMpuEnable(UINT32 defaultRegionEnable)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = (MPU_CTRL_ENABLE_Msk | ((defaultRegionEnable << MPU_CTRL_PRIVDEFENA_Pos) & MPU_CTRL_PRIVDEFENA_Msk));
     SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
-VOID HalMpuDisable(VOID)
+VOID ArchMpuDisable(VOID)
 {
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     MPU->CTRL = 0;
     __DSB();
     __ISB();
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 }
 
 STATIC VOID HalMpuRASRAddMemAttr(MPU_CFG_PARA *para, UINT32 *RASR)
@@ -97,7 +97,7 @@ STATIC UINT32 HalMpuEncodeSize(UINT64 size)
     if (size > SIZE_4G_BYTE) {
         return 0;
     }
-    if ((size & 0x1F) != 0) { /* size sould aligned to 32 byte at least. */
+    if ((size & 0x1F) != 0) { /* size should aligned to 32 byte at least. */
         return 0;
     }
     size = (size >> 2);
@@ -147,7 +147,7 @@ STATIC UINT32 HalMpuGetRASR(UINT32 encodeSize, MPU_CFG_PARA *para)
     return RASR;
 }
 
-UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
+UINT32 ArchMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
 {
     UINT32 RASR;
     UINT32 RBAR;
@@ -175,9 +175,9 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     }
     RBAR = para->baseAddr & MPU_RBAR_ADDR_Msk;
     RASR = HalMpuGetRASR(encodeSize, para);
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
     MPU->RNR = RNR;
@@ -186,11 +186,11 @@ UINT32 HalMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
     __DSB();
     __ISB();
     g_regionNumBeUsed[regionId] = 1; /* Set mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-UINT32 HalMpuDisableRegion(UINT32 regionId)
+UINT32 ArchMpuDisableRegion(UINT32 regionId)
 {
     volatile UINT32 type;
     UINT32 intSave;
@@ -199,9 +199,9 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         return LOS_NOK;
     }
 
-    intSave = HalIntLock();
+    intSave = ArchIntLock();
     if (!g_regionNumBeUsed[regionId]) {
-        HalIntRestore(intSave);
+        ArchIntRestore(intSave);
         return LOS_NOK;
     }
 
@@ -213,20 +213,20 @@ UINT32 HalMpuDisableRegion(UINT32 regionId)
         __ISB();
     }
     g_regionNumBeUsed[regionId] = 0; /* clear mpu region used flag */
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
     return LOS_OK;
 }
 
-INT32 HalMpuUnusedRegionGet(VOID)
+INT32 ArchMpuUnusedRegionGet(VOID)
 {
     INT32 id;
-    UINT32 intSave = HalIntLock();
+    UINT32 intSave = ArchIntLock();
     for (id = 0; id < MPU_MAX_REGION_NUM; id++) {
         if (!g_regionNumBeUsed[id]) {
             break;
         }
     }
-    HalIntRestore(intSave);
+    ArchIntRestore(intSave);
 
     if (id == MPU_MAX_REGION_NUM) {
         return -1;

arch/arm/cortex-m4/gcc/los_timer.c

@@ -33,38 +33,40 @@
 #include "los_config.h"
 #include "los_tick.h"
 #include "los_arch_interrupt.h"
-#include "los_context.h"
-#include "los_sched.h"
 #include "los_debug.h"
 
-/* ****************************************************************************
-Function    : HalTickStart
-Description : Configure Tick Interrupt Start
-Input       : none
-output      : none
-return      : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
-**************************************************************************** */
-WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC VOID SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+    .freq = 0,
+    .irqNum = SysTick_IRQn,
+    .init = SysTickStart,
+    .getCycle = SysTickCycleGet,
+    .reload = SysTickReload,
+    .lock = SysTickLock,
+    .unlock = SysTickUnlock,
+    .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
 {
     UINT32 ret;
+    ArchTickTimer *tick = &g_archTickTimer;
 
-    if ((OS_SYS_CLOCK == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND == 0) ||
-        (LOSCFG_BASE_CORE_TICK_PER_SECOND > OS_SYS_CLOCK)) {
-        return LOS_ERRNO_TICK_CFG_INVALID;
-    }
+    tick->freq = OS_SYS_CLOCK;
 
 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
-#if (OS_HWI_WITH_ARG == 1)
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler, NULL);
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+    OsSetVector(tick->irqNum, handler, NULL);
 #else
-    OsSetVector(SysTick_IRQn, (HWI_PROC_FUNC)handler);
+    OsSetVector(tick->irqNum, handler);
 #endif
 #endif
 
-    g_sysClock = OS_SYS_CLOCK;
-    g_cyclesPerTick = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
-
     ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
     if (ret == 1) {
         return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
@@ -73,7 +75,7 @@ WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
     return LOS_OK;
 }
 
-WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
+STATIC VOID SysTickReload(UINT64 nextResponseTime)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
     SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
@@ -82,27 +84,35 @@ WEAK VOID HalSysTickReload(UINT64 nextResponseTime)
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK UINT64 HalGetTickCycle(UINT32 *period)
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
 {
-    UINT32 hwCycle;
+    UINT32 hwCycle = 0;
     UINT32 intSave = LOS_IntLock();
+    UINT32 val = SysTick->VAL;
     *period = SysTick->LOAD;
-    hwCycle = *period - SysTick->VAL;
+    if (val != 0) {
+        hwCycle = *period - val;
+    }
     LOS_IntRestore(intSave);
     return (UINT64)hwCycle;
 }
 
-WEAK VOID HalTickLock(VOID)
+STATIC VOID SysTickLock(VOID)
 {
     SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
 }
 
-WEAK VOID HalTickUnlock(VOID)
+STATIC VOID SysTickUnlock(VOID)
 {
     SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 }
 
-UINT32 HalEnterSleep(VOID)
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+    return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
 {
     __DSB();
     __WFI();
@@ -110,3 +120,4 @@ UINT32 HalEnterSleep(VOID)
 
     return LOS_OK;
 }
+

arch/arm/cortex-m4/iar/los_arch_atomic.h

@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    INT32 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("ldrex   %0, [%1]\n"
+                         : "=&r"(val)
+                         : "r"(v)
+                         : "cc");
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    UINT32 status;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+
+    __asm__ __volatile__("1:ldrex   %0, [%2]\n"
+                         "  strex   %0, %3, [%2]\n"
+                         "  teq %0, #0\n"
+                         "  beq 1b"
+                         : "=&r"(status), "+m"(*v)
+                         : "r"(v), "r"(setVal)
+                         : "cc");
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "add   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "sub   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    return ArchAtomicSub(v, 1);
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable
+ * and return the previous value of the atomic variable.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The exchange value.
+ *
+ * @retval #INT32       The previous value of the atomic variable
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("ldrex   %0, [%3]\n"
+                             "strex   %1, %4, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal;
+}
+
+/**
+ * @ingroup  los_arch_atomic
+ * @brief Atomic exchange for 32-bit variable with compare.
+ *
+ * @par Description:
+ * This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
+ * @attention
+ * <ul>The pointer v must not be NULL.</ul>
+ *
+ * @param  v       [IN] The variable pointer.
+ * @param  val     [IN] The new value.
+ * @param  oldVal  [IN] The old value.
+ *
+ * @retval TRUE  The previous value of the atomic variable is not equal to oldVal.
+ * @retval FALSE The previous value of the atomic variable is equal to oldVal.
+ * @par Dependency:
+ * <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
+ * @see
+ */
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal = 0;
+    UINT32 status = 0;
+
+    do {
+        __asm__ __volatile__("1: ldrex %0, %2\n"
+                             "    mov %1, #0\n"
+                             "    cmp %0, %3\n"
+                             "    bne 2f\n"
+                             "    strex %1, %4, %2\n"
+                             "2:"
+                             : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
+                             : "r"(oldVal), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v = setVal;
+    LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v += addVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    *v -= subVal;
+    val = *v;
+    LOS_IntRestore(intSave);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    *v = val;
+    LOS_IntRestore(intSave);
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 intSave;
+
+    intSave = LOS_IntLock();
+    prevVal = *v;
+    if (prevVal == oldVal) {
+        *v = val;
+    }
+    LOS_IntRestore(intSave);
+
+    return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */