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Fix memory write enable in Decoder.scala

This commit is contained in:
Liphen 2023-12-06 15:14:41 +08:00
parent f6ac8ed72a
commit ecbaa40d88
2 changed files with 12 additions and 12 deletions
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2
chisel/playground/src/pipeline/decoder/Decoder.scala
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@ -58,5 +58,5 @@ class Decoder extends Module with HasInstrType {
) )
) )
io.out.info.inst := inst io.out.info.inst := inst
io.out.info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType) io.out.info.mem_wreg := fuType === FuType.lsu && io.out.info.reg_wen
} }

22
chisel/playground/src/pipeline/memory/MemoryStage.scala
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@ -7,21 +7,21 @@ import cpu.defines.Const._
import cpu.CpuConfig import cpu.CpuConfig
class ExeMemInst1 extends Bundle { class ExeMemInst1 extends Bundle {
val pc = UInt(PC_WID.W) val pc = UInt(PC_WID.W)
val info = new InstInfo() val info = new InstInfo()
val rd_info = new RdInfo() val rd_info = new RdInfo()
val ex = new ExceptionInfo() val ex = new ExceptionInfo()
} }
class ExeMemInst0(implicit val config: CpuConfig) extends ExeMemInst1 { class ExeMemInst0(implicit val config: CpuConfig) extends ExeMemInst1 {
val mem = new Bundle { val mem = new Bundle {
val en = Bool() val en = Bool()
val ren = Bool() val ren = Bool()
val wen = Bool() val wen = Bool()
val info = new InstInfo() val info = new InstInfo()
val addr = UInt(DATA_ADDR_WID.W) val addr = UInt(DATA_ADDR_WID.W)
val wdata = UInt(DATA_WID.W) val wdata = UInt(DATA_WID.W)
val sel = Vec(config.fuNum, Bool()) val sel = Vec(config.fuNum, Bool())
} }
} }