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perf: 将例外判断打包为函数

This commit is contained in:
Liphen 2023-12-06 14:50:59 +08:00
parent 5f75a0ac89
commit f6ac8ed72a
7 changed files with 29 additions and 51 deletions
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22
chisel/playground/src/defines/Util.scala
View File

@ -3,25 +3,9 @@ package cpu.defines
import chisel3._
import chisel3.util._
object SubwordModify {
def apply(source: UInt, start: Int, md: UInt): UInt = {
val ms = md.getWidth
apply(source, (start, start - ms + 1), md)
}
def apply(source: UInt, tuple: (Int, Int), md: UInt): UInt = {
val ws = source.getWidth
val ms = md.getWidth
val start = tuple._1
val end = tuple._2
require(
ws > start && start >= end && end >= 0,
s"ws: $ws, start: $start, end: $end"
)
require(start - end == ms - 1)
if (end == 0) Cat(source(ws - 1, start + 1), md)
else if (start == ws - 1) Cat(md, source(end - 1, 0))
else Cat(source(ws - 1, start + 1), md, source(end - 1, 0))
object HasExcInt {
def apply(ex: ExceptionInfo) = {
ex.exception.asUInt.orR || ex.interrupt.asUInt.orR
}
}

3
chisel/playground/src/pipeline/execute/Csr.scala
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@ -209,8 +209,7 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
// 优先使用inst0的信息
val exc_sel =
(io.memoryUnit.in.inst(0).ex.exception.asUInt.orR || io.memoryUnit.in.inst(0).ex.interrupt.asUInt.orR) ||
!(io.memoryUnit.in.inst(1).ex.exception.asUInt.orR || io.memoryUnit.in.inst(1).ex.interrupt.asUInt.orR)
(HasExcInt(io.memoryUnit.in.inst(0).ex)) || !(HasExcInt(io.memoryUnit.in.inst(1).ex))
val mem_pc = Mux(exc_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc)
val mem_ex = Mux(exc_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
val mem_inst_info = Mux(exc_sel, io.memoryUnit.in.inst(0).info, io.memoryUnit.in.inst(1).info)

25
chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
View File

@ -10,20 +10,20 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
val io = IO(new Bundle {
val mem = new Bundle {
val out = Output(new Bundle {
val en = Bool()
val ren = Bool()
val wen = Bool()
val info = new InstInfo()
val addr = UInt(DATA_ADDR_WID.W)
val wdata = UInt(DATA_WID.W)
val en = Bool()
val ren = Bool()
val wen = Bool()
val info = new InstInfo()
val addr = UInt(DATA_ADDR_WID.W)
val wdata = UInt(DATA_WID.W)
})
}
val inst = Vec(
config.fuNum,
new Bundle {
val info = Input(new InstInfo())
val src_info = Input(new SrcInfo())
val info = Input(new InstInfo())
val src_info = Input(new SrcInfo())
val ex = new Bundle {
val in = Input(new ExceptionInfo())
val out = Output(new ExceptionInfo())
@ -78,18 +78,15 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
io.inst(i).ex.out := io.inst(i).ex.in
io.inst(i).ex.out.exception(loadAddrMisaligned) := !store_inst && !addr_aligned(i)
io.inst(i).ex.out.exception(storeAddrMisaligned) := store_inst && !addr_aligned(i)
io.inst(i).ex.out.tval := Mux(
io.inst(i).ex.out.tval := Mux(
io.inst(i).ex.in.exception.asUInt.orR,
io.inst(i).ex.in.tval,
mem_addr(i)
)
}
io.inst(0).mem_sel := (io.inst(0).info.fusel === FuType.lsu) &&
!(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&
io.inst(0).info.valid
!(HasExcInt(io.inst(0).ex.out)) && io.inst(0).info.valid
io.inst(1).mem_sel := (io.inst(1).info.fusel === FuType.lsu) &&
!(io.inst(0).ex.out.exception.asUInt.orR || io.inst(0).ex.out.interrupt.asUInt.orR) &&
!(io.inst(1).ex.out.exception.asUInt.orR || io.inst(1).ex.out.interrupt.asUInt.orR) &&
io.inst(1).info.valid
!(HasExcInt(io.inst(0).ex.out)) && !(HasExcInt(io.inst(1).ex.out)) && io.inst(1).info.valid
}

12
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -48,9 +48,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
val is_csr = VecInit(
fusel(0) === FuType.csr && valid(0) &&
!(io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR),
!(HasExcInt(io.executeStage.inst0.ex)),
fusel(1) === FuType.csr && valid(1) &&
!(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR)
!(HasExcInt(io.executeStage.inst1.ex))
)
io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.info.mem_wreg
@ -84,9 +84,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
val is_lsu = VecInit(
fusel(0) === FuType.lsu && valid(0) &&
!(io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR),
!(HasExcInt(io.executeStage.inst0.ex)),
fusel(1) === FuType.lsu && valid(1) &&
!(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR)
!(HasExcInt(io.executeStage.inst1.ex))
)
// input accessMemCtrl
accessMemCtrl.inst(0).info := Mux(is_lsu(0), io.executeStage.inst0.info, 0.U.asTypeOf(new InstInfo()))
@ -135,7 +135,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.memoryStage.inst0.rd_info.wdata(FuType.lsu) := 0.U
io.memoryStage.inst0.rd_info.wdata(FuType.mou) := 0.U
val has_ex0 =
(io.executeStage.inst0.ex.exception.asUInt.orR || io.executeStage.inst0.ex.interrupt.asUInt.orR) && io.executeStage.inst0.info.valid
(HasExcInt(io.executeStage.inst0.ex)) && io.executeStage.inst0.info.valid
io.memoryStage.inst0.ex := Mux(
has_ex0,
io.executeStage.inst0.ex,
@ -160,7 +160,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.memoryStage.inst1.rd_info.wdata(FuType.lsu) := 0.U
io.memoryStage.inst1.rd_info.wdata(FuType.mou) := 0.U
val has_ex1 =
(io.executeStage.inst1.ex.exception.asUInt.orR || io.executeStage.inst1.ex.interrupt.asUInt.orR) && io.executeStage.inst1.info.valid
(HasExcInt(io.executeStage.inst1.ex)) && io.executeStage.inst1.info.valid
io.memoryStage.inst1.ex := Mux(
has_ex1,
io.executeStage.inst1.ex,

7
chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
View File

@ -26,7 +26,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
val memoryUnit = new Bundle {
val in = Input(new Bundle {
val mem_en = Bool()
val info = new InstInfo()
val info = new InstInfo()
val mem_wdata = UInt(DATA_WID.W)
val mem_addr = UInt(DATA_ADDR_WID.W)
val mem_sel = Vec(config.fuNum, Bool())
@ -47,10 +47,9 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
val op = io.memoryUnit.in.info.op
io.dataMemory.out.en := io.memoryUnit.in.mem_en &&
(io.memoryUnit.in.mem_sel(0) &&
!(io.memoryUnit.in.ex(0).exception.asUInt.orR || io.memoryUnit.in.ex(0).interrupt.asUInt.orR) ||
!(HasExcInt(io.memoryUnit.in.ex(0))) ||
io.memoryUnit.in.mem_sel(1) &&
!(io.memoryUnit.in.ex(0).exception.asUInt.orR || io.memoryUnit.in.ex(0).interrupt.asUInt.orR) &&
!(io.memoryUnit.in.ex(1).exception.asUInt.orR || io.memoryUnit.in.ex(1).interrupt.asUInt.orR))
!(HasExcInt(io.memoryUnit.in.ex(0))) && !(HasExcInt(io.memoryUnit.in.ex(1))))
io.dataMemory.out.addr := mem_addr
val rdata = LookupTree(
mem_addr(2, 0),

2
chisel/playground/src/pipeline/memory/MemoryUnit.scala
View File

@ -63,7 +63,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
io.writeBackStage.inst1.ex.exception(storeAccessFault) := io.memoryStage.inst0.mem.sel(1) &&
LSUOpType.isStore(io.memoryStage.inst1.info.op) && dataMemoryAccess.memoryUnit.out.acc_err
io.writeBackStage.inst1.commit := io.memoryStage.inst1.info.valid &&
!(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
!(HasExcInt(io.writeBackStage.inst0.ex))
io.csr.in.inst(0).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.pc, 0.U)
io.csr.in.inst(0).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.ex, 0.U.asTypeOf(new ExceptionInfo()))

9
chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
View File

@ -16,15 +16,14 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
})
io.regfile(0).wen := io.writeBackStage.inst0.info.reg_wen &&
io.ctrl.allow_to_go &&
!(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR)
io.ctrl.allow_to_go && !(HasExcInt(io.writeBackStage.inst0.ex))
io.regfile(0).waddr := io.writeBackStage.inst0.info.reg_waddr
io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
io.regfile(1).wen :=
io.writeBackStage.inst1.info.reg_wen && io.ctrl.allow_to_go &&
!(io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR) &&
!(io.writeBackStage.inst1.ex.exception.asUInt.orR || io.writeBackStage.inst1.ex.interrupt.asUInt.orR)
!(HasExcInt(io.writeBackStage.inst0.ex)) &&
!(HasExcInt(io.writeBackStage.inst1.ex))
io.regfile(1).waddr := io.writeBackStage.inst1.info.reg_waddr
io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
@ -49,7 +48,7 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
clock.asBool,
io.writeBackStage.inst0.pc,
Mux(
io.writeBackStage.inst0.ex.exception.asUInt.orR || io.writeBackStage.inst0.ex.interrupt.asUInt.orR,
HasExcInt(io.writeBackStage.inst0.ex),
0.U,
io.writeBackStage.inst1.pc
)