From ecbaa40d88ea64f60626fd8014a8d3ab1ee1c957 Mon Sep 17 00:00:00 2001 From: Liphen Date: Wed, 6 Dec 2023 15:14:41 +0800 Subject: [PATCH] Fix memory write enable in Decoder.scala --- .../src/pipeline/decoder/Decoder.scala | 2 +- .../src/pipeline/memory/MemoryStage.scala | 22 +++++++++---------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala index aa66bf3..a66fe1a 100644 --- a/chisel/playground/src/pipeline/decoder/Decoder.scala +++ b/chisel/playground/src/pipeline/decoder/Decoder.scala @@ -58,5 +58,5 @@ class Decoder extends Module with HasInstrType { ) ) io.out.info.inst := inst - io.out.info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType) + io.out.info.mem_wreg := fuType === FuType.lsu && io.out.info.reg_wen } diff --git a/chisel/playground/src/pipeline/memory/MemoryStage.scala b/chisel/playground/src/pipeline/memory/MemoryStage.scala index 9649486..67e70f5 100644 --- a/chisel/playground/src/pipeline/memory/MemoryStage.scala +++ b/chisel/playground/src/pipeline/memory/MemoryStage.scala @@ -7,21 +7,21 @@ import cpu.defines.Const._ import cpu.CpuConfig class ExeMemInst1 extends Bundle { - val pc = UInt(PC_WID.W) - val info = new InstInfo() - val rd_info = new RdInfo() - val ex = new ExceptionInfo() + val pc = UInt(PC_WID.W) + val info = new InstInfo() + val rd_info = new RdInfo() + val ex = new ExceptionInfo() } class ExeMemInst0(implicit val config: CpuConfig) extends ExeMemInst1 { val mem = new Bundle { - val en = Bool() - val ren = Bool() - val wen = Bool() - val info = new InstInfo() - val addr = UInt(DATA_ADDR_WID.W) - val wdata = UInt(DATA_WID.W) - val sel = Vec(config.fuNum, Bool()) + val en = Bool() + val ren = Bool() + val wen = Bool() + val info = new InstInfo() + val addr = UInt(DATA_ADDR_WID.W) + val wdata = UInt(DATA_WID.W) + val sel = Vec(config.fuNum, Bool()) } }