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fix(wb): 修改commit信号逻辑

This commit is contained in:
Liphen 2023-11-27 15:37:54 +08:00
parent b30026d57c
commit ca37a0a4ac
1 changed files with 2 additions and 2 deletions
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4
chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
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@ -29,11 +29,11 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
if (config.hasCommitBuffer) {
val buffer = Module(new CommitBuffer()).io
buffer.enq(0).wb_pc := io.writeBackStage.inst0.pc
buffer.enq(0).wb_rf_wen := io.regfile(0).wen || io.writeBackStage.inst0.commit
buffer.enq(0).wb_rf_wen := io.regfile(0).wen || io.writeBackStage.inst0.commit && io.ctrl.allow_to_go
buffer.enq(0).wb_rf_wnum := io.regfile(0).waddr
buffer.enq(0).wb_rf_wdata := io.regfile(0).wdata
buffer.enq(1).wb_pc := io.writeBackStage.inst1.pc
buffer.enq(1).wb_rf_wen := io.regfile(1).wen || io.writeBackStage.inst1.commit
buffer.enq(1).wb_rf_wen := io.regfile(1).wen || io.writeBackStage.inst1.commit && io.ctrl.allow_to_go
buffer.enq(1).wb_rf_wnum := io.regfile(1).waddr
buffer.enq(1).wb_rf_wdata := io.regfile(1).wdata
buffer.flush := io.ctrl.do_flush