diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 28b6ebc..38d80f1 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -29,11 +29,11 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
   if (config.hasCommitBuffer) {
     val buffer = Module(new CommitBuffer()).io
     buffer.enq(0).wb_pc       := io.writeBackStage.inst0.pc
-    buffer.enq(0).wb_rf_wen   := io.regfile(0).wen || io.writeBackStage.inst0.commit
+    buffer.enq(0).wb_rf_wen   := io.regfile(0).wen || io.writeBackStage.inst0.commit && io.ctrl.allow_to_go
     buffer.enq(0).wb_rf_wnum  := io.regfile(0).waddr
     buffer.enq(0).wb_rf_wdata := io.regfile(0).wdata
     buffer.enq(1).wb_pc       := io.writeBackStage.inst1.pc
-    buffer.enq(1).wb_rf_wen   := io.regfile(1).wen || io.writeBackStage.inst1.commit
+    buffer.enq(1).wb_rf_wen   := io.regfile(1).wen || io.writeBackStage.inst1.commit && io.ctrl.allow_to_go
     buffer.enq(1).wb_rf_wnum  := io.regfile(1).waddr
     buffer.enq(1).wb_rf_wdata := io.regfile(1).wdata
     buffer.flush              := io.ctrl.do_flush