From ca37a0a4ac0009b03ef818b1332e564778c94974 Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 27 Nov 2023 15:37:54 +0800 Subject: [PATCH] =?UTF-8?q?fix(wb):=20=E4=BF=AE=E6=94=B9commit=E4=BF=A1?= =?UTF-8?q?=E5=8F=B7=E9=80=BB=E8=BE=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/writeback/WriteBackUnit.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala index 28b6ebc..38d80f1 100644 --- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala +++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala @@ -29,11 +29,11 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module { if (config.hasCommitBuffer) { val buffer = Module(new CommitBuffer()).io buffer.enq(0).wb_pc := io.writeBackStage.inst0.pc - buffer.enq(0).wb_rf_wen := io.regfile(0).wen || io.writeBackStage.inst0.commit + buffer.enq(0).wb_rf_wen := io.regfile(0).wen || io.writeBackStage.inst0.commit && io.ctrl.allow_to_go buffer.enq(0).wb_rf_wnum := io.regfile(0).waddr buffer.enq(0).wb_rf_wdata := io.regfile(0).wdata buffer.enq(1).wb_pc := io.writeBackStage.inst1.pc - buffer.enq(1).wb_rf_wen := io.regfile(1).wen || io.writeBackStage.inst1.commit + buffer.enq(1).wb_rf_wen := io.regfile(1).wen || io.writeBackStage.inst1.commit && io.ctrl.allow_to_go buffer.enq(1).wb_rf_wnum := io.regfile(1).waddr buffer.enq(1).wb_rf_wdata := io.regfile(1).wdata buffer.flush := io.ctrl.do_flush