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exe访存时需要allow_to_go

This commit is contained in:
Liphen 2024-05-11 14:56:38 +08:00
parent 140dad44a8
commit b9f0def62e
1 changed files with 4 additions and 5 deletions
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9
chisel/playground/src/pipeline/execute/fu/Lsu.scala
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@ -14,6 +14,9 @@ class Lsu extends Module {
val dataSram = new DataSram() val dataSram = new DataSram()
}) })
val allow_to_go = Wire(Bool())
BoringUtils.addSink(allow_to_go, "exe_allow_to_go")
def genWmask(addr: UInt, sizeEncode: UInt): UInt = { def genWmask(addr: UInt, sizeEncode: UInt): UInt = {
LookupTree( LookupTree(
sizeEncode, sizeEncode,
@ -58,7 +61,7 @@ class Lsu extends Module {
) )
} }
val valid = io.info.valid && io.info.fusel === FuType.lsu // && 无异常 val valid = io.info.valid && io.info.fusel === FuType.lsu && allow_to_go// && 无异常
val op = io.info.op val op = io.info.op
val is_load = valid && LSUOpType.isLoad(op) val is_load = valid && LSUOpType.isLoad(op)
val is_store = valid && LSUOpType.isStore(op) val is_store = valid && LSUOpType.isStore(op)
@ -114,10 +117,6 @@ class Lsu extends Module {
"b11".U -> (addr(2, 0) === 0.U) //d "b11".U -> (addr(2, 0) === 0.U) //d
) )
) )
val allow_to_go = Wire(Bool())
BoringUtils.addSink(allow_to_go, "exe_allow_to_go")
val addr_last = RegEnable(addr, allow_to_go) val addr_last = RegEnable(addr, allow_to_go)
io.dataSram.en := valid && addr_aligned io.dataSram.en := valid && addr_aligned