From b9f0def62e8e17f5e709bb73d4e60960b20f22e3 Mon Sep 17 00:00:00 2001 From: Liphen Date: Sat, 11 May 2024 14:56:38 +0800 Subject: [PATCH] =?UTF-8?q?exe=E8=AE=BF=E5=AD=98=E6=97=B6=E9=9C=80?= =?UTF-8?q?=E8=A6=81allow=5Fto=5Fgo?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/fu/Lsu.scala | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/chisel/playground/src/pipeline/execute/fu/Lsu.scala b/chisel/playground/src/pipeline/execute/fu/Lsu.scala index 4e0ee48..73009df 100644 --- a/chisel/playground/src/pipeline/execute/fu/Lsu.scala +++ b/chisel/playground/src/pipeline/execute/fu/Lsu.scala @@ -14,6 +14,9 @@ class Lsu extends Module { val dataSram = new DataSram() }) + val allow_to_go = Wire(Bool()) + BoringUtils.addSink(allow_to_go, "exe_allow_to_go") + def genWmask(addr: UInt, sizeEncode: UInt): UInt = { LookupTree( sizeEncode, @@ -58,7 +61,7 @@ class Lsu extends Module { ) } - val valid = io.info.valid && io.info.fusel === FuType.lsu // && 无异常 + val valid = io.info.valid && io.info.fusel === FuType.lsu && allow_to_go// && 无异常 val op = io.info.op val is_load = valid && LSUOpType.isLoad(op) val is_store = valid && LSUOpType.isStore(op) @@ -114,10 +117,6 @@ class Lsu extends Module { "b11".U -> (addr(2, 0) === 0.U) //d ) ) - - val allow_to_go = Wire(Bool()) - BoringUtils.addSink(allow_to_go, "exe_allow_to_go") - val addr_last = RegEnable(addr, allow_to_go) io.dataSram.en := valid && addr_aligned